Commit | Line | Data |
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cc26b3b0 SMK |
1 | /* |
2 | * linux/arch/arm/mach-omap3/sram.S | |
3 | * | |
4 | * Omap3 specific functions that need to be run in internal SRAM | |
5 | * | |
4267b5d1 PW |
6 | * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. |
7 | * Copyright (C) 2008 Nokia Corporation | |
cc26b3b0 | 8 | * |
4267b5d1 | 9 | * Rajendra Nayak <rnayak@ti.com> |
cc26b3b0 | 10 | * Richard Woodruff <r-woodruff2@ti.com> |
4267b5d1 | 11 | * Paul Walmsley |
cc26b3b0 SMK |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | #include <linux/linkage.h> | |
ee0839c2 | 29 | |
cc26b3b0 | 30 | #include <asm/assembler.h> |
cc26b3b0 | 31 | |
dbc04161 | 32 | #include "soc.h" |
ee0839c2 | 33 | #include "iomap.h" |
cc26b3b0 | 34 | #include "sdrc.h" |
ff4ae5d9 | 35 | #include "cm3xxx.h" |
cc26b3b0 | 36 | |
ef7a87d3 DM |
37 | /* |
38 | * This file needs be built unconditionally as ARM to interoperate correctly | |
39 | * with non-Thumb-2-capable firmware. | |
40 | */ | |
41 | .arm | |
42 | ||
cc26b3b0 SMK |
43 | .text |
44 | ||
58cda884 | 45 | /* r1 parameters */ |
df14e474 PW |
46 | #define SDRC_NO_UNLOCK_DLL 0x0 |
47 | #define SDRC_UNLOCK_DLL 0x1 | |
48 | ||
49 | /* SDRC_DLLA_CTRL bit settings */ | |
7b7bcefa PW |
50 | #define FIXEDDELAY_SHIFT 24 |
51 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) | |
df14e474 PW |
52 | #define DLLIDLE_MASK 0x4 |
53 | ||
7b7bcefa PW |
54 | /* |
55 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that | |
56 | * FIXEDDELAY should be initialized to 0xf. This apparently was | |
57 | * empirically determined during process testing, so no derivation | |
58 | * was provided. | |
59 | */ | |
60 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) | |
61 | ||
df14e474 PW |
62 | /* SDRC_DLLA_STATUS bit settings */ |
63 | #define LOCKSTATUS_MASK 0x4 | |
64 | ||
65 | /* SDRC_POWER bit settings */ | |
66 | #define SRFRONIDLEREQ_MASK 0x40 | |
df14e474 PW |
67 | |
68 | /* CM_IDLEST1_CORE bit settings */ | |
69 | #define ST_SDRC_MASK 0x2 | |
70 | ||
71 | /* CM_ICLKEN1_CORE bit settings */ | |
72 | #define EN_SDRC_MASK 0x2 | |
73 | ||
74 | /* CM_CLKSEL1_PLL bit settings */ | |
75 | #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b | |
76 | ||
cc26b3b0 | 77 | /* |
4267b5d1 | 78 | * omap3_sram_configure_core_dpll - change DPLL3 M2 divider |
58cda884 JP |
79 | * |
80 | * Params passed in registers: | |
81 | * r0 = new M2 divider setting (only 1 and 2 supported right now) | |
82 | * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for | |
4519c2bf | 83 | * SDRC rates < 83MHz |
58cda884 | 84 | * r2 = number of MPU cycles to wait for SDRC to stabilize after |
c9812d04 | 85 | * reprogramming the SDRC when switching to a slower MPU speed |
58cda884 JP |
86 | * r3 = increasing SDRC rate? (1 = yes, 0 = no) |
87 | * | |
88 | * Params passed via the stack. The needed params will be copied in SRAM | |
89 | * before use by the code in SRAM (SDRAM is not accessible during SDRC | |
90 | * reconfiguration): | |
91 | * new SDRC_RFR_CTRL_0 register contents | |
92 | * new SDRC_ACTIM_CTRL_A_0 register contents | |
93 | * new SDRC_ACTIM_CTRL_B_0 register contents | |
94 | * new SDRC_MR_0 register value | |
95 | * new SDRC_RFR_CTRL_1 register contents | |
96 | * new SDRC_ACTIM_CTRL_A_1 register contents | |
97 | * new SDRC_ACTIM_CTRL_B_1 register contents | |
98 | * new SDRC_MR_1 register value | |
c9812d04 | 99 | * |
18862cbe PW |
100 | * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into |
101 | * the SDRC CS1 registers | |
102 | * | |
103 | * NOTE: This code no longer attempts to program the SDRC AC timing and MR | |
104 | * registers. This is because the code currently cannot ensure that all | |
105 | * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the | |
106 | * SDRAM when the registers are written. If the registers are changed while | |
107 | * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC | |
108 | * may enter an unpredictable state. In the future, the intent is to | |
109 | * re-enable this code in cases where we can ensure that no initiators are | |
110 | * touching the SDRAM. Until that time, users who know that their use case | |
111 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING | |
112 | * option. | |
1124d2f9 PW |
113 | * |
114 | * Richard Woodruff notes that any changes to this code must be carefully | |
115 | * audited and tested to ensure that they don't cause a TLB miss while | |
116 | * the SDRAM is inaccessible. Such a situation will crash the system | |
117 | * since it will cause the ARM MMU to attempt to walk the page tables. | |
118 | * These crashes may be intermittent. | |
cc26b3b0 | 119 | */ |
b6338bdc | 120 | .align 3 |
cc26b3b0 SMK |
121 | ENTRY(omap3_sram_configure_core_dpll) |
122 | stmfd sp!, {r1-r12, lr} @ store regs to stack | |
58cda884 JP |
123 | |
124 | @ pull the extra args off the stack | |
125 | @ and store them in SRAM | |
ef7a87d3 DM |
126 | |
127 | /* | |
128 | * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour | |
129 | * in Thumb-2: use a r7 as a base instead. | |
130 | * Be careful not to clobber r7 when maintaing this file. | |
131 | */ | |
132 | THUMB( adr r7, omap3_sram_configure_core_dpll ) | |
133 | .macro strtext Rt:req, label:req | |
134 | ARM( str \Rt, \label ) | |
135 | THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] ) | |
136 | .endm | |
137 | ||
58cda884 | 138 | ldr r4, [sp, #52] |
ef7a87d3 | 139 | strtext r4, omap_sdrc_rfr_ctrl_0_val |
58cda884 | 140 | ldr r4, [sp, #56] |
ef7a87d3 | 141 | strtext r4, omap_sdrc_actim_ctrl_a_0_val |
58cda884 | 142 | ldr r4, [sp, #60] |
ef7a87d3 | 143 | strtext r4, omap_sdrc_actim_ctrl_b_0_val |
58cda884 | 144 | ldr r4, [sp, #64] |
ef7a87d3 | 145 | strtext r4, omap_sdrc_mr_0_val |
58cda884 | 146 | ldr r4, [sp, #68] |
ef7a87d3 | 147 | strtext r4, omap_sdrc_rfr_ctrl_1_val |
58cda884 JP |
148 | cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, |
149 | beq skip_cs1_params @ do not use cs1 params | |
150 | ldr r4, [sp, #72] | |
ef7a87d3 | 151 | strtext r4, omap_sdrc_actim_ctrl_a_1_val |
58cda884 | 152 | ldr r4, [sp, #76] |
ef7a87d3 | 153 | strtext r4, omap_sdrc_actim_ctrl_b_1_val |
58cda884 | 154 | ldr r4, [sp, #80] |
ef7a87d3 | 155 | strtext r4, omap_sdrc_mr_1_val |
58cda884 | 156 | skip_cs1_params: |
a3fed9bc JH |
157 | mrc p15, 0, r8, c1, c0, 0 @ read ctrl register |
158 | bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction | |
159 | mcr p15, 0, r10, c1, c0, 0 @ write ctrl register | |
69d4255b | 160 | dsb @ flush buffered writes to interconnect |
a3fed9bc | 161 | isb @ prevent speculative exec past here |
58cda884 | 162 | cmp r3, #1 @ if increasing SDRC clk rate, |
3afec633 | 163 | bleq configure_sdrc @ program the SDRC regs early (for RFR) |
58cda884 | 164 | cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state |
4519c2bf | 165 | bleq unlock_dll |
cc26b3b0 | 166 | blne lock_dll |
4267b5d1 PW |
167 | bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC |
168 | bl configure_core_dpll @ change the DPLL3 M2 divider | |
df56556e RN |
169 | mov r12, r2 |
170 | bl wait_clk_stable @ wait for SDRC to stabilize | |
4267b5d1 | 171 | bl enable_sdrc @ take SDRC out of idle |
58cda884 | 172 | cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change |
4519c2bf | 173 | bleq wait_dll_unlock |
cc26b3b0 | 174 | blne wait_dll_lock |
58cda884 | 175 | cmp r3, #1 @ if increasing SDRC clk rate, |
4267b5d1 PW |
176 | beq return_to_sdram @ return to SDRAM code, otherwise, |
177 | bl configure_sdrc @ reprogram SDRC regs now | |
c9812d04 | 178 | return_to_sdram: |
a3fed9bc | 179 | mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register |
69d4255b | 180 | isb @ prevent speculative exec past here |
cc26b3b0 SMK |
181 | mov r0, #0 @ return value |
182 | ldmfd sp!, {r1-r12, pc} @ restore regs and return | |
183 | unlock_dll: | |
b2abb271 PW |
184 | ldr r11, omap3_sdrc_dlla_ctrl |
185 | ldr r12, [r11] | |
8ff120e5 | 186 | bic r12, r12, #FIXEDDELAY_MASK |
7b7bcefa | 187 | orr r12, r12, #FIXEDDELAY_DEFAULT |
df14e474 | 188 | orr r12, r12, #DLLIDLE_MASK |
b2abb271 | 189 | str r12, [r11] @ (no OCP barrier needed) |
cc26b3b0 SMK |
190 | bx lr |
191 | lock_dll: | |
b2abb271 PW |
192 | ldr r11, omap3_sdrc_dlla_ctrl |
193 | ldr r12, [r11] | |
df14e474 | 194 | bic r12, r12, #DLLIDLE_MASK |
b2abb271 | 195 | str r12, [r11] @ (no OCP barrier needed) |
cc26b3b0 SMK |
196 | bx lr |
197 | sdram_in_selfrefresh: | |
b2abb271 PW |
198 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
199 | ldr r12, [r11] @ read the contents of SDRC_POWER | |
200 | mov r9, r12 @ keep a copy of SDRC_POWER bits | |
df14e474 | 201 | orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle |
b2abb271 PW |
202 | str r12, [r11] @ write back to SDRC_POWER register |
203 | ldr r12, [r11] @ posted-write barrier for SDRC | |
4267b5d1 | 204 | idle_sdrc: |
b2abb271 PW |
205 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
206 | ldr r12, [r11] | |
df14e474 | 207 | bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC |
b2abb271 | 208 | str r12, [r11] |
cc26b3b0 | 209 | wait_sdrc_idle: |
b2abb271 PW |
210 | ldr r11, omap3_cm_idlest1_core |
211 | ldr r12, [r11] | |
df14e474 PW |
212 | and r12, r12, #ST_SDRC_MASK @ check for SDRC idle |
213 | cmp r12, #ST_SDRC_MASK | |
cc26b3b0 SMK |
214 | bne wait_sdrc_idle |
215 | bx lr | |
216 | configure_core_dpll: | |
b2abb271 PW |
217 | ldr r11, omap3_cm_clksel1_pll |
218 | ldr r12, [r11] | |
219 | ldr r10, core_m2_mask_val @ modify m2 for core dpll | |
220 | and r12, r12, r10 | |
58cda884 | 221 | orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT |
b2abb271 PW |
222 | str r12, [r11] |
223 | ldr r12, [r11] @ posted-write barrier for CM | |
cc26b3b0 SMK |
224 | bx lr |
225 | wait_clk_stable: | |
b2abb271 | 226 | subs r12, r12, #1 |
cc26b3b0 | 227 | bne wait_clk_stable |
cc26b3b0 SMK |
228 | bx lr |
229 | enable_sdrc: | |
b2abb271 PW |
230 | ldr r11, omap3_cm_iclken1_core |
231 | ldr r12, [r11] | |
df14e474 | 232 | orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC |
b2abb271 | 233 | str r12, [r11] |
cc26b3b0 | 234 | wait_sdrc_idle1: |
b2abb271 PW |
235 | ldr r11, omap3_cm_idlest1_core |
236 | ldr r12, [r11] | |
df14e474 | 237 | and r12, r12, #ST_SDRC_MASK |
b2abb271 | 238 | cmp r12, #0 |
cc26b3b0 | 239 | bne wait_sdrc_idle1 |
fa0406a8 | 240 | restore_sdrc_power_val: |
b2abb271 PW |
241 | ldr r11, omap3_sdrc_power |
242 | str r9, [r11] @ restore SDRC_POWER, no barrier needed | |
cc26b3b0 SMK |
243 | bx lr |
244 | wait_dll_lock: | |
b2abb271 PW |
245 | ldr r11, omap3_sdrc_dlla_status |
246 | ldr r12, [r11] | |
df14e474 PW |
247 | and r12, r12, #LOCKSTATUS_MASK |
248 | cmp r12, #LOCKSTATUS_MASK | |
cc26b3b0 SMK |
249 | bne wait_dll_lock |
250 | bx lr | |
251 | wait_dll_unlock: | |
b2abb271 PW |
252 | ldr r11, omap3_sdrc_dlla_status |
253 | ldr r12, [r11] | |
df14e474 | 254 | and r12, r12, #LOCKSTATUS_MASK |
b2abb271 | 255 | cmp r12, #0x0 |
cc26b3b0 SMK |
256 | bne wait_dll_unlock |
257 | bx lr | |
258 | configure_sdrc: | |
58cda884 JP |
259 | ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM |
260 | ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM | |
261 | str r12, [r11] @ store | |
18862cbe | 262 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
58cda884 JP |
263 | ldr r12, omap_sdrc_actim_ctrl_a_0_val |
264 | ldr r11, omap3_sdrc_actim_ctrl_a_0 | |
265 | str r12, [r11] | |
266 | ldr r12, omap_sdrc_actim_ctrl_b_0_val | |
267 | ldr r11, omap3_sdrc_actim_ctrl_b_0 | |
268 | str r12, [r11] | |
269 | ldr r12, omap_sdrc_mr_0_val | |
d0ba3922 | 270 | ldr r11, omap3_sdrc_mr_0 |
58cda884 | 271 | str r12, [r11] |
18862cbe | 272 | #endif |
58cda884 JP |
273 | ldr r12, omap_sdrc_rfr_ctrl_1_val |
274 | cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, | |
275 | beq skip_cs1_prog @ do not program cs1 params | |
276 | ldr r11, omap3_sdrc_rfr_ctrl_1 | |
277 | str r12, [r11] | |
18862cbe | 278 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
58cda884 JP |
279 | ldr r12, omap_sdrc_actim_ctrl_a_1_val |
280 | ldr r11, omap3_sdrc_actim_ctrl_a_1 | |
281 | str r12, [r11] | |
282 | ldr r12, omap_sdrc_actim_ctrl_b_1_val | |
283 | ldr r11, omap3_sdrc_actim_ctrl_b_1 | |
284 | str r12, [r11] | |
285 | ldr r12, omap_sdrc_mr_1_val | |
286 | ldr r11, omap3_sdrc_mr_1 | |
287 | str r12, [r11] | |
18862cbe | 288 | #endif |
58cda884 JP |
289 | skip_cs1_prog: |
290 | ldr r12, [r11] @ posted-write barrier for SDRC | |
cc26b3b0 SMK |
291 | bx lr |
292 | ||
ef7a87d3 | 293 | .align |
cc26b3b0 SMK |
294 | omap3_sdrc_power: |
295 | .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) | |
296 | omap3_cm_clksel1_pll: | |
297 | .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1) | |
298 | omap3_cm_idlest1_core: | |
299 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) | |
300 | omap3_cm_iclken1_core: | |
301 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) | |
58cda884 JP |
302 | |
303 | omap3_sdrc_rfr_ctrl_0: | |
cc26b3b0 | 304 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
58cda884 JP |
305 | omap3_sdrc_rfr_ctrl_1: |
306 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1) | |
307 | omap3_sdrc_actim_ctrl_a_0: | |
cc26b3b0 | 308 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) |
58cda884 JP |
309 | omap3_sdrc_actim_ctrl_a_1: |
310 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1) | |
311 | omap3_sdrc_actim_ctrl_b_0: | |
cc26b3b0 | 312 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) |
58cda884 JP |
313 | omap3_sdrc_actim_ctrl_b_1: |
314 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1) | |
d0ba3922 PW |
315 | omap3_sdrc_mr_0: |
316 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) | |
58cda884 JP |
317 | omap3_sdrc_mr_1: |
318 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1) | |
319 | omap_sdrc_rfr_ctrl_0_val: | |
320 | .word 0xDEADBEEF | |
321 | omap_sdrc_rfr_ctrl_1_val: | |
322 | .word 0xDEADBEEF | |
323 | omap_sdrc_actim_ctrl_a_0_val: | |
324 | .word 0xDEADBEEF | |
325 | omap_sdrc_actim_ctrl_a_1_val: | |
326 | .word 0xDEADBEEF | |
327 | omap_sdrc_actim_ctrl_b_0_val: | |
328 | .word 0xDEADBEEF | |
329 | omap_sdrc_actim_ctrl_b_1_val: | |
330 | .word 0xDEADBEEF | |
331 | omap_sdrc_mr_0_val: | |
332 | .word 0xDEADBEEF | |
333 | omap_sdrc_mr_1_val: | |
334 | .word 0xDEADBEEF | |
335 | ||
cc26b3b0 SMK |
336 | omap3_sdrc_dlla_status: |
337 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) | |
338 | omap3_sdrc_dlla_ctrl: | |
339 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | |
340 | core_m2_mask_val: | |
341 | .word 0x07FFFFFF | |
ef7a87d3 | 342 | ENDPROC(omap3_sram_configure_core_dpll) |
cc26b3b0 SMK |
343 | |
344 | ENTRY(omap3_sram_configure_core_dpll_sz) | |
345 | .word . - omap3_sram_configure_core_dpll | |
58cda884 | 346 |