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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0c0a5d61 TG |
2 | /* |
3 | * OMAP3/OMAP4 smartreflex device file | |
4 | * | |
5 | * Author: Thara Gopinath <thara@ti.com> | |
6 | * | |
7 | * Based originally on code from smartreflex.c | |
8 | * Copyright (C) 2010 Texas Instruments, Inc. | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * Copyright (C) 2008 Nokia Corporation | |
12 | * Kalle Jokiniemi | |
13 | * | |
14 | * Copyright (C) 2007 Texas Instruments, Inc. | |
15 | * Lesly A M <x0080970@ti.com> | |
0c0a5d61 | 16 | */ |
b86aeafc | 17 | #include <linux/power/smartreflex.h> |
0c0a5d61 TG |
18 | |
19 | #include <linux/err.h> | |
20 | #include <linux/slab.h> | |
b35cecf9 | 21 | #include <linux/io.h> |
0c0a5d61 | 22 | |
e4c060db | 23 | #include "soc.h" |
25c7d49e | 24 | #include "omap_device.h" |
e1d6f472 | 25 | #include "voltage.h" |
0c0a5d61 | 26 | #include "control.h" |
d0eadf6d | 27 | #include "pm.h" |
0c0a5d61 | 28 | |
0c0a5d61 TG |
29 | /* Read EFUSE values from control registers for OMAP3430 */ |
30 | static void __init sr_set_nvalues(struct omap_volt_data *volt_data, | |
31 | struct omap_sr_data *sr_data) | |
32 | { | |
33 | struct omap_sr_nvalue_table *nvalue_table; | |
5e7f2e12 JP |
34 | int i, j, count = 0; |
35 | ||
36 | sr_data->nvalue_count = 0; | |
37 | sr_data->nvalue_table = NULL; | |
0c0a5d61 TG |
38 | |
39 | while (volt_data[count].volt_nominal) | |
40 | count++; | |
41 | ||
6b72de4d | 42 | nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL); |
c76e4d2e | 43 | if (!nvalue_table) |
5e7f2e12 | 44 | return; |
5e7f2e12 JP |
45 | |
46 | for (i = 0, j = 0; i < count; i++) { | |
b35cecf9 | 47 | u32 v; |
5e7f2e12 | 48 | |
b35cecf9 TG |
49 | /* |
50 | * In OMAP4 the efuse registers are 24 bit aligned. | |
edfaf05c | 51 | * A readl_relaxed will fail for non-32 bit aligned address |
b35cecf9 TG |
52 | * and hence the 8-bit read and shift. |
53 | */ | |
54 | if (cpu_is_omap44xx()) { | |
55 | u16 offset = volt_data[i].sr_efuse_offs; | |
56 | ||
57 | v = omap_ctrl_readb(offset) | | |
58 | omap_ctrl_readb(offset + 1) << 8 | | |
59 | omap_ctrl_readb(offset + 2) << 16; | |
60 | } else { | |
5e7f2e12 | 61 | v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); |
b35cecf9 | 62 | } |
0c0a5d61 | 63 | |
5e7f2e12 JP |
64 | /* |
65 | * Many OMAP SoCs don't have the eFuse values set. | |
66 | * For example, pretty much all OMAP3xxx before | |
67 | * ES3.something. | |
68 | * | |
69 | * XXX There needs to be some way for board files or | |
70 | * userspace to add these in. | |
71 | */ | |
72 | if (v == 0) | |
73 | continue; | |
74 | ||
75 | nvalue_table[j].nvalue = v; | |
76 | nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs; | |
77 | nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit; | |
78 | nvalue_table[j].volt_nominal = volt_data[i].volt_nominal; | |
79 | ||
80 | j++; | |
0c0a5d61 TG |
81 | } |
82 | ||
83 | sr_data->nvalue_table = nvalue_table; | |
5e7f2e12 | 84 | sr_data->nvalue_count = j; |
0c0a5d61 TG |
85 | } |
86 | ||
d060b405 TL |
87 | extern struct omap_sr_data omap_sr_pdata[]; |
88 | ||
fbfa463b | 89 | static int __init sr_init_by_name(const char *name, const char *voltdm) |
0c0a5d61 | 90 | { |
695eea3d | 91 | struct omap_sr_data *sr_data = NULL; |
0c0a5d61 | 92 | struct omap_volt_data *volt_data; |
0c0a5d61 TG |
93 | static int i; |
94 | ||
fbfa463b TL |
95 | if (!strncmp(name, "smartreflex_mpu_iva", 20) || |
96 | !strncmp(name, "smartreflex_mpu", 16)) | |
695eea3d | 97 | sr_data = &omap_sr_pdata[OMAP_SR_MPU]; |
fbfa463b | 98 | else if (!strncmp(name, "smartreflex_core", 17)) |
695eea3d | 99 | sr_data = &omap_sr_pdata[OMAP_SR_CORE]; |
fbfa463b | 100 | else if (!strncmp(name, "smartreflex_iva", 16)) |
695eea3d TL |
101 | sr_data = &omap_sr_pdata[OMAP_SR_IVA]; |
102 | ||
103 | if (!sr_data) { | |
fbfa463b | 104 | pr_err("%s: Unknown instance %s\n", __func__, name); |
695eea3d TL |
105 | return -EINVAL; |
106 | } | |
0c0a5d61 | 107 | |
fbfa463b | 108 | sr_data->name = name; |
70451127 TL |
109 | if (cpu_is_omap343x()) |
110 | sr_data->ip_type = 1; | |
111 | else | |
112 | sr_data->ip_type = 2; | |
0c0a5d61 TG |
113 | sr_data->senn_mod = 0x1; |
114 | sr_data->senp_mod = 0x1; | |
115 | ||
98aed08e JP |
116 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
117 | sr_data->err_weight = OMAP3430_SR_ERRWEIGHT; | |
118 | sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT; | |
119 | sr_data->accum_data = OMAP3430_SR_ACCUMDATA; | |
120 | if (!(strcmp(sr_data->name, "smartreflex_mpu"))) { | |
121 | sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT; | |
122 | sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT; | |
123 | } else { | |
124 | sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT; | |
125 | sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT; | |
126 | } | |
127 | } | |
128 | ||
fbfa463b | 129 | sr_data->voltdm = voltdm_lookup(voltdm); |
07684c1b | 130 | if (!sr_data->voltdm) { |
0c0a5d61 | 131 | pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", |
fbfa463b | 132 | __func__, voltdm); |
0c0a5d61 TG |
133 | goto exit; |
134 | } | |
135 | ||
136 | omap_voltage_get_volttable(sr_data->voltdm, &volt_data); | |
137 | if (!volt_data) { | |
7852ec05 PW |
138 | pr_err("%s: No Voltage table registered for VDD%d\n", |
139 | __func__, i + 1); | |
0c0a5d61 TG |
140 | goto exit; |
141 | } | |
142 | ||
143 | sr_set_nvalues(volt_data, sr_data); | |
144 | ||
0c0a5d61 TG |
145 | exit: |
146 | i++; | |
695eea3d | 147 | |
0c0a5d61 TG |
148 | return 0; |
149 | } | |
150 | ||
f21af425 | 151 | #ifdef CONFIG_OMAP_HWMOD |
fbfa463b TL |
152 | static int __init sr_dev_init(struct omap_hwmod *oh, void *user) |
153 | { | |
154 | struct omap_smartreflex_dev_attr *sr_dev_attr; | |
155 | ||
156 | sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; | |
157 | if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { | |
158 | pr_err("%s: No voltage domain specified for %s. Cannot initialize\n", | |
159 | __func__, oh->name); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name); | |
164 | } | |
f21af425 TL |
165 | #else |
166 | static int __init sr_dev_init(struct omap_hwmod *oh, void *user) | |
167 | { | |
168 | return -EINVAL; | |
169 | } | |
170 | #endif | |
fbfa463b | 171 | |
fbfa463b TL |
172 | static const char * const omap4_sr_instances[] = { |
173 | "mpu", | |
174 | "iva", | |
175 | "core", | |
176 | }; | |
177 | ||
178 | static const char * const dra7_sr_instances[] = { | |
179 | "mpu", | |
180 | "core", | |
181 | }; | |
182 | ||
0c0a5d61 TG |
183 | int __init omap_devinit_smartreflex(void) |
184 | { | |
fc85dc42 | 185 | const char * const *sr_inst = NULL; |
fbfa463b TL |
186 | int i, nr_sr = 0; |
187 | ||
188 | if (soc_is_omap44xx()) { | |
189 | sr_inst = omap4_sr_instances; | |
190 | nr_sr = ARRAY_SIZE(omap4_sr_instances); | |
191 | ||
192 | } else if (soc_is_dra7xx()) { | |
193 | sr_inst = dra7_sr_instances; | |
194 | nr_sr = ARRAY_SIZE(dra7_sr_instances); | |
195 | } | |
196 | ||
197 | if (nr_sr) { | |
198 | const char *name, *voltdm; | |
199 | ||
200 | for (i = 0; i < nr_sr; i++) { | |
201 | name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]); | |
202 | voltdm = sr_inst[i]; | |
203 | sr_init_by_name(name, voltdm); | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
0c0a5d61 TG |
209 | return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL); |
210 | } |