Commit | Line | Data |
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984aa6db TG |
1 | /* |
2 | * OMAP SmartReflex Voltage Control | |
3 | * | |
4 | * Author: Thara Gopinath <thara@ti.com> | |
5 | * | |
6 | * Copyright (C) 2010 Texas Instruments, Inc. | |
7 | * Thara Gopinath <thara@ti.com> | |
8 | * | |
9 | * Copyright (C) 2008 Nokia Corporation | |
10 | * Kalle Jokiniemi | |
11 | * | |
12 | * Copyright (C) 2007 Texas Instruments, Inc. | |
13 | * Lesly A M <x0080970@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
a1bcc1dc | 20 | #include <linux/module.h> |
984aa6db TG |
21 | #include <linux/interrupt.h> |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/pm_runtime.h> | |
b86aeafc | 28 | #include <linux/power/smartreflex.h> |
984aa6db | 29 | |
4e65331c | 30 | #include "common.h" |
984aa6db TG |
31 | #include "pm.h" |
32 | ||
33 | #define SMARTREFLEX_NAME_LEN 16 | |
077fceca | 34 | #define NVALUE_NAME_LEN 40 |
984aa6db TG |
35 | #define SR_DISABLE_TIMEOUT 200 |
36 | ||
984aa6db TG |
37 | /* sr_list contains all the instances of smartreflex module */ |
38 | static LIST_HEAD(sr_list); | |
39 | ||
40 | static struct omap_sr_class_data *sr_class; | |
41 | static struct omap_sr_pmic_data *sr_pmic_data; | |
633ef8b7 | 42 | static struct dentry *sr_dbg_dir; |
984aa6db TG |
43 | |
44 | static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value) | |
45 | { | |
46 | __raw_writel(value, (sr->base + offset)); | |
47 | } | |
48 | ||
49 | static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask, | |
50 | u32 value) | |
51 | { | |
52 | u32 reg_val; | |
984aa6db TG |
53 | |
54 | /* | |
55 | * Smartreflex error config register is special as it contains | |
56 | * certain status bits which if written a 1 into means a clear | |
57 | * of those bits. So in order to make sure no accidental write of | |
58 | * 1 happens to those status bits, do a clear of them in the read | |
59 | * value. This mean this API doesn't rewrite values in these bits | |
60 | * if they are currently set, but does allow the caller to write | |
61 | * those bits. | |
62 | */ | |
ade6ec05 NM |
63 | if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1) |
64 | mask |= ERRCONFIG_STATUS_V1_MASK; | |
65 | else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2) | |
66 | mask |= ERRCONFIG_VPBOUNDINTST_V2; | |
67 | ||
68 | reg_val = __raw_readl(sr->base + offset); | |
69 | reg_val &= ~mask; | |
984aa6db | 70 | |
ade6ec05 | 71 | value &= mask; |
984aa6db TG |
72 | |
73 | reg_val |= value; | |
74 | ||
75 | __raw_writel(reg_val, (sr->base + offset)); | |
76 | } | |
77 | ||
78 | static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset) | |
79 | { | |
80 | return __raw_readl(sr->base + offset); | |
81 | } | |
82 | ||
83 | static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm) | |
84 | { | |
85 | struct omap_sr *sr_info; | |
86 | ||
87 | if (!voltdm) { | |
88 | pr_err("%s: Null voltage domain passed!\n", __func__); | |
89 | return ERR_PTR(-EINVAL); | |
90 | } | |
91 | ||
92 | list_for_each_entry(sr_info, &sr_list, node) { | |
93 | if (voltdm == sr_info->voltdm) | |
94 | return sr_info; | |
95 | } | |
96 | ||
97 | return ERR_PTR(-ENODATA); | |
98 | } | |
99 | ||
100 | static irqreturn_t sr_interrupt(int irq, void *data) | |
101 | { | |
4018bfeb | 102 | struct omap_sr *sr_info = data; |
984aa6db TG |
103 | u32 status = 0; |
104 | ||
4018bfeb FB |
105 | switch (sr_info->ip_type) { |
106 | case SR_TYPE_V1: | |
984aa6db TG |
107 | /* Read the status bits */ |
108 | status = sr_read_reg(sr_info, ERRCONFIG_V1); | |
109 | ||
110 | /* Clear them by writing back */ | |
111 | sr_write_reg(sr_info, ERRCONFIG_V1, status); | |
4018bfeb FB |
112 | break; |
113 | case SR_TYPE_V2: | |
984aa6db | 114 | /* Read the status bits */ |
5a4f1844 | 115 | status = sr_read_reg(sr_info, IRQSTATUS); |
984aa6db TG |
116 | |
117 | /* Clear them by writing back */ | |
118 | sr_write_reg(sr_info, IRQSTATUS, status); | |
4018bfeb FB |
119 | break; |
120 | default: | |
121 | dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n", | |
122 | sr_info->ip_type); | |
123 | return IRQ_NONE; | |
984aa6db TG |
124 | } |
125 | ||
7a89afa8 | 126 | if (sr_class->notify) |
80821c9c | 127 | sr_class->notify(sr_info, status); |
984aa6db TG |
128 | |
129 | return IRQ_HANDLED; | |
130 | } | |
131 | ||
132 | static void sr_set_clk_length(struct omap_sr *sr) | |
133 | { | |
134 | struct clk *sys_ck; | |
135 | u32 sys_clk_speed; | |
136 | ||
b35cecf9 TG |
137 | if (cpu_is_omap34xx()) |
138 | sys_ck = clk_get(NULL, "sys_ck"); | |
139 | else | |
140 | sys_ck = clk_get(NULL, "sys_clkin_ck"); | |
141 | ||
984aa6db TG |
142 | if (IS_ERR(sys_ck)) { |
143 | dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n", | |
144 | __func__); | |
145 | return; | |
146 | } | |
4018bfeb | 147 | |
984aa6db TG |
148 | sys_clk_speed = clk_get_rate(sys_ck); |
149 | clk_put(sys_ck); | |
150 | ||
151 | switch (sys_clk_speed) { | |
152 | case 12000000: | |
153 | sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; | |
154 | break; | |
155 | case 13000000: | |
156 | sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; | |
157 | break; | |
158 | case 19200000: | |
159 | sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; | |
160 | break; | |
161 | case 26000000: | |
162 | sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; | |
163 | break; | |
164 | case 38400000: | |
165 | sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; | |
166 | break; | |
167 | default: | |
168 | dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n", | |
169 | __func__, sys_clk_speed); | |
170 | break; | |
171 | } | |
172 | } | |
173 | ||
174 | static void sr_set_regfields(struct omap_sr *sr) | |
175 | { | |
176 | /* | |
177 | * For time being these values are defined in smartreflex.h | |
178 | * and populated during init. May be they can be moved to board | |
179 | * file or pmic specific data structure. In that case these structure | |
180 | * fields will have to be populated using the pdata or pmic structure. | |
181 | */ | |
b35cecf9 | 182 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
984aa6db TG |
183 | sr->err_weight = OMAP3430_SR_ERRWEIGHT; |
184 | sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT; | |
185 | sr->accum_data = OMAP3430_SR_ACCUMDATA; | |
1fcd3069 | 186 | if (!(strcmp(sr->name, "smartreflex_mpu_iva"))) { |
984aa6db TG |
187 | sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT; |
188 | sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT; | |
189 | } else { | |
190 | sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT; | |
191 | sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT; | |
192 | } | |
193 | } | |
194 | } | |
195 | ||
196 | static void sr_start_vddautocomp(struct omap_sr *sr) | |
197 | { | |
198 | if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { | |
199 | dev_warn(&sr->pdev->dev, | |
200 | "%s: smartreflex class driver not registered\n", | |
201 | __func__); | |
202 | return; | |
203 | } | |
204 | ||
80821c9c | 205 | if (!sr_class->enable(sr)) |
984aa6db TG |
206 | sr->autocomp_active = true; |
207 | } | |
208 | ||
209 | static void sr_stop_vddautocomp(struct omap_sr *sr) | |
210 | { | |
211 | if (!sr_class || !(sr_class->disable)) { | |
212 | dev_warn(&sr->pdev->dev, | |
213 | "%s: smartreflex class driver not registered\n", | |
214 | __func__); | |
215 | return; | |
216 | } | |
217 | ||
218 | if (sr->autocomp_active) { | |
80821c9c | 219 | sr_class->disable(sr, 1); |
984aa6db TG |
220 | sr->autocomp_active = false; |
221 | } | |
222 | } | |
223 | ||
224 | /* | |
225 | * This function handles the intializations which have to be done | |
226 | * only when both sr device and class driver regiter has | |
227 | * completed. This will be attempted to be called from both sr class | |
228 | * driver register and sr device intializtion API's. Only one call | |
229 | * will ultimately succeed. | |
230 | * | |
fb914ebf | 231 | * Currently this function registers interrupt handler for a particular SR |
984aa6db TG |
232 | * if smartreflex class driver is already registered and has |
233 | * requested for interrupts and the SR interrupt line in present. | |
234 | */ | |
235 | static int sr_late_init(struct omap_sr *sr_info) | |
236 | { | |
984aa6db TG |
237 | struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data; |
238 | struct resource *mem; | |
239 | int ret = 0; | |
240 | ||
7a89afa8 | 241 | if (sr_class->notify && sr_class->notify_flags && sr_info->irq) { |
984aa6db | 242 | ret = request_irq(sr_info->irq, sr_interrupt, |
8b765d72 | 243 | 0, sr_info->name, sr_info); |
984aa6db TG |
244 | if (ret) |
245 | goto error; | |
1279ba59 | 246 | disable_irq(sr_info->irq); |
984aa6db TG |
247 | } |
248 | ||
249 | if (pdata && pdata->enable_on_init) | |
250 | sr_start_vddautocomp(sr_info); | |
251 | ||
252 | return ret; | |
253 | ||
254 | error: | |
442155ad NM |
255 | iounmap(sr_info->base); |
256 | mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0); | |
257 | release_mem_region(mem->start, resource_size(mem)); | |
258 | list_del(&sr_info->node); | |
259 | dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" | |
260 | "interrupt handler. Smartreflex will" | |
261 | "not function as desired\n", __func__); | |
442155ad | 262 | kfree(sr_info); |
4018bfeb | 263 | |
442155ad | 264 | return ret; |
984aa6db TG |
265 | } |
266 | ||
267 | static void sr_v1_disable(struct omap_sr *sr) | |
268 | { | |
269 | int timeout = 0; | |
cfec9c54 NM |
270 | int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST | |
271 | ERRCONFIG_MCUBOUNDINTST; | |
984aa6db TG |
272 | |
273 | /* Enable MCUDisableAcknowledge interrupt */ | |
274 | sr_modify_reg(sr, ERRCONFIG_V1, | |
275 | ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN); | |
276 | ||
277 | /* SRCONFIG - disable SR */ | |
278 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); | |
279 | ||
cfec9c54 NM |
280 | /* Disable all other SR interrupts and clear the status as needed */ |
281 | if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1) | |
282 | errconf_val |= ERRCONFIG_VPBOUNDINTST_V1; | |
984aa6db TG |
283 | sr_modify_reg(sr, ERRCONFIG_V1, |
284 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | | |
285 | ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1), | |
cfec9c54 | 286 | errconf_val); |
984aa6db TG |
287 | |
288 | /* | |
289 | * Wait for SR to be disabled. | |
290 | * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us. | |
291 | */ | |
50e4a7d0 JP |
292 | sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) & |
293 | ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT, | |
294 | timeout); | |
984aa6db TG |
295 | |
296 | if (timeout >= SR_DISABLE_TIMEOUT) | |
297 | dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", | |
298 | __func__); | |
299 | ||
300 | /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ | |
301 | sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN, | |
302 | ERRCONFIG_MCUDISACKINTST); | |
303 | } | |
304 | ||
305 | static void sr_v2_disable(struct omap_sr *sr) | |
306 | { | |
307 | int timeout = 0; | |
308 | ||
309 | /* Enable MCUDisableAcknowledge interrupt */ | |
310 | sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT); | |
311 | ||
312 | /* SRCONFIG - disable SR */ | |
313 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); | |
314 | ||
cfec9c54 NM |
315 | /* |
316 | * Disable all other SR interrupts and clear the status | |
317 | * write to status register ONLY on need basis - only if status | |
318 | * is set. | |
319 | */ | |
320 | if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2) | |
321 | sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, | |
984aa6db | 322 | ERRCONFIG_VPBOUNDINTST_V2); |
cfec9c54 NM |
323 | else |
324 | sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, | |
325 | 0x0); | |
984aa6db TG |
326 | sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT | |
327 | IRQENABLE_MCUVALIDINT | | |
328 | IRQENABLE_MCUBOUNDSINT)); | |
329 | sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT | | |
330 | IRQSTATUS_MCVALIDINT | | |
331 | IRQSTATUS_MCBOUNDSINT)); | |
332 | ||
333 | /* | |
334 | * Wait for SR to be disabled. | |
335 | * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us. | |
336 | */ | |
50e4a7d0 JP |
337 | sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) & |
338 | IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT, | |
339 | timeout); | |
984aa6db TG |
340 | |
341 | if (timeout >= SR_DISABLE_TIMEOUT) | |
342 | dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", | |
343 | __func__); | |
344 | ||
345 | /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ | |
346 | sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT); | |
347 | sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT); | |
348 | } | |
349 | ||
350 | static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs) | |
351 | { | |
352 | int i; | |
353 | ||
354 | if (!sr->nvalue_table) { | |
355 | dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n", | |
356 | __func__); | |
357 | return 0; | |
358 | } | |
359 | ||
360 | for (i = 0; i < sr->nvalue_count; i++) { | |
361 | if (sr->nvalue_table[i].efuse_offs == efuse_offs) | |
362 | return sr->nvalue_table[i].nvalue; | |
363 | } | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | /* Public Functions */ | |
369 | ||
370 | /** | |
371 | * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the | |
372 | * error generator module. | |
373 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
374 | * | |
375 | * This API is to be called from the smartreflex class driver to | |
376 | * configure the error generator module inside the smartreflex module. | |
377 | * SR settings if using the ERROR module inside Smartreflex. | |
378 | * SR CLASS 3 by default uses only the ERROR module where as | |
379 | * SR CLASS 2 can choose between ERROR module and MINMAXAVG | |
380 | * module. Returns 0 on success and error value in case of failure. | |
381 | */ | |
382 | int sr_configure_errgen(struct voltagedomain *voltdm) | |
383 | { | |
4018bfeb FB |
384 | u32 sr_config, sr_errconfig, errconfig_offs; |
385 | u32 vpboundint_en, vpboundint_st; | |
386 | u32 senp_en = 0, senn_en = 0; | |
984aa6db TG |
387 | u8 senp_shift, senn_shift; |
388 | struct omap_sr *sr = _sr_lookup(voltdm); | |
389 | ||
390 | if (IS_ERR(sr)) { | |
8b765d72 | 391 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
63371faf | 392 | return PTR_ERR(sr); |
984aa6db TG |
393 | } |
394 | ||
395 | if (!sr->clk_length) | |
396 | sr_set_clk_length(sr); | |
397 | ||
398 | senp_en = sr->senp_mod; | |
399 | senn_en = sr->senn_mod; | |
400 | ||
401 | sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | |
402 | SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN; | |
403 | ||
4018bfeb FB |
404 | switch (sr->ip_type) { |
405 | case SR_TYPE_V1: | |
984aa6db TG |
406 | sr_config |= SRCONFIG_DELAYCTRL; |
407 | senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; | |
408 | senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; | |
409 | errconfig_offs = ERRCONFIG_V1; | |
410 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1; | |
411 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1; | |
4018bfeb FB |
412 | break; |
413 | case SR_TYPE_V2: | |
984aa6db TG |
414 | senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; |
415 | senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; | |
416 | errconfig_offs = ERRCONFIG_V2; | |
417 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2; | |
418 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2; | |
4018bfeb FB |
419 | break; |
420 | default: | |
984aa6db TG |
421 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" |
422 | "module without specifying the ip\n", __func__); | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); | |
427 | sr_write_reg(sr, SRCONFIG, sr_config); | |
428 | sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) | | |
429 | (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) | | |
430 | (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT); | |
431 | sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK | | |
432 | SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), | |
433 | sr_errconfig); | |
434 | ||
435 | /* Enabling the interrupts if the ERROR module is used */ | |
74754cc5 NM |
436 | sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st), |
437 | vpboundint_en); | |
984aa6db TG |
438 | |
439 | return 0; | |
440 | } | |
441 | ||
ad54c3dd NM |
442 | /** |
443 | * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component | |
444 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
445 | * | |
446 | * This API is to be called from the smartreflex class driver to | |
447 | * disable the error generator module inside the smartreflex module. | |
448 | * | |
449 | * Returns 0 on success and error value in case of failure. | |
450 | */ | |
451 | int sr_disable_errgen(struct voltagedomain *voltdm) | |
452 | { | |
4018bfeb FB |
453 | u32 errconfig_offs; |
454 | u32 vpboundint_en, vpboundint_st; | |
ad54c3dd NM |
455 | struct omap_sr *sr = _sr_lookup(voltdm); |
456 | ||
457 | if (IS_ERR(sr)) { | |
8b765d72 | 458 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
63371faf | 459 | return PTR_ERR(sr); |
ad54c3dd NM |
460 | } |
461 | ||
4018bfeb FB |
462 | switch (sr->ip_type) { |
463 | case SR_TYPE_V1: | |
ad54c3dd NM |
464 | errconfig_offs = ERRCONFIG_V1; |
465 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1; | |
466 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1; | |
4018bfeb FB |
467 | break; |
468 | case SR_TYPE_V2: | |
ad54c3dd NM |
469 | errconfig_offs = ERRCONFIG_V2; |
470 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2; | |
471 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2; | |
4018bfeb FB |
472 | break; |
473 | default: | |
ad54c3dd NM |
474 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" |
475 | "module without specifying the ip\n", __func__); | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
479 | /* Disable the interrupts of ERROR module */ | |
480 | sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0); | |
481 | ||
482 | /* Disable the Sensor and errorgen */ | |
483 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
984aa6db TG |
488 | /** |
489 | * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the | |
490 | * minmaxavg module. | |
491 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
492 | * | |
493 | * This API is to be called from the smartreflex class driver to | |
494 | * configure the minmaxavg module inside the smartreflex module. | |
495 | * SR settings if using the ERROR module inside Smartreflex. | |
496 | * SR CLASS 3 by default uses only the ERROR module where as | |
497 | * SR CLASS 2 can choose between ERROR module and MINMAXAVG | |
498 | * module. Returns 0 on success and error value in case of failure. | |
499 | */ | |
500 | int sr_configure_minmax(struct voltagedomain *voltdm) | |
501 | { | |
502 | u32 sr_config, sr_avgwt; | |
503 | u32 senp_en = 0, senn_en = 0; | |
504 | u8 senp_shift, senn_shift; | |
505 | struct omap_sr *sr = _sr_lookup(voltdm); | |
506 | ||
507 | if (IS_ERR(sr)) { | |
8b765d72 | 508 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
63371faf | 509 | return PTR_ERR(sr); |
984aa6db TG |
510 | } |
511 | ||
512 | if (!sr->clk_length) | |
513 | sr_set_clk_length(sr); | |
514 | ||
515 | senp_en = sr->senp_mod; | |
516 | senn_en = sr->senn_mod; | |
517 | ||
518 | sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | |
519 | SRCONFIG_SENENABLE | | |
520 | (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT); | |
521 | ||
4018bfeb FB |
522 | switch (sr->ip_type) { |
523 | case SR_TYPE_V1: | |
984aa6db TG |
524 | sr_config |= SRCONFIG_DELAYCTRL; |
525 | senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; | |
526 | senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; | |
4018bfeb FB |
527 | break; |
528 | case SR_TYPE_V2: | |
984aa6db TG |
529 | senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; |
530 | senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; | |
4018bfeb FB |
531 | break; |
532 | default: | |
984aa6db TG |
533 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" |
534 | "module without specifying the ip\n", __func__); | |
535 | return -EINVAL; | |
536 | } | |
537 | ||
538 | sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); | |
539 | sr_write_reg(sr, SRCONFIG, sr_config); | |
540 | sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) | | |
541 | (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT); | |
542 | sr_write_reg(sr, AVGWEIGHT, sr_avgwt); | |
543 | ||
544 | /* | |
545 | * Enabling the interrupts if MINMAXAVG module is used. | |
546 | * TODO: check if all the interrupts are mandatory | |
547 | */ | |
4018bfeb FB |
548 | switch (sr->ip_type) { |
549 | case SR_TYPE_V1: | |
984aa6db TG |
550 | sr_modify_reg(sr, ERRCONFIG_V1, |
551 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | | |
552 | ERRCONFIG_MCUBOUNDINTEN), | |
553 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST | | |
554 | ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST | | |
555 | ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST)); | |
4018bfeb FB |
556 | break; |
557 | case SR_TYPE_V2: | |
984aa6db TG |
558 | sr_write_reg(sr, IRQSTATUS, |
559 | IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT | | |
560 | IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT); | |
561 | sr_write_reg(sr, IRQENABLE_SET, | |
562 | IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT | | |
563 | IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT); | |
4018bfeb FB |
564 | break; |
565 | default: | |
566 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" | |
567 | "module without specifying the ip\n", __func__); | |
568 | return -EINVAL; | |
984aa6db TG |
569 | } |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | /** | |
575 | * sr_enable() - Enables the smartreflex module. | |
576 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
577 | * @volt: The voltage at which the Voltage domain associated with | |
578 | * the smartreflex module is operating at. | |
579 | * This is required only to program the correct Ntarget value. | |
580 | * | |
581 | * This API is to be called from the smartreflex class driver to | |
582 | * enable a smartreflex module. Returns 0 on success. Returns error | |
583 | * value if the voltage passed is wrong or if ntarget value is wrong. | |
584 | */ | |
585 | int sr_enable(struct voltagedomain *voltdm, unsigned long volt) | |
586 | { | |
984aa6db TG |
587 | struct omap_volt_data *volt_data; |
588 | struct omap_sr *sr = _sr_lookup(voltdm); | |
4018bfeb | 589 | u32 nvalue_reciprocal; |
984aa6db TG |
590 | int ret; |
591 | ||
592 | if (IS_ERR(sr)) { | |
8b765d72 | 593 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
63371faf | 594 | return PTR_ERR(sr); |
984aa6db TG |
595 | } |
596 | ||
597 | volt_data = omap_voltage_get_voltdata(sr->voltdm, volt); | |
598 | ||
599 | if (IS_ERR(volt_data)) { | |
600 | dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table" | |
601 | "for nominal voltage %ld\n", __func__, volt); | |
63371faf | 602 | return PTR_ERR(volt_data); |
984aa6db TG |
603 | } |
604 | ||
605 | nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs); | |
606 | ||
607 | if (!nvalue_reciprocal) { | |
608 | dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n", | |
609 | __func__, volt); | |
610 | return -ENODATA; | |
611 | } | |
612 | ||
613 | /* errminlimit is opp dependent and hence linked to voltage */ | |
614 | sr->err_minlimit = volt_data->sr_errminlimit; | |
615 | ||
616 | pm_runtime_get_sync(&sr->pdev->dev); | |
617 | ||
618 | /* Check if SR is already enabled. If yes do nothing */ | |
619 | if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) | |
620 | return 0; | |
621 | ||
622 | /* Configure SR */ | |
80821c9c | 623 | ret = sr_class->configure(sr); |
984aa6db TG |
624 | if (ret) |
625 | return ret; | |
626 | ||
627 | sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); | |
628 | ||
629 | /* SRCONFIG - enable SR */ | |
630 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | /** | |
635 | * sr_disable() - Disables the smartreflex module. | |
636 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
637 | * | |
638 | * This API is to be called from the smartreflex class driver to | |
639 | * disable a smartreflex module. | |
640 | */ | |
641 | void sr_disable(struct voltagedomain *voltdm) | |
642 | { | |
643 | struct omap_sr *sr = _sr_lookup(voltdm); | |
644 | ||
645 | if (IS_ERR(sr)) { | |
8b765d72 | 646 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
984aa6db TG |
647 | return; |
648 | } | |
649 | ||
650 | /* Check if SR clocks are already disabled. If yes do nothing */ | |
651 | if (pm_runtime_suspended(&sr->pdev->dev)) | |
652 | return; | |
653 | ||
654 | /* | |
655 | * Disable SR if only it is indeed enabled. Else just | |
656 | * disable the clocks. | |
657 | */ | |
658 | if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) { | |
4018bfeb FB |
659 | switch (sr->ip_type) { |
660 | case SR_TYPE_V1: | |
984aa6db | 661 | sr_v1_disable(sr); |
4018bfeb FB |
662 | break; |
663 | case SR_TYPE_V2: | |
984aa6db | 664 | sr_v2_disable(sr); |
4018bfeb FB |
665 | break; |
666 | default: | |
667 | dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n", | |
668 | sr->ip_type); | |
669 | } | |
984aa6db TG |
670 | } |
671 | ||
98333b3d | 672 | pm_runtime_put_sync_suspend(&sr->pdev->dev); |
984aa6db TG |
673 | } |
674 | ||
675 | /** | |
676 | * sr_register_class() - API to register a smartreflex class parameters. | |
677 | * @class_data: The structure containing various sr class specific data. | |
678 | * | |
679 | * This API is to be called by the smartreflex class driver to register itself | |
680 | * with the smartreflex driver during init. Returns 0 on success else the | |
681 | * error value. | |
682 | */ | |
683 | int sr_register_class(struct omap_sr_class_data *class_data) | |
684 | { | |
685 | struct omap_sr *sr_info; | |
686 | ||
687 | if (!class_data) { | |
688 | pr_warning("%s:, Smartreflex class data passed is NULL\n", | |
689 | __func__); | |
690 | return -EINVAL; | |
691 | } | |
692 | ||
693 | if (sr_class) { | |
694 | pr_warning("%s: Smartreflex class driver already registered\n", | |
695 | __func__); | |
696 | return -EBUSY; | |
697 | } | |
698 | ||
699 | sr_class = class_data; | |
700 | ||
701 | /* | |
702 | * Call into late init to do intializations that require | |
703 | * both sr driver and sr class driver to be initiallized. | |
704 | */ | |
705 | list_for_each_entry(sr_info, &sr_list, node) | |
706 | sr_late_init(sr_info); | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | /** | |
712 | * omap_sr_enable() - API to enable SR clocks and to call into the | |
713 | * registered smartreflex class enable API. | |
714 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
715 | * | |
716 | * This API is to be called from the kernel in order to enable | |
717 | * a particular smartreflex module. This API will do the initial | |
718 | * configurations to turn on the smartreflex module and in turn call | |
719 | * into the registered smartreflex class enable API. | |
720 | */ | |
721 | void omap_sr_enable(struct voltagedomain *voltdm) | |
722 | { | |
723 | struct omap_sr *sr = _sr_lookup(voltdm); | |
724 | ||
725 | if (IS_ERR(sr)) { | |
8b765d72 | 726 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
984aa6db TG |
727 | return; |
728 | } | |
729 | ||
730 | if (!sr->autocomp_active) | |
731 | return; | |
732 | ||
733 | if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { | |
734 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | |
735 | "registered\n", __func__); | |
736 | return; | |
737 | } | |
738 | ||
80821c9c | 739 | sr_class->enable(sr); |
984aa6db TG |
740 | } |
741 | ||
742 | /** | |
743 | * omap_sr_disable() - API to disable SR without resetting the voltage | |
744 | * processor voltage | |
745 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
746 | * | |
747 | * This API is to be called from the kernel in order to disable | |
748 | * a particular smartreflex module. This API will in turn call | |
749 | * into the registered smartreflex class disable API. This API will tell | |
750 | * the smartreflex class disable not to reset the VP voltage after | |
751 | * disabling smartreflex. | |
752 | */ | |
753 | void omap_sr_disable(struct voltagedomain *voltdm) | |
754 | { | |
755 | struct omap_sr *sr = _sr_lookup(voltdm); | |
756 | ||
757 | if (IS_ERR(sr)) { | |
8b765d72 | 758 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
984aa6db TG |
759 | return; |
760 | } | |
761 | ||
762 | if (!sr->autocomp_active) | |
763 | return; | |
764 | ||
765 | if (!sr_class || !(sr_class->disable)) { | |
766 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | |
767 | "registered\n", __func__); | |
768 | return; | |
769 | } | |
770 | ||
80821c9c | 771 | sr_class->disable(sr, 0); |
984aa6db TG |
772 | } |
773 | ||
774 | /** | |
775 | * omap_sr_disable_reset_volt() - API to disable SR and reset the | |
776 | * voltage processor voltage | |
777 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | |
778 | * | |
779 | * This API is to be called from the kernel in order to disable | |
780 | * a particular smartreflex module. This API will in turn call | |
781 | * into the registered smartreflex class disable API. This API will tell | |
782 | * the smartreflex class disable to reset the VP voltage after | |
783 | * disabling smartreflex. | |
784 | */ | |
785 | void omap_sr_disable_reset_volt(struct voltagedomain *voltdm) | |
786 | { | |
787 | struct omap_sr *sr = _sr_lookup(voltdm); | |
788 | ||
789 | if (IS_ERR(sr)) { | |
8b765d72 | 790 | pr_warning("%s: omap_sr struct for voltdm not found\n", __func__); |
984aa6db TG |
791 | return; |
792 | } | |
793 | ||
794 | if (!sr->autocomp_active) | |
795 | return; | |
796 | ||
797 | if (!sr_class || !(sr_class->disable)) { | |
798 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | |
799 | "registered\n", __func__); | |
800 | return; | |
801 | } | |
802 | ||
80821c9c | 803 | sr_class->disable(sr, 1); |
984aa6db TG |
804 | } |
805 | ||
806 | /** | |
807 | * omap_sr_register_pmic() - API to register pmic specific info. | |
808 | * @pmic_data: The structure containing pmic specific data. | |
809 | * | |
810 | * This API is to be called from the PMIC specific code to register with | |
811 | * smartreflex driver pmic specific info. Currently the only info required | |
812 | * is the smartreflex init on the PMIC side. | |
813 | */ | |
814 | void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data) | |
815 | { | |
816 | if (!pmic_data) { | |
817 | pr_warning("%s: Trying to register NULL PMIC data structure" | |
818 | "with smartreflex\n", __func__); | |
819 | return; | |
820 | } | |
821 | ||
822 | sr_pmic_data = pmic_data; | |
823 | } | |
824 | ||
4018bfeb | 825 | /* PM Debug FS entries to enable and disable smartreflex. */ |
984aa6db TG |
826 | static int omap_sr_autocomp_show(void *data, u64 *val) |
827 | { | |
4018bfeb | 828 | struct omap_sr *sr_info = data; |
984aa6db TG |
829 | |
830 | if (!sr_info) { | |
8353584e | 831 | pr_warning("%s: omap_sr struct not found\n", __func__); |
984aa6db TG |
832 | return -EINVAL; |
833 | } | |
834 | ||
835 | *val = sr_info->autocomp_active; | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | static int omap_sr_autocomp_store(void *data, u64 val) | |
841 | { | |
4018bfeb | 842 | struct omap_sr *sr_info = data; |
984aa6db TG |
843 | |
844 | if (!sr_info) { | |
8353584e | 845 | pr_warning("%s: omap_sr struct not found\n", __func__); |
984aa6db TG |
846 | return -EINVAL; |
847 | } | |
848 | ||
849 | /* Sanity check */ | |
d6173692 | 850 | if (val > 1) { |
984aa6db TG |
851 | pr_warning("%s: Invalid argument %lld\n", __func__, val); |
852 | return -EINVAL; | |
853 | } | |
854 | ||
ac77a6f7 NM |
855 | /* control enable/disable only if there is a delta in value */ |
856 | if (sr_info->autocomp_active != val) { | |
857 | if (!val) | |
858 | sr_stop_vddautocomp(sr_info); | |
859 | else | |
860 | sr_start_vddautocomp(sr_info); | |
861 | } | |
984aa6db TG |
862 | |
863 | return 0; | |
864 | } | |
865 | ||
866 | DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show, | |
4018bfeb | 867 | omap_sr_autocomp_store, "%llu\n"); |
984aa6db TG |
868 | |
869 | static int __init omap_sr_probe(struct platform_device *pdev) | |
870 | { | |
4018bfeb | 871 | struct omap_sr *sr_info; |
984aa6db TG |
872 | struct omap_sr_data *pdata = pdev->dev.platform_data; |
873 | struct resource *mem, *irq; | |
633ef8b7 | 874 | struct dentry *nvalue_dir; |
077fceca TG |
875 | struct omap_volt_data *volt_data; |
876 | int i, ret = 0; | |
984aa6db | 877 | |
4018bfeb | 878 | sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL); |
984aa6db TG |
879 | if (!sr_info) { |
880 | dev_err(&pdev->dev, "%s: unable to allocate sr_info\n", | |
881 | __func__); | |
882 | return -ENOMEM; | |
883 | } | |
884 | ||
1079a8b2 FB |
885 | platform_set_drvdata(pdev, sr_info); |
886 | ||
984aa6db TG |
887 | if (!pdata) { |
888 | dev_err(&pdev->dev, "%s: platform data missing\n", __func__); | |
720bc782 SW |
889 | ret = -EINVAL; |
890 | goto err_free_devinfo; | |
984aa6db TG |
891 | } |
892 | ||
893 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
894 | if (!mem) { | |
895 | dev_err(&pdev->dev, "%s: no mem resource\n", __func__); | |
896 | ret = -ENODEV; | |
897 | goto err_free_devinfo; | |
898 | } | |
899 | ||
da9e7392 AK |
900 | mem = request_mem_region(mem->start, resource_size(mem), |
901 | dev_name(&pdev->dev)); | |
902 | if (!mem) { | |
903 | dev_err(&pdev->dev, "%s: no mem region\n", __func__); | |
904 | ret = -EBUSY; | |
905 | goto err_free_devinfo; | |
906 | } | |
907 | ||
984aa6db TG |
908 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
909 | ||
910 | pm_runtime_enable(&pdev->dev); | |
e13d8f38 | 911 | pm_runtime_irq_safe(&pdev->dev); |
984aa6db | 912 | |
8b765d72 JP |
913 | sr_info->name = kasprintf(GFP_KERNEL, "%s", pdata->name); |
914 | if (!sr_info->name) { | |
915 | dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n", | |
916 | __func__); | |
917 | ret = -ENOMEM; | |
918 | goto err_release_region; | |
919 | } | |
920 | ||
984aa6db TG |
921 | sr_info->pdev = pdev; |
922 | sr_info->srid = pdev->id; | |
923 | sr_info->voltdm = pdata->voltdm; | |
924 | sr_info->nvalue_table = pdata->nvalue_table; | |
925 | sr_info->nvalue_count = pdata->nvalue_count; | |
926 | sr_info->senn_mod = pdata->senn_mod; | |
927 | sr_info->senp_mod = pdata->senp_mod; | |
928 | sr_info->autocomp_active = false; | |
929 | sr_info->ip_type = pdata->ip_type; | |
930 | sr_info->base = ioremap(mem->start, resource_size(mem)); | |
931 | if (!sr_info->base) { | |
932 | dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); | |
933 | ret = -ENOMEM; | |
934 | goto err_release_region; | |
935 | } | |
936 | ||
937 | if (irq) | |
938 | sr_info->irq = irq->start; | |
939 | ||
940 | sr_set_clk_length(sr_info); | |
941 | sr_set_regfields(sr_info); | |
942 | ||
943 | list_add(&sr_info->node, &sr_list); | |
944 | ||
945 | /* | |
946 | * Call into late init to do intializations that require | |
947 | * both sr driver and sr class driver to be initiallized. | |
948 | */ | |
949 | if (sr_class) { | |
950 | ret = sr_late_init(sr_info); | |
951 | if (ret) { | |
952 | pr_warning("%s: Error in SR late init\n", __func__); | |
14ea9601 | 953 | goto err_iounmap; |
984aa6db TG |
954 | } |
955 | } | |
956 | ||
957 | dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__); | |
633ef8b7 KH |
958 | if (!sr_dbg_dir) { |
959 | sr_dbg_dir = debugfs_create_dir("smartreflex", NULL); | |
54b28cdf | 960 | if (IS_ERR_OR_NULL(sr_dbg_dir)) { |
633ef8b7 KH |
961 | ret = PTR_ERR(sr_dbg_dir); |
962 | pr_err("%s:sr debugfs dir creation failed(%d)\n", | |
963 | __func__, ret); | |
964 | goto err_iounmap; | |
965 | } | |
966 | } | |
984aa6db | 967 | |
8b765d72 | 968 | sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir); |
54b28cdf | 969 | if (IS_ERR_OR_NULL(sr_info->dbg_dir)) { |
984aa6db TG |
970 | dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n", |
971 | __func__); | |
b1ace380 | 972 | ret = PTR_ERR(sr_info->dbg_dir); |
8b765d72 | 973 | goto err_free_name; |
984aa6db TG |
974 | } |
975 | ||
b1ace380 AS |
976 | (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, |
977 | sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops); | |
978 | (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir, | |
077fceca | 979 | &sr_info->err_weight); |
b1ace380 | 980 | (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir, |
077fceca | 981 | &sr_info->err_maxlimit); |
b1ace380 | 982 | (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir, |
077fceca TG |
983 | &sr_info->err_minlimit); |
984 | ||
b1ace380 | 985 | nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir); |
54b28cdf | 986 | if (IS_ERR_OR_NULL(nvalue_dir)) { |
077fceca TG |
987 | dev_err(&pdev->dev, "%s: Unable to create debugfs directory" |
988 | "for n-values\n", __func__); | |
b3329a33 | 989 | ret = PTR_ERR(nvalue_dir); |
283a1c1f | 990 | goto err_debugfs; |
077fceca TG |
991 | } |
992 | ||
993 | omap_voltage_get_volttable(sr_info->voltdm, &volt_data); | |
994 | if (!volt_data) { | |
8b765d72 JP |
995 | dev_warn(&pdev->dev, "%s: %s: No Voltage table for the" |
996 | " corresponding vdd. Cannot create debugfs" | |
077fceca | 997 | "entries for n-values\n", |
8b765d72 | 998 | __func__, sr_info->name); |
b3329a33 | 999 | ret = -ENODATA; |
283a1c1f | 1000 | goto err_debugfs; |
077fceca TG |
1001 | } |
1002 | ||
1003 | for (i = 0; i < sr_info->nvalue_count; i++) { | |
865212ab | 1004 | char name[NVALUE_NAME_LEN + 1]; |
077fceca | 1005 | |
865212ab AK |
1006 | snprintf(name, sizeof(name), "volt_%d", |
1007 | volt_data[i].volt_nominal); | |
1232a185 | 1008 | (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir, |
077fceca TG |
1009 | &(sr_info->nvalue_table[i].nvalue)); |
1010 | } | |
984aa6db TG |
1011 | |
1012 | return ret; | |
1013 | ||
283a1c1f AK |
1014 | err_debugfs: |
1015 | debugfs_remove_recursive(sr_info->dbg_dir); | |
8b765d72 JP |
1016 | err_free_name: |
1017 | kfree(sr_info->name); | |
0c49cc16 | 1018 | err_iounmap: |
833d78fc | 1019 | list_del(&sr_info->node); |
0c49cc16 | 1020 | iounmap(sr_info->base); |
984aa6db TG |
1021 | err_release_region: |
1022 | release_mem_region(mem->start, resource_size(mem)); | |
1023 | err_free_devinfo: | |
1024 | kfree(sr_info); | |
1025 | ||
1026 | return ret; | |
1027 | } | |
1028 | ||
1029 | static int __devexit omap_sr_remove(struct platform_device *pdev) | |
1030 | { | |
1031 | struct omap_sr_data *pdata = pdev->dev.platform_data; | |
1032 | struct omap_sr *sr_info; | |
1033 | struct resource *mem; | |
1034 | ||
1035 | if (!pdata) { | |
1036 | dev_err(&pdev->dev, "%s: platform data missing\n", __func__); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | sr_info = _sr_lookup(pdata->voltdm); | |
28693ec0 | 1041 | if (IS_ERR(sr_info)) { |
984aa6db TG |
1042 | dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", |
1043 | __func__); | |
63371faf | 1044 | return PTR_ERR(sr_info); |
984aa6db TG |
1045 | } |
1046 | ||
1047 | if (sr_info->autocomp_active) | |
1048 | sr_stop_vddautocomp(sr_info); | |
b1ace380 AS |
1049 | if (sr_info->dbg_dir) |
1050 | debugfs_remove_recursive(sr_info->dbg_dir); | |
984aa6db TG |
1051 | |
1052 | list_del(&sr_info->node); | |
1053 | iounmap(sr_info->base); | |
8b765d72 | 1054 | kfree(sr_info->name); |
984aa6db TG |
1055 | kfree(sr_info); |
1056 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1057 | release_mem_region(mem->start, resource_size(mem)); | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1f55bc18 NM |
1062 | static void __devexit omap_sr_shutdown(struct platform_device *pdev) |
1063 | { | |
1064 | struct omap_sr_data *pdata = pdev->dev.platform_data; | |
1065 | struct omap_sr *sr_info; | |
1066 | ||
1067 | if (!pdata) { | |
1068 | dev_err(&pdev->dev, "%s: platform data missing\n", __func__); | |
1069 | return; | |
1070 | } | |
1071 | ||
1072 | sr_info = _sr_lookup(pdata->voltdm); | |
1073 | if (IS_ERR(sr_info)) { | |
1074 | dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", | |
1075 | __func__); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | if (sr_info->autocomp_active) | |
1080 | sr_stop_vddautocomp(sr_info); | |
1081 | ||
1082 | return; | |
1083 | } | |
1084 | ||
984aa6db | 1085 | static struct platform_driver smartreflex_driver = { |
149f1d5c | 1086 | .remove = __devexit_p(omap_sr_remove), |
1f55bc18 | 1087 | .shutdown = __devexit_p(omap_sr_shutdown), |
984aa6db TG |
1088 | .driver = { |
1089 | .name = "smartreflex", | |
1090 | }, | |
1091 | }; | |
1092 | ||
1093 | static int __init sr_init(void) | |
1094 | { | |
1095 | int ret = 0; | |
1096 | ||
1097 | /* | |
1098 | * sr_init is a late init. If by then a pmic specific API is not | |
1099 | * registered either there is no need for anything to be done on | |
1100 | * the PMIC side or somebody has forgotten to register a PMIC | |
1101 | * handler. Warn for the second condition. | |
1102 | */ | |
1103 | if (sr_pmic_data && sr_pmic_data->sr_pmic_init) | |
1104 | sr_pmic_data->sr_pmic_init(); | |
1105 | else | |
1106 | pr_warning("%s: No PMIC hook to init smartreflex\n", __func__); | |
1107 | ||
1108 | ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe); | |
1109 | if (ret) { | |
1110 | pr_err("%s: platform driver register failed for SR\n", | |
1111 | __func__); | |
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1a21a680 | 1117 | late_initcall(sr_init); |
984aa6db TG |
1118 | |
1119 | static void __exit sr_exit(void) | |
1120 | { | |
1121 | platform_driver_unregister(&smartreflex_driver); | |
1122 | } | |
984aa6db TG |
1123 | module_exit(sr_exit); |
1124 | ||
1125 | MODULE_DESCRIPTION("OMAP Smartreflex Driver"); | |
1126 | MODULE_LICENSE("GPL"); | |
1127 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1128 | MODULE_AUTHOR("Texas Instruments Inc"); |