Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * arch/arm/mach-omap2/serial.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 serial support. | |
5 | * | |
6e81176d | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
1dbae815 TL |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | |
4af4016c KH |
9 | * Major rework for PM support by Kevin Hilman |
10 | * | |
1dbae815 TL |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com | |
15 | * | |
1dbae815 TL |
16 | * This file is subject to the terms and conditions of the GNU General Public |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/serial_8250.h> | |
23 | #include <linux/serial_reg.h> | |
f8ce2547 | 24 | #include <linux/clk.h> |
fced80c7 | 25 | #include <linux/io.h> |
1dbae815 | 26 | |
ce491cf8 TL |
27 | #include <plat/common.h> |
28 | #include <plat/board.h> | |
29 | #include <plat/clock.h> | |
30 | #include <plat/control.h> | |
4af4016c KH |
31 | |
32 | #include "prm.h" | |
33 | #include "pm.h" | |
34 | #include "prm-regbits-34xx.h" | |
35 | ||
ce13d471 | 36 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
4af4016c KH |
37 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
38 | ||
ba87a9be | 39 | #define DEFAULT_TIMEOUT (5 * HZ) |
4af4016c KH |
40 | |
41 | struct omap_uart_state { | |
42 | int num; | |
43 | int can_sleep; | |
44 | struct timer_list timer; | |
45 | u32 timeout; | |
46 | ||
47 | void __iomem *wk_st; | |
48 | void __iomem *wk_en; | |
49 | u32 wk_mask; | |
50 | u32 padconf; | |
51 | ||
52 | struct clk *ick; | |
53 | struct clk *fck; | |
54 | int clocked; | |
55 | ||
56 | struct plat_serial8250_port *p; | |
57 | struct list_head node; | |
fd455ea8 | 58 | struct platform_device pdev; |
1dbae815 | 59 | |
4af4016c KH |
60 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
61 | int context_valid; | |
62 | ||
63 | /* Registers to be saved/restored for OFF-mode */ | |
64 | u16 dll; | |
65 | u16 dlh; | |
66 | u16 ier; | |
67 | u16 sysc; | |
68 | u16 scr; | |
69 | u16 wer; | |
70 | #endif | |
71 | }; | |
72 | ||
4af4016c | 73 | static LIST_HEAD(uart_list); |
1dbae815 | 74 | |
fd455ea8 | 75 | static struct plat_serial8250_port serial_platform_data0[] = { |
1dbae815 | 76 | { |
e8a91c95 | 77 | .mapbase = OMAP_UART1_BASE, |
1dbae815 TL |
78 | .irq = 72, |
79 | .flags = UPF_BOOT_AUTOCONF, | |
80 | .iotype = UPIO_MEM, | |
81 | .regshift = 2, | |
6e81176d | 82 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 | 83 | }, { |
fd455ea8 KH |
84 | .flags = 0 |
85 | } | |
86 | }; | |
87 | ||
88 | static struct plat_serial8250_port serial_platform_data1[] = { | |
89 | { | |
e8a91c95 | 90 | .mapbase = OMAP_UART2_BASE, |
1dbae815 TL |
91 | .irq = 73, |
92 | .flags = UPF_BOOT_AUTOCONF, | |
93 | .iotype = UPIO_MEM, | |
94 | .regshift = 2, | |
6e81176d | 95 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 | 96 | }, { |
fd455ea8 KH |
97 | .flags = 0 |
98 | } | |
99 | }; | |
100 | ||
101 | static struct plat_serial8250_port serial_platform_data2[] = { | |
102 | { | |
e8a91c95 | 103 | .mapbase = OMAP_UART3_BASE, |
1dbae815 TL |
104 | .irq = 74, |
105 | .flags = UPF_BOOT_AUTOCONF, | |
106 | .iotype = UPIO_MEM, | |
107 | .regshift = 2, | |
6e81176d | 108 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 TL |
109 | }, { |
110 | .flags = 0 | |
111 | } | |
112 | }; | |
113 | ||
0e3eaadf SS |
114 | #ifdef CONFIG_ARCH_OMAP4 |
115 | static struct plat_serial8250_port serial_platform_data3[] = { | |
116 | { | |
0e3eaadf SS |
117 | .mapbase = OMAP_UART4_BASE, |
118 | .irq = 70, | |
119 | .flags = UPF_BOOT_AUTOCONF, | |
120 | .iotype = UPIO_MEM, | |
121 | .regshift = 2, | |
122 | .uartclk = OMAP24XX_BASE_BAUD * 16, | |
123 | }, { | |
124 | .flags = 0 | |
125 | } | |
126 | }; | |
127 | #endif | |
1dbae815 TL |
128 | static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, |
129 | int offset) | |
130 | { | |
131 | offset <<= up->regshift; | |
132 | return (unsigned int)__raw_readb(up->membase + offset); | |
133 | } | |
134 | ||
135 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, | |
136 | int value) | |
137 | { | |
138 | offset <<= p->regshift; | |
e8a91c95 | 139 | __raw_writeb(value, p->membase + offset); |
1dbae815 TL |
140 | } |
141 | ||
142 | /* | |
143 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
144 | * properly. Note that the TX watermark initialization may not be needed | |
145 | * once the 8250.c watermark handling code is merged. | |
146 | */ | |
4af4016c | 147 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
1dbae815 | 148 | { |
4af4016c KH |
149 | struct plat_serial8250_port *p = uart->p; |
150 | ||
1dbae815 TL |
151 | serial_write_reg(p, UART_OMAP_MDR1, 0x07); |
152 | serial_write_reg(p, UART_OMAP_SCR, 0x08); | |
153 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); | |
671c7235 | 154 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); |
1dbae815 TL |
155 | } |
156 | ||
4af4016c KH |
157 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
158 | ||
4af4016c | 159 | static void omap_uart_save_context(struct omap_uart_state *uart) |
6e81176d | 160 | { |
4af4016c KH |
161 | u16 lcr = 0; |
162 | struct plat_serial8250_port *p = uart->p; | |
163 | ||
164 | if (!enable_off_mode) | |
165 | return; | |
166 | ||
167 | lcr = serial_read_reg(p, UART_LCR); | |
168 | serial_write_reg(p, UART_LCR, 0xBF); | |
169 | uart->dll = serial_read_reg(p, UART_DLL); | |
170 | uart->dlh = serial_read_reg(p, UART_DLM); | |
171 | serial_write_reg(p, UART_LCR, lcr); | |
172 | uart->ier = serial_read_reg(p, UART_IER); | |
173 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); | |
174 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); | |
175 | uart->wer = serial_read_reg(p, UART_OMAP_WER); | |
176 | ||
177 | uart->context_valid = 1; | |
178 | } | |
179 | ||
180 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
181 | { | |
182 | u16 efr = 0; | |
183 | struct plat_serial8250_port *p = uart->p; | |
184 | ||
185 | if (!enable_off_mode) | |
186 | return; | |
187 | ||
188 | if (!uart->context_valid) | |
189 | return; | |
190 | ||
191 | uart->context_valid = 0; | |
192 | ||
193 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); | |
194 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
195 | efr = serial_read_reg(p, UART_EFR); | |
196 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); | |
197 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
198 | serial_write_reg(p, UART_IER, 0x0); | |
199 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
200 | serial_write_reg(p, UART_DLL, uart->dll); | |
201 | serial_write_reg(p, UART_DLM, uart->dlh); | |
202 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
203 | serial_write_reg(p, UART_IER, uart->ier); | |
204 | serial_write_reg(p, UART_FCR, 0xA1); | |
205 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
206 | serial_write_reg(p, UART_EFR, efr); | |
207 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); | |
208 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); | |
209 | serial_write_reg(p, UART_OMAP_WER, uart->wer); | |
210 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); | |
211 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ | |
212 | } | |
213 | #else | |
214 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
215 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
216 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ | |
217 | ||
218 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
219 | { | |
220 | if (uart->clocked) | |
221 | return; | |
222 | ||
223 | clk_enable(uart->ick); | |
224 | clk_enable(uart->fck); | |
225 | uart->clocked = 1; | |
226 | omap_uart_restore_context(uart); | |
227 | } | |
228 | ||
229 | #ifdef CONFIG_PM | |
230 | ||
231 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
232 | { | |
233 | if (!uart->clocked) | |
234 | return; | |
235 | ||
236 | omap_uart_save_context(uart); | |
237 | uart->clocked = 0; | |
238 | clk_disable(uart->ick); | |
239 | clk_disable(uart->fck); | |
240 | } | |
241 | ||
fd455ea8 KH |
242 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
243 | { | |
244 | /* Set wake-enable bit */ | |
245 | if (uart->wk_en && uart->wk_mask) { | |
246 | u32 v = __raw_readl(uart->wk_en); | |
247 | v |= uart->wk_mask; | |
248 | __raw_writel(v, uart->wk_en); | |
249 | } | |
250 | ||
251 | /* Ensure IOPAD wake-enables are set */ | |
252 | if (cpu_is_omap34xx() && uart->padconf) { | |
253 | u16 v = omap_ctrl_readw(uart->padconf); | |
254 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
255 | omap_ctrl_writew(v, uart->padconf); | |
256 | } | |
257 | } | |
258 | ||
259 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | |
260 | { | |
261 | /* Clear wake-enable bit */ | |
262 | if (uart->wk_en && uart->wk_mask) { | |
263 | u32 v = __raw_readl(uart->wk_en); | |
264 | v &= ~uart->wk_mask; | |
265 | __raw_writel(v, uart->wk_en); | |
266 | } | |
267 | ||
268 | /* Ensure IOPAD wake-enables are cleared */ | |
269 | if (cpu_is_omap34xx() && uart->padconf) { | |
270 | u16 v = omap_ctrl_readw(uart->padconf); | |
271 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | |
272 | omap_ctrl_writew(v, uart->padconf); | |
273 | } | |
274 | } | |
275 | ||
4af4016c KH |
276 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
277 | int enable) | |
278 | { | |
279 | struct plat_serial8250_port *p = uart->p; | |
280 | u16 sysc; | |
281 | ||
282 | sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; | |
283 | if (enable) | |
284 | sysc |= 0x2 << 3; | |
285 | else | |
286 | sysc |= 0x1 << 3; | |
287 | ||
288 | serial_write_reg(p, UART_OMAP_SYSC, sysc); | |
289 | } | |
290 | ||
291 | static void omap_uart_block_sleep(struct omap_uart_state *uart) | |
292 | { | |
293 | omap_uart_enable_clocks(uart); | |
294 | ||
295 | omap_uart_smart_idle_enable(uart, 0); | |
296 | uart->can_sleep = 0; | |
ba87a9be JH |
297 | if (uart->timeout) |
298 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
299 | else | |
300 | del_timer(&uart->timer); | |
4af4016c KH |
301 | } |
302 | ||
303 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
304 | { | |
fd455ea8 KH |
305 | if (device_may_wakeup(&uart->pdev.dev)) |
306 | omap_uart_enable_wakeup(uart); | |
307 | else | |
308 | omap_uart_disable_wakeup(uart); | |
309 | ||
4af4016c KH |
310 | if (!uart->clocked) |
311 | return; | |
312 | ||
313 | omap_uart_smart_idle_enable(uart, 1); | |
314 | uart->can_sleep = 1; | |
315 | del_timer(&uart->timer); | |
316 | } | |
317 | ||
318 | static void omap_uart_idle_timer(unsigned long data) | |
319 | { | |
320 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
321 | ||
322 | omap_uart_allow_sleep(uart); | |
323 | } | |
324 | ||
325 | void omap_uart_prepare_idle(int num) | |
326 | { | |
327 | struct omap_uart_state *uart; | |
328 | ||
329 | list_for_each_entry(uart, &uart_list, node) { | |
330 | if (num == uart->num && uart->can_sleep) { | |
331 | omap_uart_disable_clocks(uart); | |
332 | return; | |
333 | } | |
334 | } | |
335 | } | |
336 | ||
337 | void omap_uart_resume_idle(int num) | |
338 | { | |
339 | struct omap_uart_state *uart; | |
340 | ||
341 | list_for_each_entry(uart, &uart_list, node) { | |
342 | if (num == uart->num) { | |
343 | omap_uart_enable_clocks(uart); | |
344 | ||
345 | /* Check for IO pad wakeup */ | |
346 | if (cpu_is_omap34xx() && uart->padconf) { | |
347 | u16 p = omap_ctrl_readw(uart->padconf); | |
348 | ||
349 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) | |
350 | omap_uart_block_sleep(uart); | |
6e81176d | 351 | } |
4af4016c KH |
352 | |
353 | /* Check for normal UART wakeup */ | |
354 | if (__raw_readl(uart->wk_st) & uart->wk_mask) | |
355 | omap_uart_block_sleep(uart); | |
4af4016c KH |
356 | return; |
357 | } | |
358 | } | |
359 | } | |
360 | ||
361 | void omap_uart_prepare_suspend(void) | |
362 | { | |
363 | struct omap_uart_state *uart; | |
364 | ||
365 | list_for_each_entry(uart, &uart_list, node) { | |
366 | omap_uart_allow_sleep(uart); | |
367 | } | |
368 | } | |
369 | ||
370 | int omap_uart_can_sleep(void) | |
371 | { | |
372 | struct omap_uart_state *uart; | |
373 | int can_sleep = 1; | |
374 | ||
375 | list_for_each_entry(uart, &uart_list, node) { | |
376 | if (!uart->clocked) | |
377 | continue; | |
378 | ||
379 | if (!uart->can_sleep) { | |
380 | can_sleep = 0; | |
381 | continue; | |
6e81176d | 382 | } |
4af4016c KH |
383 | |
384 | /* This UART can now safely sleep. */ | |
385 | omap_uart_allow_sleep(uart); | |
6e81176d | 386 | } |
4af4016c KH |
387 | |
388 | return can_sleep; | |
6e81176d JH |
389 | } |
390 | ||
4af4016c KH |
391 | /** |
392 | * omap_uart_interrupt() | |
393 | * | |
394 | * This handler is used only to detect that *any* UART interrupt has | |
395 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
396 | * any UART interrupt will trigger the inactivity timer so the | |
397 | * UART will not idle or sleep for its timeout period. | |
398 | * | |
399 | **/ | |
400 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) | |
401 | { | |
402 | struct omap_uart_state *uart = dev_id; | |
403 | ||
404 | omap_uart_block_sleep(uart); | |
405 | ||
406 | return IRQ_NONE; | |
407 | } | |
408 | ||
409 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
410 | { | |
4af4016c KH |
411 | struct plat_serial8250_port *p = uart->p; |
412 | int ret; | |
413 | ||
414 | uart->can_sleep = 0; | |
fd455ea8 | 415 | uart->timeout = DEFAULT_TIMEOUT; |
4af4016c KH |
416 | setup_timer(&uart->timer, omap_uart_idle_timer, |
417 | (unsigned long) uart); | |
418 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
419 | omap_uart_smart_idle_enable(uart, 0); | |
420 | ||
421 | if (cpu_is_omap34xx()) { | |
422 | u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; | |
423 | u32 wk_mask = 0; | |
424 | u32 padconf = 0; | |
425 | ||
426 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); | |
427 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
428 | switch (uart->num) { | |
429 | case 0: | |
430 | wk_mask = OMAP3430_ST_UART1_MASK; | |
431 | padconf = 0x182; | |
432 | break; | |
433 | case 1: | |
434 | wk_mask = OMAP3430_ST_UART2_MASK; | |
435 | padconf = 0x17a; | |
436 | break; | |
437 | case 2: | |
438 | wk_mask = OMAP3430_ST_UART3_MASK; | |
439 | padconf = 0x19e; | |
440 | break; | |
441 | } | |
442 | uart->wk_mask = wk_mask; | |
443 | uart->padconf = padconf; | |
444 | } else if (cpu_is_omap24xx()) { | |
445 | u32 wk_mask = 0; | |
446 | ||
447 | if (cpu_is_omap2430()) { | |
448 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
449 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
450 | } else if (cpu_is_omap2420()) { | |
451 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
452 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
453 | } | |
454 | switch (uart->num) { | |
455 | case 0: | |
456 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
457 | break; | |
458 | case 1: | |
459 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
460 | break; | |
461 | case 2: | |
462 | wk_mask = OMAP24XX_ST_UART3_MASK; | |
463 | break; | |
464 | } | |
465 | uart->wk_mask = wk_mask; | |
466 | } else { | |
467 | uart->wk_en = 0; | |
468 | uart->wk_st = 0; | |
469 | uart->wk_mask = 0; | |
470 | uart->padconf = 0; | |
471 | } | |
472 | ||
c426df87 | 473 | p->irqflags |= IRQF_SHARED; |
4af4016c KH |
474 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, |
475 | "serial idle", (void *)uart); | |
476 | WARN_ON(ret); | |
477 | } | |
478 | ||
2466211e TK |
479 | void omap_uart_enable_irqs(int enable) |
480 | { | |
481 | int ret; | |
482 | struct omap_uart_state *uart; | |
483 | ||
484 | list_for_each_entry(uart, &uart_list, node) { | |
485 | if (enable) | |
486 | ret = request_irq(uart->p->irq, omap_uart_interrupt, | |
487 | IRQF_SHARED, "serial idle", (void *)uart); | |
488 | else | |
489 | free_irq(uart->p->irq, (void *)uart); | |
490 | } | |
491 | } | |
492 | ||
fd455ea8 KH |
493 | static ssize_t sleep_timeout_show(struct device *dev, |
494 | struct device_attribute *attr, | |
ba87a9be JH |
495 | char *buf) |
496 | { | |
fd455ea8 KH |
497 | struct platform_device *pdev = container_of(dev, |
498 | struct platform_device, dev); | |
499 | struct omap_uart_state *uart = container_of(pdev, | |
500 | struct omap_uart_state, pdev); | |
501 | ||
502 | return sprintf(buf, "%u\n", uart->timeout / HZ); | |
ba87a9be JH |
503 | } |
504 | ||
fd455ea8 KH |
505 | static ssize_t sleep_timeout_store(struct device *dev, |
506 | struct device_attribute *attr, | |
ba87a9be JH |
507 | const char *buf, size_t n) |
508 | { | |
fd455ea8 KH |
509 | struct platform_device *pdev = container_of(dev, |
510 | struct platform_device, dev); | |
511 | struct omap_uart_state *uart = container_of(pdev, | |
512 | struct omap_uart_state, pdev); | |
ba87a9be JH |
513 | unsigned int value; |
514 | ||
515 | if (sscanf(buf, "%u", &value) != 1) { | |
516 | printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); | |
517 | return -EINVAL; | |
518 | } | |
fd455ea8 KH |
519 | |
520 | uart->timeout = value * HZ; | |
521 | if (uart->timeout) | |
522 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
523 | else | |
524 | /* A zero value means disable timeout feature */ | |
525 | omap_uart_block_sleep(uart); | |
526 | ||
ba87a9be JH |
527 | return n; |
528 | } | |
529 | ||
fd455ea8 KH |
530 | DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); |
531 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) | |
4af4016c KH |
532 | #else |
533 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
fd455ea8 | 534 | #define DEV_CREATE_FILE(dev, attr) |
4af4016c KH |
535 | #endif /* CONFIG_PM */ |
536 | ||
9d30b99f | 537 | static struct omap_uart_state omap_uart[] = { |
fd455ea8 KH |
538 | { |
539 | .pdev = { | |
540 | .name = "serial8250", | |
541 | .id = PLAT8250_DEV_PLATFORM, | |
542 | .dev = { | |
543 | .platform_data = serial_platform_data0, | |
544 | }, | |
545 | }, | |
546 | }, { | |
547 | .pdev = { | |
548 | .name = "serial8250", | |
549 | .id = PLAT8250_DEV_PLATFORM1, | |
550 | .dev = { | |
551 | .platform_data = serial_platform_data1, | |
552 | }, | |
553 | }, | |
554 | }, { | |
555 | .pdev = { | |
556 | .name = "serial8250", | |
557 | .id = PLAT8250_DEV_PLATFORM2, | |
558 | .dev = { | |
559 | .platform_data = serial_platform_data2, | |
560 | }, | |
561 | }, | |
2aa57be2 | 562 | }, |
0e3eaadf SS |
563 | #ifdef CONFIG_ARCH_OMAP4 |
564 | { | |
565 | .pdev = { | |
566 | .name = "serial8250", | |
61f04ee8 | 567 | .id = 3, |
0e3eaadf SS |
568 | .dev = { |
569 | .platform_data = serial_platform_data3, | |
570 | }, | |
571 | }, | |
572 | }, | |
573 | #endif | |
2aa57be2 VP |
574 | }; |
575 | ||
ce13d471 | 576 | /* |
577 | * Override the default 8250 read handler: mem_serial_in() | |
578 | * Empty RX fifo read causes an abort on omap3630 and omap4 | |
579 | * This function makes sure that an empty rx fifo is not read on these silicons | |
580 | * (OMAP1/2/3430 are not affected) | |
581 | */ | |
582 | static unsigned int serial_in_override(struct uart_port *up, int offset) | |
583 | { | |
584 | if (UART_RX == offset) { | |
585 | unsigned int lsr; | |
586 | lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR); | |
587 | if (!(lsr & UART_LSR_DR)) | |
588 | return -EPERM; | |
589 | } | |
590 | return serial_read_reg(omap_uart[up->line].p, offset); | |
591 | } | |
592 | ||
b3c6df3a | 593 | void __init omap_serial_early_init(void) |
1dbae815 | 594 | { |
fd455ea8 | 595 | int i; |
6e81176d | 596 | char name[16]; |
1dbae815 TL |
597 | |
598 | /* | |
599 | * Make sure the serial ports are muxed on at this point. | |
600 | * You have to mux them off in device drivers later on | |
601 | * if not needed. | |
602 | */ | |
603 | ||
9d30b99f | 604 | for (i = 0; i < ARRAY_SIZE(omap_uart); i++) { |
4af4016c | 605 | struct omap_uart_state *uart = &omap_uart[i]; |
fd455ea8 KH |
606 | struct platform_device *pdev = &uart->pdev; |
607 | struct device *dev = &pdev->dev; | |
608 | struct plat_serial8250_port *p = dev->platform_data; | |
1dbae815 | 609 | |
84f90c9c TL |
610 | /* |
611 | * Module 4KB + L4 interconnect 4KB | |
612 | * Static mapping, never released | |
613 | */ | |
614 | p->membase = ioremap(p->mapbase, SZ_8K); | |
615 | if (!p->membase) { | |
616 | printk(KERN_ERR "ioremap failed for uart%i\n", i + 1); | |
617 | continue; | |
618 | } | |
619 | ||
6e81176d | 620 | sprintf(name, "uart%d_ick", i+1); |
4af4016c KH |
621 | uart->ick = clk_get(NULL, name); |
622 | if (IS_ERR(uart->ick)) { | |
6e81176d | 623 | printk(KERN_ERR "Could not get uart%d_ick\n", i+1); |
4af4016c KH |
624 | uart->ick = NULL; |
625 | } | |
6e81176d JH |
626 | |
627 | sprintf(name, "uart%d_fck", i+1); | |
4af4016c KH |
628 | uart->fck = clk_get(NULL, name); |
629 | if (IS_ERR(uart->fck)) { | |
6e81176d | 630 | printk(KERN_ERR "Could not get uart%d_fck\n", i+1); |
4af4016c KH |
631 | uart->fck = NULL; |
632 | } | |
633 | ||
aae290fb SS |
634 | /* FIXME: Remove this once the clkdev is ready */ |
635 | if (!cpu_is_omap44xx()) { | |
636 | if (!uart->ick || !uart->fck) | |
637 | continue; | |
638 | } | |
4af4016c KH |
639 | |
640 | uart->num = i; | |
641 | p->private_data = uart; | |
642 | uart->p = p; | |
1dbae815 | 643 | |
4789998a KH |
644 | if (cpu_is_omap44xx()) |
645 | p->irq += 32; | |
b3c6df3a PW |
646 | } |
647 | } | |
648 | ||
f62349ee MW |
649 | /** |
650 | * omap_serial_init_port() - initialize single serial port | |
651 | * @port: serial port number (0-3) | |
652 | * | |
653 | * This function initialies serial driver for given @port only. | |
654 | * Platforms can call this function instead of omap_serial_init() | |
655 | * if they don't plan to use all available UARTs as serial ports. | |
656 | * | |
657 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | |
658 | * use only one of the two. | |
659 | */ | |
660 | void __init omap_serial_init_port(int port) | |
b3c6df3a | 661 | { |
f62349ee MW |
662 | struct omap_uart_state *uart; |
663 | struct platform_device *pdev; | |
664 | struct device *dev; | |
b3c6df3a | 665 | |
f62349ee MW |
666 | BUG_ON(port < 0); |
667 | BUG_ON(port >= ARRAY_SIZE(omap_uart)); | |
b3c6df3a | 668 | |
f62349ee MW |
669 | uart = &omap_uart[port]; |
670 | pdev = &uart->pdev; | |
671 | dev = &pdev->dev; | |
970a724d | 672 | |
f2eeeae0 MW |
673 | omap_uart_enable_clocks(uart); |
674 | ||
f62349ee MW |
675 | omap_uart_reset(uart); |
676 | omap_uart_idle_init(uart); | |
677 | ||
f2eeeae0 MW |
678 | list_add_tail(&uart->node, &uart_list); |
679 | ||
f62349ee MW |
680 | if (WARN_ON(platform_device_register(pdev))) |
681 | return; | |
682 | ||
683 | if ((cpu_is_omap34xx() && uart->padconf) || | |
684 | (uart->wk_en && uart->wk_mask)) { | |
685 | device_init_wakeup(dev, true); | |
686 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | |
fd455ea8 | 687 | } |
f62349ee | 688 | |
ce13d471 | 689 | /* omap44xx: Never read empty UART fifo |
690 | * omap3xxx: Never read empty UART fifo on UARTs | |
691 | * with IP rev >=0x52 | |
692 | */ | |
693 | if (cpu_is_omap44xx()) | |
694 | uart->p->serial_in = serial_in_override; | |
695 | else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) | |
696 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) | |
697 | uart->p->serial_in = serial_in_override; | |
f62349ee MW |
698 | } |
699 | ||
700 | /** | |
701 | * omap_serial_init() - intialize all supported serial ports | |
702 | * | |
703 | * Initializes all available UARTs as serial ports. Platforms | |
704 | * can call this function when they want to have default behaviour | |
705 | * for serial ports (e.g initialize them all as serial ports). | |
706 | */ | |
707 | void __init omap_serial_init(void) | |
708 | { | |
709 | int i; | |
710 | ||
711 | for (i = 0; i < ARRAY_SIZE(omap_uart); i++) | |
712 | omap_serial_init_port(i); | |
1dbae815 | 713 | } |