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omap2/3/4: serial: introduce errata handling
[linux-2.6-block.git] / arch / arm / mach-omap2 / serial.c
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1dbae815 1/*
f30c2269 2 * arch/arm/mach-omap2/serial.c
1dbae815
TL		 3 *
4 * OMAP2 serial support.
5 *
6e81176d 6 * Copyright (C) 2005-2008 Nokia Corporation
1dbae815
TL		 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
4af4016c
KH		 9 * Major rework for PM support by Kevin Hilman
10 *
1dbae815
TL		 11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
1dbae815
TL		 16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_reg.h>
f8ce2547 24#include <linux/clk.h>
fced80c7 25#include <linux/io.h>
e03d37d8 26#include <linux/delay.h>
1dbae815 27
ce491cf8
TL		 28#include <plat/common.h>
29#include <plat/board.h>
30#include <plat/clock.h>
31#include <plat/control.h>
4af4016c
KH		 32
33#include "prm.h"
34#include "pm.h"
35#include "prm-regbits-34xx.h"
36
ce13d471 37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
4af4016c
KH		 38#define UART_OMAP_WER 0x17 /* Wake-up enable register */
39
5a927b36
NM		 40#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
41
301fe8ee
TL		 42/*
43 * NOTE: By default the serial timeout is disabled as it causes lost characters
44 * over the serial ports. This means that the UART clocks will stay on until
45 * disabled via sysfs. This also causes that any deeper omap sleep states are
46 * blocked.
47 */
48#define DEFAULT_TIMEOUT 0
4af4016c
KH		 49
50struct omap_uart_state {
51 int num;
52 int can_sleep;
53 struct timer_list timer;
54 u32 timeout;
55
56 void __iomem *wk_st;
57 void __iomem *wk_en;
58 u32 wk_mask;
59 u32 padconf;
60
61 struct clk *ick;
62 struct clk *fck;
63 int clocked;
64
65 struct plat_serial8250_port *p;
66 struct list_head node;
fd455ea8 67 struct platform_device pdev;
1dbae815 68
5a927b36 69 u32 errata;
4af4016c
KH		 70#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
71 int context_valid;
72
73 /* Registers to be saved/restored for OFF-mode */
74 u16 dll;
75 u16 dlh;
76 u16 ier;
77 u16 sysc;
78 u16 scr;
79 u16 wer;
5ade4ff5 80 u16 mcr;
4af4016c
KH		 81#endif
82};
83
4af4016c 84static LIST_HEAD(uart_list);
1dbae815 85
fd455ea8 86static struct plat_serial8250_port serial_platform_data0[] = {
1dbae815 87 {
1dbae815
TL		 88 .irq = 72,
89 .flags = UPF_BOOT_AUTOCONF,
90 .iotype = UPIO_MEM,
91 .regshift = 2,
6e81176d 92 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 93 }, {
fd455ea8
KH		 94 .flags = 0
95 }
96};
97
98static struct plat_serial8250_port serial_platform_data1[] = {
99 {
1dbae815
TL		 100 .irq = 73,
101 .flags = UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM,
103 .regshift = 2,
6e81176d 104 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 105 }, {
fd455ea8
KH		 106 .flags = 0
107 }
108};
109
110static struct plat_serial8250_port serial_platform_data2[] = {
111 {
1dbae815
TL		 112 .irq = 74,
113 .flags = UPF_BOOT_AUTOCONF,
114 .iotype = UPIO_MEM,
115 .regshift = 2,
6e81176d 116 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815
TL		 117 }, {
118 .flags = 0
119 }
120};
121
0e3eaadf
SS		 122static struct plat_serial8250_port serial_platform_data3[] = {
123 {
0e3eaadf
SS		 124 .irq = 70,
125 .flags = UPF_BOOT_AUTOCONF,
126 .iotype = UPIO_MEM,
127 .regshift = 2,
128 .uartclk = OMAP24XX_BASE_BAUD * 16,
129 }, {
130 .flags = 0
131 }
132};
a3a9b36e 133
4f2c49fe
TL		 134void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
135{
136 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
137 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
138 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
4b1bbd3f 139 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
4f2c49fe
TL		 140}
141
9230372a
AS		 142static inline unsigned int __serial_read_reg(struct uart_port *up,
143 int offset)
144{
145 offset <<= up->regshift;
146 return (unsigned int)__raw_readb(up->membase + offset);
147}
148
1dbae815
TL		 149static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
150 int offset)
151{
152 offset <<= up->regshift;
153 return (unsigned int)__raw_readb(up->membase + offset);
154}
155
e03d37d8
SS		 156static inline void __serial_write_reg(struct uart_port *up, int offset,
157 int value)
158{
159 offset <<= up->regshift;
160 __raw_writeb(value, up->membase + offset);
161}
162
1dbae815
TL		 163static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
164 int value)
165{
166 offset <<= p->regshift;
e8a91c95 167 __raw_writeb(value, p->membase + offset);
1dbae815
TL		 168}
169
170/*
171 * Internal UARTs need to be initialized for the 8250 autoconfig to work
172 * properly. Note that the TX watermark initialization may not be needed
173 * once the 8250.c watermark handling code is merged.
174 */
4af4016c 175static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815 176{
4af4016c
KH		 177 struct plat_serial8250_port *p = uart->p;
178
1dbae815
TL		 179 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
180 serial_write_reg(p, UART_OMAP_SCR, 0x08);
181 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
671c7235 182 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
1dbae815
TL		 183}
184
4af4016c
KH		 185#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
186
4af4016c 187static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d 188{
4af4016c
KH		 189 u16 lcr = 0;
190 struct plat_serial8250_port *p = uart->p;
191
192 if (!enable_off_mode)
193 return;
194
195 lcr = serial_read_reg(p, UART_LCR);
196 serial_write_reg(p, UART_LCR, 0xBF);
197 uart->dll = serial_read_reg(p, UART_DLL);
198 uart->dlh = serial_read_reg(p, UART_DLM);
199 serial_write_reg(p, UART_LCR, lcr);
200 uart->ier = serial_read_reg(p, UART_IER);
201 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
202 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
203 uart->wer = serial_read_reg(p, UART_OMAP_WER);
5ade4ff5
G		 204 serial_write_reg(p, UART_LCR, 0x80);
205 uart->mcr = serial_read_reg(p, UART_MCR);
206 serial_write_reg(p, UART_LCR, lcr);
4af4016c
KH		 207
208 uart->context_valid = 1;
209}
210
211static void omap_uart_restore_context(struct omap_uart_state *uart)
212{
213 u16 efr = 0;
214 struct plat_serial8250_port *p = uart->p;
215
216 if (!enable_off_mode)
217 return;
218
219 if (!uart->context_valid)
220 return;
221
222 uart->context_valid = 0;
223
224 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
225 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
226 efr = serial_read_reg(p, UART_EFR);
227 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
228 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
229 serial_write_reg(p, UART_IER, 0x0);
230 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
231 serial_write_reg(p, UART_DLL, uart->dll);
232 serial_write_reg(p, UART_DLM, uart->dlh);
233 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
234 serial_write_reg(p, UART_IER, uart->ier);
5ade4ff5
G		 235 serial_write_reg(p, UART_LCR, 0x80);
236 serial_write_reg(p, UART_MCR, uart->mcr);
4af4016c
KH		 237 serial_write_reg(p, UART_FCR, 0xA1);
238 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
239 serial_write_reg(p, UART_EFR, efr);
240 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
241 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
242 serial_write_reg(p, UART_OMAP_WER, uart->wer);
243 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
244 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
245}
246#else
247static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
248static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
249#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
250
251static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
252{
253 if (uart->clocked)
254 return;
255
256 clk_enable(uart->ick);
257 clk_enable(uart->fck);
258 uart->clocked = 1;
259 omap_uart_restore_context(uart);
260}
261
262#ifdef CONFIG_PM
263
264static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
265{
266 if (!uart->clocked)
267 return;
268
269 omap_uart_save_context(uart);
270 uart->clocked = 0;
271 clk_disable(uart->ick);
272 clk_disable(uart->fck);
273}
274
fd455ea8
KH		 275static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
276{
277 /* Set wake-enable bit */
278 if (uart->wk_en && uart->wk_mask) {
279 u32 v = __raw_readl(uart->wk_en);
280 v |= uart->wk_mask;
281 __raw_writel(v, uart->wk_en);
282 }
283
284 /* Ensure IOPAD wake-enables are set */
285 if (cpu_is_omap34xx() && uart->padconf) {
286 u16 v = omap_ctrl_readw(uart->padconf);
287 v |= OMAP3_PADCONF_WAKEUPENABLE0;
288 omap_ctrl_writew(v, uart->padconf);
289 }
290}
291
292static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
293{
294 /* Clear wake-enable bit */
295 if (uart->wk_en && uart->wk_mask) {
296 u32 v = __raw_readl(uart->wk_en);
297 v &= ~uart->wk_mask;
298 __raw_writel(v, uart->wk_en);
299 }
300
301 /* Ensure IOPAD wake-enables are cleared */
302 if (cpu_is_omap34xx() && uart->padconf) {
303 u16 v = omap_ctrl_readw(uart->padconf);
304 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
305 omap_ctrl_writew(v, uart->padconf);
306 }
307}
308
4af4016c
KH		 309static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
310 int enable)
311{
312 struct plat_serial8250_port *p = uart->p;
313 u16 sysc;
314
315 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
316 if (enable)
317 sysc |= 0x2 << 3;
318 else
319 sysc |= 0x1 << 3;
320
321 serial_write_reg(p, UART_OMAP_SYSC, sysc);
322}
323
324static void omap_uart_block_sleep(struct omap_uart_state *uart)
325{
326 omap_uart_enable_clocks(uart);
327
328 omap_uart_smart_idle_enable(uart, 0);
329 uart->can_sleep = 0;
ba87a9be
JH		 330 if (uart->timeout)
331 mod_timer(&uart->timer, jiffies + uart->timeout);
332 else
333 del_timer(&uart->timer);
4af4016c
KH		 334}
335
336static void omap_uart_allow_sleep(struct omap_uart_state *uart)
337{
fd455ea8
KH		 338 if (device_may_wakeup(&uart->pdev.dev))
339 omap_uart_enable_wakeup(uart);
340 else
341 omap_uart_disable_wakeup(uart);
342
4af4016c
KH		 343 if (!uart->clocked)
344 return;
345
346 omap_uart_smart_idle_enable(uart, 1);
347 uart->can_sleep = 1;
348 del_timer(&uart->timer);
349}
350
351static void omap_uart_idle_timer(unsigned long data)
352{
353 struct omap_uart_state *uart = (struct omap_uart_state *)data;
354
355 omap_uart_allow_sleep(uart);
356}
357
358void omap_uart_prepare_idle(int num)
359{
360 struct omap_uart_state *uart;
361
362 list_for_each_entry(uart, &uart_list, node) {
363 if (num == uart->num && uart->can_sleep) {
364 omap_uart_disable_clocks(uart);
365 return;
366 }
367 }
368}
369
370void omap_uart_resume_idle(int num)
371{
372 struct omap_uart_state *uart;
373
374 list_for_each_entry(uart, &uart_list, node) {
375 if (num == uart->num) {
376 omap_uart_enable_clocks(uart);
377
378 /* Check for IO pad wakeup */
379 if (cpu_is_omap34xx() && uart->padconf) {
380 u16 p = omap_ctrl_readw(uart->padconf);
381
382 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
383 omap_uart_block_sleep(uart);
6e81176d 384 }
4af4016c
KH		 385
386 /* Check for normal UART wakeup */
387 if (__raw_readl(uart->wk_st) & uart->wk_mask)
388 omap_uart_block_sleep(uart);
4af4016c
KH		 389 return;
390 }
391 }
392}
393
394void omap_uart_prepare_suspend(void)
395{
396 struct omap_uart_state *uart;
397
398 list_for_each_entry(uart, &uart_list, node) {
399 omap_uart_allow_sleep(uart);
400 }
401}
402
403int omap_uart_can_sleep(void)
404{
405 struct omap_uart_state *uart;
406 int can_sleep = 1;
407
408 list_for_each_entry(uart, &uart_list, node) {
409 if (!uart->clocked)
410 continue;
411
412 if (!uart->can_sleep) {
413 can_sleep = 0;
414 continue;
6e81176d 415 }
4af4016c
KH		 416
417 /* This UART can now safely sleep. */
418 omap_uart_allow_sleep(uart);
6e81176d 419 }
4af4016c
KH		 420
421 return can_sleep;
6e81176d
JH		 422}
423
4af4016c
KH		 424/**
425 * omap_uart_interrupt()
426 *
427 * This handler is used only to detect that *any* UART interrupt has
428 * occurred. It does _nothing_ to handle the interrupt. Rather,
429 * any UART interrupt will trigger the inactivity timer so the
430 * UART will not idle or sleep for its timeout period.
431 *
432 **/
433static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
434{
435 struct omap_uart_state *uart = dev_id;
436
437 omap_uart_block_sleep(uart);
438
439 return IRQ_NONE;
440}
441
442static void omap_uart_idle_init(struct omap_uart_state *uart)
443{
4af4016c
KH		 444 struct plat_serial8250_port *p = uart->p;
445 int ret;
446
447 uart->can_sleep = 0;
fd455ea8 448 uart->timeout = DEFAULT_TIMEOUT;
4af4016c
KH		 449 setup_timer(&uart->timer, omap_uart_idle_timer,
450 (unsigned long) uart);
301fe8ee
TL		 451 if (uart->timeout)
452 mod_timer(&uart->timer, jiffies + uart->timeout);
4af4016c
KH		 453 omap_uart_smart_idle_enable(uart, 0);
454
455 if (cpu_is_omap34xx()) {
456 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
457 u32 wk_mask = 0;
458 u32 padconf = 0;
459
460 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
461 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
462 switch (uart->num) {
463 case 0:
464 wk_mask = OMAP3430_ST_UART1_MASK;
465 padconf = 0x182;
466 break;
467 case 1:
468 wk_mask = OMAP3430_ST_UART2_MASK;
469 padconf = 0x17a;
470 break;
471 case 2:
472 wk_mask = OMAP3430_ST_UART3_MASK;
473 padconf = 0x19e;
474 break;
475 }
476 uart->wk_mask = wk_mask;
477 uart->padconf = padconf;
478 } else if (cpu_is_omap24xx()) {
479 u32 wk_mask = 0;
480
481 if (cpu_is_omap2430()) {
482 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
483 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
484 } else if (cpu_is_omap2420()) {
485 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
486 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
487 }
488 switch (uart->num) {
489 case 0:
490 wk_mask = OMAP24XX_ST_UART1_MASK;
491 break;
492 case 1:
493 wk_mask = OMAP24XX_ST_UART2_MASK;
494 break;
495 case 2:
496 wk_mask = OMAP24XX_ST_UART3_MASK;
497 break;
498 }
499 uart->wk_mask = wk_mask;
500 } else {
c54bae1f
NM		 501 uart->wk_en = NULL;
502 uart->wk_st = NULL;
4af4016c
KH		 503 uart->wk_mask = 0;
504 uart->padconf = 0;
505 }
506
c426df87 507 p->irqflags |= IRQF_SHARED;
4af4016c
KH		 508 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
509 "serial idle", (void *)uart);
510 WARN_ON(ret);
511}
512
2466211e
TK		 513void omap_uart_enable_irqs(int enable)
514{
515 int ret;
516 struct omap_uart_state *uart;
517
518 list_for_each_entry(uart, &uart_list, node) {
519 if (enable)
520 ret = request_irq(uart->p->irq, omap_uart_interrupt,
521 IRQF_SHARED, "serial idle", (void *)uart);
522 else
523 free_irq(uart->p->irq, (void *)uart);
524 }
525}
526
fd455ea8
KH		 527static ssize_t sleep_timeout_show(struct device *dev,
528 struct device_attribute *attr,
ba87a9be
JH		 529 char *buf)
530{
fd455ea8
KH		 531 struct platform_device *pdev = container_of(dev,
532 struct platform_device, dev);
533 struct omap_uart_state *uart = container_of(pdev,
534 struct omap_uart_state, pdev);
535
536 return sprintf(buf, "%u\n", uart->timeout / HZ);
ba87a9be
JH		 537}
538
fd455ea8
KH		 539static ssize_t sleep_timeout_store(struct device *dev,
540 struct device_attribute *attr,
ba87a9be
JH		 541 const char *buf, size_t n)
542{
fd455ea8
KH		 543 struct platform_device *pdev = container_of(dev,
544 struct platform_device, dev);
545 struct omap_uart_state *uart = container_of(pdev,
546 struct omap_uart_state, pdev);
ba87a9be
JH		 547 unsigned int value;
548
549 if (sscanf(buf, "%u", &value) != 1) {
10c805eb 550 dev_err(dev, "sleep_timeout_store: Invalid value\n");
ba87a9be
JH		 551 return -EINVAL;
552 }
fd455ea8
KH		 553
554 uart->timeout = value * HZ;
555 if (uart->timeout)
556 mod_timer(&uart->timer, jiffies + uart->timeout);
557 else
558 /* A zero value means disable timeout feature */
559 omap_uart_block_sleep(uart);
560
ba87a9be
JH		 561 return n;
562}
563
bfe6977a
NM		 564static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
565 sleep_timeout_store);
fd455ea8 566#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
4af4016c
KH		 567#else
568static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
fd455ea8 569#define DEV_CREATE_FILE(dev, attr)
4af4016c
KH		 570#endif /* CONFIG_PM */
571
9d30b99f 572static struct omap_uart_state omap_uart[] = {
fd455ea8
KH		 573 {
574 .pdev = {
575 .name = "serial8250",
576 .id = PLAT8250_DEV_PLATFORM,
577 .dev = {
578 .platform_data = serial_platform_data0,
579 },
580 },
581 }, {
582 .pdev = {
583 .name = "serial8250",
584 .id = PLAT8250_DEV_PLATFORM1,
585 .dev = {
586 .platform_data = serial_platform_data1,
587 },
588 },
589 }, {
590 .pdev = {
591 .name = "serial8250",
592 .id = PLAT8250_DEV_PLATFORM2,
593 .dev = {
594 .platform_data = serial_platform_data2,
595 },
596 },
2aa57be2 597 },
a3a9b36e 598#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
0e3eaadf
SS		 599 {
600 .pdev = {
601 .name = "serial8250",
61f04ee8 602 .id = 3,
0e3eaadf
SS		 603 .dev = {
604 .platform_data = serial_platform_data3,
605 },
606 },
607 },
608#endif
2aa57be2
VP		 609};
610
ce13d471 611/*
612 * Override the default 8250 read handler: mem_serial_in()
613 * Empty RX fifo read causes an abort on omap3630 and omap4
614 * This function makes sure that an empty rx fifo is not read on these silicons
615 * (OMAP1/2/3430 are not affected)
616 */
617static unsigned int serial_in_override(struct uart_port *up, int offset)
618{
619 if (UART_RX == offset) {
620 unsigned int lsr;
9230372a 621 lsr = __serial_read_reg(up, UART_LSR);
ce13d471 622 if (!(lsr & UART_LSR_DR))
623 return -EPERM;
624 }
9230372a
AS		 625
626 return __serial_read_reg(up, offset);
ce13d471 627}
628
e03d37d8
SS		 629static void serial_out_override(struct uart_port *up, int offset, int value)
630{
631 unsigned int status, tmout = 10000;
632
633 status = __serial_read_reg(up, UART_LSR);
634 while (!(status & UART_LSR_THRE)) {
635 /* Wait up to 10ms for the character(s) to be sent. */
636 if (--tmout == 0)
637 break;
638 udelay(1);
639 status = __serial_read_reg(up, UART_LSR);
640 }
641 __serial_write_reg(up, offset, value);
642}
b3c6df3a 643void __init omap_serial_early_init(void)
1dbae815 644{
21b90340 645 int i, nr_ports;
6e81176d 646 char name[16];
1dbae815 647
21b90340
TW		 648 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
649 nr_ports = 3;
650 else
651 nr_ports = ARRAY_SIZE(omap_uart);
652
1dbae815
TL		 653 /*
654 * Make sure the serial ports are muxed on at this point.
655 * You have to mux them off in device drivers later on
656 * if not needed.
657 */
658
21b90340 659 for (i = 0; i < nr_ports; i++) {
4af4016c 660 struct omap_uart_state *uart = &omap_uart[i];
fd455ea8
KH		 661 struct platform_device *pdev = &uart->pdev;
662 struct device *dev = &pdev->dev;
663 struct plat_serial8250_port *p = dev->platform_data;
1dbae815 664
e88d556d
SA		 665 /* Don't map zero-based physical address */
666 if (p->mapbase == 0) {
10c805eb
SA		 667 dev_warn(dev, "no physical address for uart#%d,"
668 " so skipping early_init...\n", i);
e88d556d
SA		 669 continue;
670 }
84f90c9c
TL		 671 /*
672 * Module 4KB + L4 interconnect 4KB
673 * Static mapping, never released
674 */
675 p->membase = ioremap(p->mapbase, SZ_8K);
676 if (!p->membase) {
10c805eb 677 dev_err(dev, "ioremap failed for uart%i\n", i + 1);
84f90c9c
TL		 678 continue;
679 }
680
21b90340 681 sprintf(name, "uart%d_ick", i + 1);
4af4016c
KH		 682 uart->ick = clk_get(NULL, name);
683 if (IS_ERR(uart->ick)) {
10c805eb 684 dev_err(dev, "Could not get uart%d_ick\n", i + 1);
4af4016c
KH		 685 uart->ick = NULL;
686 }
6e81176d
JH		 687
688 sprintf(name, "uart%d_fck", i+1);
4af4016c
KH		 689 uart->fck = clk_get(NULL, name);
690 if (IS_ERR(uart->fck)) {
10c805eb 691 dev_err(dev, "Could not get uart%d_fck\n", i + 1);
4af4016c
KH		 692 uart->fck = NULL;
693 }
694
aae290fb
SS		 695 /* FIXME: Remove this once the clkdev is ready */
696 if (!cpu_is_omap44xx()) {
697 if (!uart->ick || !uart->fck)
698 continue;
699 }
4af4016c
KH		 700
701 uart->num = i;
702 p->private_data = uart;
703 uart->p = p;
1dbae815 704
4789998a
KH		 705 if (cpu_is_omap44xx())
706 p->irq += 32;
b3c6df3a
PW		 707 }
708}
709
f62349ee
MW		 710/**
711 * omap_serial_init_port() - initialize single serial port
712 * @port: serial port number (0-3)
713 *
714 * This function initialies serial driver for given @port only.
715 * Platforms can call this function instead of omap_serial_init()
716 * if they don't plan to use all available UARTs as serial ports.
717 *
718 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
719 * use only one of the two.
720 */
721void __init omap_serial_init_port(int port)
b3c6df3a 722{
f62349ee
MW		 723 struct omap_uart_state *uart;
724 struct platform_device *pdev;
725 struct device *dev;
b3c6df3a 726
f62349ee
MW		 727 BUG_ON(port < 0);
728 BUG_ON(port >= ARRAY_SIZE(omap_uart));
b3c6df3a 729
f62349ee
MW		 730 uart = &omap_uart[port];
731 pdev = &uart->pdev;
732 dev = &pdev->dev;
970a724d 733
e88d556d
SA		 734 /* Don't proceed if there's no clocks available */
735 if (unlikely(!uart->ick || !uart->fck)) {
736 WARN(1, "%s: can't init uart%d, no clocks available\n",
737 kobject_name(&dev->kobj), port);
738 return;
739 }
740
f2eeeae0
MW		 741 omap_uart_enable_clocks(uart);
742
f62349ee
MW		 743 omap_uart_reset(uart);
744 omap_uart_idle_init(uart);
745
f2eeeae0
MW		 746 list_add_tail(&uart->node, &uart_list);
747
f62349ee
MW		 748 if (WARN_ON(platform_device_register(pdev)))
749 return;
750
751 if ((cpu_is_omap34xx() && uart->padconf) ||
752 (uart->wk_en && uart->wk_mask)) {
753 device_init_wakeup(dev, true);
754 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
fd455ea8 755 }
f62349ee 756
30e53bcc 757 /*
758 * omap44xx: Never read empty UART fifo
759 * omap3xxx: Never read empty UART fifo on UARTs
760 * with IP rev >=0x52
761 */
5a927b36
NM		 762 if (cpu_is_omap44xx())
763 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
764 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
765 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
766 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
767
768 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
30e53bcc 769 uart->p->serial_in = serial_in_override;
e03d37d8
SS		 770 uart->p->serial_out = serial_out_override;
771 }
f62349ee
MW		 772}
773
774/**
775 * omap_serial_init() - intialize all supported serial ports
776 *
777 * Initializes all available UARTs as serial ports. Platforms
778 * can call this function when they want to have default behaviour
779 * for serial ports (e.g initialize them all as serial ports).
780 */
781void __init omap_serial_init(void)
782{
a3a9b36e
TL		 783 int i, nr_ports;
784
785 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
786 nr_ports = 3;
787 else
788 nr_ports = ARRAY_SIZE(omap_uart);
f62349ee 789
a3a9b36e 790 for (i = 0; i < nr_ports; i++)
f62349ee 791 omap_serial_init_port(i);
1dbae815 792}
Linux 6.x block layer and io_uring tree(s)