[linux-2.6-block.git] / arch / arm / mach-omap2 / serial.c

/*
 * arch/arm/mach-omap2/serial.c
 *
 * OMAP2 serial support.
 *
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * Major rework for PM support by Kevin Hilman
 *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/common.h>
#include <mach/board.h>
#include <mach/clock.h>
#include <mach/control.h>

#include "prm.h"
#include "pm.h"
#include "prm-regbits-34xx.h"

#define UART_OMAP_WER		0x17	/* Wake-up enable register */

#define DEFAULT_TIMEOUT (5 * HZ)

struct omap_uart_state {
	int num;
	int can_sleep;
	struct timer_list timer;
	u32 timeout;

	void __iomem *wk_st;
	void __iomem *wk_en;
	u32 wk_mask;
	u32 padconf;

	struct clk *ick;
	struct clk *fck;
	int clocked;

	struct plat_serial8250_port *p;
	struct list_head node;
	struct platform_device pdev;

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	int context_valid;

	/* Registers to be saved/restored for OFF-mode */
	u16 dll;
	u16 dlh;
	u16 ier;
	u16 sysc;
	u16 scr;
	u16 wer;
#endif
};

static LIST_HEAD(uart_list);

static struct plat_serial8250_port serial_platform_data0[] = {
	{
		.membase	= OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
		.mapbase	= OMAP_UART1_BASE,
		.irq		= 72,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

static struct plat_serial8250_port serial_platform_data1[] = {
	{
		.membase	= OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
		.mapbase	= OMAP_UART2_BASE,
		.irq		= 73,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

static struct plat_serial8250_port serial_platform_data2[] = {
	{
		.membase	= OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
		.mapbase	= OMAP_UART3_BASE,
		.irq		= 74,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
					   int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
				    int value)
{
	offset <<= p->regshift;
	__raw_writeb(value, p->membase + offset);
}

/*
 * Internal UARTs need to be initialized for the 8250 autoconfig to work
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */
static inline void __init omap_uart_reset(struct omap_uart_state *uart)
{
	struct plat_serial8250_port *p = uart->p;

	serial_write_reg(p, UART_OMAP_MDR1, 0x07);
	serial_write_reg(p, UART_OMAP_SCR, 0x08);
	serial_write_reg(p, UART_OMAP_MDR1, 0x00);
	serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)

static int enable_off_mode; /* to be removed by full off-mode patches */

static void omap_uart_save_context(struct omap_uart_state *uart)
{
	u16 lcr = 0;
	struct plat_serial8250_port *p = uart->p;

	if (!enable_off_mode)
		return;

	lcr = serial_read_reg(p, UART_LCR);
	serial_write_reg(p, UART_LCR, 0xBF);
	uart->dll = serial_read_reg(p, UART_DLL);
	uart->dlh = serial_read_reg(p, UART_DLM);
	serial_write_reg(p, UART_LCR, lcr);
	uart->ier = serial_read_reg(p, UART_IER);
	uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
	uart->scr = serial_read_reg(p, UART_OMAP_SCR);
	uart->wer = serial_read_reg(p, UART_OMAP_WER);

	uart->context_valid = 1;
}

static void omap_uart_restore_context(struct omap_uart_state *uart)
{
	u16 efr = 0;
	struct plat_serial8250_port *p = uart->p;

	if (!enable_off_mode)
		return;

	if (!uart->context_valid)
		return;

	uart->context_valid = 0;

	serial_write_reg(p, UART_OMAP_MDR1, 0x7);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	efr = serial_read_reg(p, UART_EFR);
	serial_write_reg(p, UART_EFR, UART_EFR_ECB);
	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(p, UART_IER, 0x0);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	serial_write_reg(p, UART_DLL, uart->dll);
	serial_write_reg(p, UART_DLM, uart->dlh);
	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(p, UART_IER, uart->ier);
	serial_write_reg(p, UART_FCR, 0xA1);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	serial_write_reg(p, UART_EFR, efr);
	serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
	serial_write_reg(p, UART_OMAP_SCR, uart->scr);
	serial_write_reg(p, UART_OMAP_WER, uart->wer);
	serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
	serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
}
#else
static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */

static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
{
	if (uart->clocked)
		return;

	clk_enable(uart->ick);
	clk_enable(uart->fck);
	uart->clocked = 1;
	omap_uart_restore_context(uart);
}

#ifdef CONFIG_PM

static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
	if (!uart->clocked)
		return;

	omap_uart_save_context(uart);
	uart->clocked = 0;
	clk_disable(uart->ick);
	clk_disable(uart->fck);
}

static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
	/* Set wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v |= uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are set */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v |= OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
	/* Clear wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v &= ~uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are cleared */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
					  int enable)
{
	struct plat_serial8250_port *p = uart->p;
	u16 sysc;

	sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
	if (enable)
		sysc |= 0x2 << 3;
	else
		sysc |= 0x1 << 3;

	serial_write_reg(p, UART_OMAP_SYSC, sysc);
}

static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	omap_uart_enable_clocks(uart);

	omap_uart_smart_idle_enable(uart, 0);
	uart->can_sleep = 0;
	if (uart->timeout)
		mod_timer(&uart->timer, jiffies + uart->timeout);
	else
		del_timer(&uart->timer);
}

static void omap_uart_allow_sleep(struct omap_uart_state *uart)
{
	if (device_may_wakeup(&uart->pdev.dev))
		omap_uart_enable_wakeup(uart);
	else
		omap_uart_disable_wakeup(uart);

	if (!uart->clocked)
		return;

	omap_uart_smart_idle_enable(uart, 1);
	uart->can_sleep = 1;
	del_timer(&uart->timer);
}

static void omap_uart_idle_timer(unsigned long data)
{
	struct omap_uart_state *uart = (struct omap_uart_state *)data;

	omap_uart_allow_sleep(uart);
}

void omap_uart_prepare_idle(int num)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (num == uart->num && uart->can_sleep) {
			omap_uart_disable_clocks(uart);
			return;
		}
	}
}

void omap_uart_resume_idle(int num)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (num == uart->num) {
			omap_uart_enable_clocks(uart);

			/* Check for IO pad wakeup */
			if (cpu_is_omap34xx() && uart->padconf) {
				u16 p = omap_ctrl_readw(uart->padconf);

				if (p & OMAP3_PADCONF_WAKEUPEVENT0)
					omap_uart_block_sleep(uart);
			}

			/* Check for normal UART wakeup */
			if (__raw_readl(uart->wk_st) & uart->wk_mask)
				omap_uart_block_sleep(uart);
			return;
		}
	}
}

void omap_uart_prepare_suspend(void)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		omap_uart_allow_sleep(uart);
	}
}

int omap_uart_can_sleep(void)
{
	struct omap_uart_state *uart;
	int can_sleep = 1;

	list_for_each_entry(uart, &uart_list, node) {
		if (!uart->clocked)
			continue;

		if (!uart->can_sleep) {
			can_sleep = 0;
			continue;
		}

		/* This UART can now safely sleep. */
		omap_uart_allow_sleep(uart);
	}

	return can_sleep;
}

/**
 * omap_uart_interrupt()
 *
 * This handler is used only to detect that *any* UART interrupt has
 * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 * any UART interrupt will trigger the inactivity timer so the
 * UART will not idle or sleep for its timeout period.
 *
 **/
static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
{
	struct omap_uart_state *uart = dev_id;

	omap_uart_block_sleep(uart);

	return IRQ_NONE;
}

static void omap_uart_idle_init(struct omap_uart_state *uart)
{
	struct plat_serial8250_port *p = uart->p;
	int ret;

	uart->can_sleep = 0;
	uart->timeout = DEFAULT_TIMEOUT;
	setup_timer(&uart->timer, omap_uart_idle_timer,
		    (unsigned long) uart);
	mod_timer(&uart->timer, jiffies + uart->timeout);
	omap_uart_smart_idle_enable(uart, 0);

	if (cpu_is_omap34xx()) {
		u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
		u32 wk_mask = 0;
		u32 padconf = 0;

		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
		switch (uart->num) {
		case 0:
			wk_mask = OMAP3430_ST_UART1_MASK;
			padconf = 0x182;
			break;
		case 1:
			wk_mask = OMAP3430_ST_UART2_MASK;
			padconf = 0x17a;
			break;
		case 2:
			wk_mask = OMAP3430_ST_UART3_MASK;
			padconf = 0x19e;
			break;
		}
		uart->wk_mask = wk_mask;
		uart->padconf = padconf;
	} else if (cpu_is_omap24xx()) {
		u32 wk_mask = 0;

		if (cpu_is_omap2430()) {
			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
		} else if (cpu_is_omap2420()) {
			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
		}
		switch (uart->num) {
		case 0:
			wk_mask = OMAP24XX_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP24XX_ST_UART2_MASK;
			break;
		case 2:
			wk_mask = OMAP24XX_ST_UART3_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
	} else {
		uart->wk_en = 0;
		uart->wk_st = 0;
		uart->wk_mask = 0;
		uart->padconf = 0;
	}

	p->flags |= UPF_SHARE_IRQ;
	ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
			  "serial idle", (void *)uart);
	WARN_ON(ret);
}

void omap_uart_enable_irqs(int enable)
{
	int ret;
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (enable)
			ret = request_irq(uart->p->irq, omap_uart_interrupt,
				IRQF_SHARED, "serial idle", (void *)uart);
		else
			free_irq(uart->p->irq, (void *)uart);
	}
}

static ssize_t sleep_timeout_show(struct device *dev,
				  struct device_attribute *attr,
				  char *buf)
{
	struct platform_device *pdev = container_of(dev,
					struct platform_device, dev);
	struct omap_uart_state *uart = container_of(pdev,
					struct omap_uart_state, pdev);

	return sprintf(buf, "%u\n", uart->timeout / HZ);
}

static ssize_t sleep_timeout_store(struct device *dev,
				   struct device_attribute *attr,
				   const char *buf, size_t n)
{
	struct platform_device *pdev = container_of(dev,
					struct platform_device, dev);
	struct omap_uart_state *uart = container_of(pdev,
					struct omap_uart_state, pdev);
	unsigned int value;

	if (sscanf(buf, "%u", &value) != 1) {
		printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
		return -EINVAL;
	}

	uart->timeout = value * HZ;
	if (uart->timeout)
		mod_timer(&uart->timer, jiffies + uart->timeout);
	else
		/* A zero value means disable timeout feature */
		omap_uart_block_sleep(uart);

	return n;
}

DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
#else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
#define DEV_CREATE_FILE(dev, attr)
#endif /* CONFIG_PM */

static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
	{
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM,
			.dev			= {
				.platform_data	= serial_platform_data0,
			},
		},
	}, {
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM1,
			.dev			= {
				.platform_data	= serial_platform_data1,
			},
		},
	}, {
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM2,
			.dev			= {
				.platform_data	= serial_platform_data2,
			},
		},
	},
};

void __init omap_serial_init(void)
{
	int i;
	char name[16];

	/*
	 * Make sure the serial ports are muxed on at this point.
	 * You have to mux them off in device drivers later on
	 * if not needed.
	 */

	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
		struct omap_uart_state *uart = &omap_uart[i];
		struct platform_device *pdev = &uart->pdev;
		struct device *dev = &pdev->dev;
		struct plat_serial8250_port *p = dev->platform_data;

		sprintf(name, "uart%d_ick", i+1);
		uart->ick = clk_get(NULL, name);
		if (IS_ERR(uart->ick)) {
			printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
			uart->ick = NULL;
		}

		sprintf(name, "uart%d_fck", i+1);
		uart->fck = clk_get(NULL, name);
		if (IS_ERR(uart->fck)) {
			printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
			uart->fck = NULL;
		}

		if (!uart->ick || !uart->fck)
			continue;

		uart->num = i;
		p->private_data = uart;
		uart->p = p;
		list_add_tail(&uart->node, &uart_list);

		if (cpu_is_omap44xx())
			p->irq += 32;

		omap_uart_enable_clocks(uart);
		omap_uart_reset(uart);
		omap_uart_idle_init(uart);

		if (WARN_ON(platform_device_register(pdev)))
			continue;
		if ((cpu_is_omap34xx() && uart->padconf) ||
		    (uart->wk_en && uart->wk_mask)) {
			device_init_wakeup(dev, true);
			DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
		}
	}
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* arch/arm/mach-omap2/serial.c
1dbae815 TL	3	*
	4	* OMAP2 serial support.
	5	*
6e81176d	6	* Copyright (C) 2005-2008 Nokia Corporation
1dbae815 TL	7	* Author: Paul Mundt <paul.mundt@nokia.com>
1dbae815 TL	8	*
4af4016c KH	9	* Major rework for PM support by Kevin Hilman
4af4016c KH	10	*
1dbae815 TL	11	* Based off of arch/arm/mach-omap/omap1/serial.c
1dbae815 TL	12	*
44169075 SS	13	* Copyright (C) 2009 Texas Instruments
	14	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
	15	*
1dbae815 TL	16	* This file is subject to the terms and conditions of the GNU General Public
	17	* License. See the file "COPYING" in the main directory of this archive
	18	* for more details.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/serial_8250.h>
	23	#include <linux/serial_reg.h>
f8ce2547	24	#include <linux/clk.h>
fced80c7	25	#include <linux/io.h>
1dbae815	26
a09e64fb RK	27	#include <mach/common.h>
a09e64fb RK	28	#include <mach/board.h>
4af4016c KH	29	#include <mach/clock.h>
	30	#include <mach/control.h>
	31
	32	#include "prm.h"
	33	#include "pm.h"
	34	#include "prm-regbits-34xx.h"
	35
	36	#define UART_OMAP_WER 0x17 /* Wake-up enable register */
	37
ba87a9be	38	#define DEFAULT_TIMEOUT (5 * HZ)
4af4016c KH	39
	40	struct omap_uart_state {
	41	int num;
	42	int can_sleep;
	43	struct timer_list timer;
	44	u32 timeout;
	45
	46	void __iomem *wk_st;
	47	void __iomem *wk_en;
	48	u32 wk_mask;
	49	u32 padconf;
	50
	51	struct clk *ick;
	52	struct clk *fck;
	53	int clocked;
	54
	55	struct plat_serial8250_port *p;
	56	struct list_head node;
fd455ea8	57	struct platform_device pdev;
1dbae815	58
4af4016c KH	59	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	60	int context_valid;
	61
	62	/* Registers to be saved/restored for OFF-mode */
	63	u16 dll;
	64	u16 dlh;
	65	u16 ier;
	66	u16 sysc;
	67	u16 scr;
	68	u16 wer;
	69	#endif
	70	};
	71
4af4016c	72	static LIST_HEAD(uart_list);
1dbae815	73
fd455ea8	74	static struct plat_serial8250_port serial_platform_data0[] = {
1dbae815	75	{
94113260	76	.membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
e8a91c95	77	.mapbase = OMAP_UART1_BASE,
1dbae815 TL	78	.irq = 72,
	79	.flags = UPF_BOOT_AUTOCONF,
	80	.iotype = UPIO_MEM,
	81	.regshift = 2,
6e81176d	82	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815	83	}, {
fd455ea8 KH	84	.flags = 0
	85	}
	86	};
	87
	88	static struct plat_serial8250_port serial_platform_data1[] = {
	89	{
94113260	90	.membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
e8a91c95	91	.mapbase = OMAP_UART2_BASE,
1dbae815 TL	92	.irq = 73,
	93	.flags = UPF_BOOT_AUTOCONF,
	94	.iotype = UPIO_MEM,
	95	.regshift = 2,
6e81176d	96	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815	97	}, {
fd455ea8 KH	98	.flags = 0
	99	}
	100	};
	101
	102	static struct plat_serial8250_port serial_platform_data2[] = {
	103	{
94113260	104	.membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
e8a91c95	105	.mapbase = OMAP_UART3_BASE,
1dbae815 TL	106	.irq = 74,
	107	.flags = UPF_BOOT_AUTOCONF,
	108	.iotype = UPIO_MEM,
	109	.regshift = 2,
6e81176d	110	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 TL	111	}, {
	112	.flags = 0
	113	}
	114	};
	115
	116	static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
	117	int offset)
	118	{
	119	offset <<= up->regshift;
	120	return (unsigned int)__raw_readb(up->membase + offset);
	121	}
	122
	123	static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
	124	int value)
	125	{
	126	offset <<= p->regshift;
e8a91c95	127	__raw_writeb(value, p->membase + offset);
1dbae815 TL	128	}
	129
	130	/*
	131	* Internal UARTs need to be initialized for the 8250 autoconfig to work
	132	* properly. Note that the TX watermark initialization may not be needed
	133	* once the 8250.c watermark handling code is merged.
	134	*/
4af4016c	135	static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815	136	{
4af4016c KH	137	struct plat_serial8250_port *p = uart->p;
4af4016c KH	138
1dbae815 TL	139	serial_write_reg(p, UART_OMAP_MDR1, 0x07);
	140	serial_write_reg(p, UART_OMAP_SCR, 0x08);
	141	serial_write_reg(p, UART_OMAP_MDR1, 0x00);
671c7235	142	serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) \| (1 << 2) \| (1 << 0));
1dbae815 TL	143	}
1dbae815 TL	144
4af4016c KH	145	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
	146
	147	static int enable_off_mode; /* to be removed by full off-mode patches */
	148
	149	static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d	150	{
4af4016c KH	151	u16 lcr = 0;
	152	struct plat_serial8250_port *p = uart->p;
	153
	154	if (!enable_off_mode)
	155	return;
	156
	157	lcr = serial_read_reg(p, UART_LCR);
	158	serial_write_reg(p, UART_LCR, 0xBF);
	159	uart->dll = serial_read_reg(p, UART_DLL);
	160	uart->dlh = serial_read_reg(p, UART_DLM);
	161	serial_write_reg(p, UART_LCR, lcr);
	162	uart->ier = serial_read_reg(p, UART_IER);
	163	uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
	164	uart->scr = serial_read_reg(p, UART_OMAP_SCR);
	165	uart->wer = serial_read_reg(p, UART_OMAP_WER);
	166
	167	uart->context_valid = 1;
	168	}
	169
	170	static void omap_uart_restore_context(struct omap_uart_state *uart)
	171	{
	172	u16 efr = 0;
	173	struct plat_serial8250_port *p = uart->p;
	174
	175	if (!enable_off_mode)
	176	return;
	177
	178	if (!uart->context_valid)
	179	return;
	180
	181	uart->context_valid = 0;
	182
	183	serial_write_reg(p, UART_OMAP_MDR1, 0x7);
	184	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	185	efr = serial_read_reg(p, UART_EFR);
	186	serial_write_reg(p, UART_EFR, UART_EFR_ECB);
	187	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	188	serial_write_reg(p, UART_IER, 0x0);
	189	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	190	serial_write_reg(p, UART_DLL, uart->dll);
	191	serial_write_reg(p, UART_DLM, uart->dlh);
	192	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	193	serial_write_reg(p, UART_IER, uart->ier);
	194	serial_write_reg(p, UART_FCR, 0xA1);
	195	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	196	serial_write_reg(p, UART_EFR, efr);
	197	serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
	198	serial_write_reg(p, UART_OMAP_SCR, uart->scr);
	199	serial_write_reg(p, UART_OMAP_WER, uart->wer);
	200	serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
	201	serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
	202	}
	203	#else
	204	static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
	205	static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
	206	#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
	207
	208	static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
	209	{
	210	if (uart->clocked)
	211	return;
	212
	213	clk_enable(uart->ick);
	214	clk_enable(uart->fck);
215	uart->clocked = 1;
216	omap_uart_restore_context(uart);
217	}
218
219	#ifdef CONFIG_PM
220
221	static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
222	{
223	if (!uart->clocked)
224	return;
225
226	omap_uart_save_context(uart);
227	uart->clocked = 0;
228	clk_disable(uart->ick);
229	clk_disable(uart->fck);
230	}
231
fd455ea8 KH	232	static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
	233	{
	234	/* Set wake-enable bit */
	235	if (uart->wk_en && uart->wk_mask) {
	236	u32 v = __raw_readl(uart->wk_en);
	237	v \|= uart->wk_mask;
	238	__raw_writel(v, uart->wk_en);
	239	}
	240
	241	/* Ensure IOPAD wake-enables are set */
	242	if (cpu_is_omap34xx() && uart->padconf) {
	243	u16 v = omap_ctrl_readw(uart->padconf);
	244	v \|= OMAP3_PADCONF_WAKEUPENABLE0;
	245	omap_ctrl_writew(v, uart->padconf);
	246	}
	247	}
	248
	249	static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
	250	{
	251	/* Clear wake-enable bit */
	252	if (uart->wk_en && uart->wk_mask) {
	253	u32 v = __raw_readl(uart->wk_en);
	254	v &= ~uart->wk_mask;
	255	__raw_writel(v, uart->wk_en);
	256	}
	257
	258	/* Ensure IOPAD wake-enables are cleared */
	259	if (cpu_is_omap34xx() && uart->padconf) {
	260	u16 v = omap_ctrl_readw(uart->padconf);
	261	v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
	262	omap_ctrl_writew(v, uart->padconf);
	263	}
	264	}
	265
4af4016c KH	266	static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
	267	int enable)
	268	{
	269	struct plat_serial8250_port *p = uart->p;
	270	u16 sysc;
	271
	272	sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
	273	if (enable)
	274	sysc \|= 0x2 << 3;
	275	else
	276	sysc \|= 0x1 << 3;
	277
	278	serial_write_reg(p, UART_OMAP_SYSC, sysc);
	279	}
	280
	281	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	282	{
	283	omap_uart_enable_clocks(uart);
	284
	285	omap_uart_smart_idle_enable(uart, 0);
	286	uart->can_sleep = 0;
ba87a9be JH	287	if (uart->timeout)
	288	mod_timer(&uart->timer, jiffies + uart->timeout);
	289	else
	290	del_timer(&uart->timer);
4af4016c KH	291	}
	292
	293	static void omap_uart_allow_sleep(struct omap_uart_state *uart)
	294	{
fd455ea8 KH	295	if (device_may_wakeup(&uart->pdev.dev))
	296	omap_uart_enable_wakeup(uart);
	297	else
	298	omap_uart_disable_wakeup(uart);
	299
4af4016c KH	300	if (!uart->clocked)
	301	return;
	302
	303	omap_uart_smart_idle_enable(uart, 1);
	304	uart->can_sleep = 1;
	305	del_timer(&uart->timer);
	306	}
	307
	308	static void omap_uart_idle_timer(unsigned long data)
	309	{
	310	struct omap_uart_state uart = (struct omap_uart_state )data;
	311
	312	omap_uart_allow_sleep(uart);
	313	}
	314
	315	void omap_uart_prepare_idle(int num)
	316	{
	317	struct omap_uart_state *uart;
	318
	319	list_for_each_entry(uart, &uart_list, node) {
	320	if (num == uart->num && uart->can_sleep) {
	321	omap_uart_disable_clocks(uart);
	322	return;
	323	}
	324	}
	325	}
	326
	327	void omap_uart_resume_idle(int num)
	328	{
	329	struct omap_uart_state *uart;
	330
	331	list_for_each_entry(uart, &uart_list, node) {
	332	if (num == uart->num) {
	333	omap_uart_enable_clocks(uart);
	334
	335	/* Check for IO pad wakeup */
	336	if (cpu_is_omap34xx() && uart->padconf) {
	337	u16 p = omap_ctrl_readw(uart->padconf);
	338
	339	if (p & OMAP3_PADCONF_WAKEUPEVENT0)
	340	omap_uart_block_sleep(uart);
6e81176d	341	}
4af4016c KH	342
	343	/* Check for normal UART wakeup */
	344	if (__raw_readl(uart->wk_st) & uart->wk_mask)
	345	omap_uart_block_sleep(uart);
4af4016c KH	346	return;
	347	}
	348	}
	349	}
	350
	351	void omap_uart_prepare_suspend(void)
	352	{
	353	struct omap_uart_state *uart;
	354
	355	list_for_each_entry(uart, &uart_list, node) {
	356	omap_uart_allow_sleep(uart);
	357	}
	358	}
	359
	360	int omap_uart_can_sleep(void)
	361	{
	362	struct omap_uart_state *uart;
	363	int can_sleep = 1;
	364
	365	list_for_each_entry(uart, &uart_list, node) {
	366	if (!uart->clocked)
	367	continue;
	368
	369	if (!uart->can_sleep) {
	370	can_sleep = 0;
	371	continue;
6e81176d	372	}
4af4016c KH	373
	374	/* This UART can now safely sleep. */
	375	omap_uart_allow_sleep(uart);
6e81176d	376	}
4af4016c KH	377
4af4016c KH	378	return can_sleep;
6e81176d JH	379	}
6e81176d JH	380
4af4016c KH	381	/**
	382	* omap_uart_interrupt()
	383	*
	384	* This handler is used only to detect that any UART interrupt has
	385	* occurred. It does _nothing_ to handle the interrupt. Rather,
	386	* any UART interrupt will trigger the inactivity timer so the
	387	* UART will not idle or sleep for its timeout period.
	388	*
	389	**/
	390	static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
	391	{
	392	struct omap_uart_state *uart = dev_id;
	393
	394	omap_uart_block_sleep(uart);
	395
	396	return IRQ_NONE;
	397	}
	398
	399	static void omap_uart_idle_init(struct omap_uart_state *uart)
	400	{
4af4016c KH	401	struct plat_serial8250_port *p = uart->p;
	402	int ret;
	403
	404	uart->can_sleep = 0;
fd455ea8	405	uart->timeout = DEFAULT_TIMEOUT;
4af4016c KH	406	setup_timer(&uart->timer, omap_uart_idle_timer,
	407	(unsigned long) uart);
	408	mod_timer(&uart->timer, jiffies + uart->timeout);
	409	omap_uart_smart_idle_enable(uart, 0);
	410
	411	if (cpu_is_omap34xx()) {
	412	u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
	413	u32 wk_mask = 0;
	414	u32 padconf = 0;
	415
	416	uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
	417	uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
	418	switch (uart->num) {
	419	case 0:
	420	wk_mask = OMAP3430_ST_UART1_MASK;
	421	padconf = 0x182;
	422	break;
	423	case 1:
	424	wk_mask = OMAP3430_ST_UART2_MASK;
	425	padconf = 0x17a;
	426	break;
	427	case 2:
	428	wk_mask = OMAP3430_ST_UART3_MASK;
	429	padconf = 0x19e;
	430	break;
	431	}
	432	uart->wk_mask = wk_mask;
	433	uart->padconf = padconf;
	434	} else if (cpu_is_omap24xx()) {
	435	u32 wk_mask = 0;
	436
	437	if (cpu_is_omap2430()) {
	438	uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
	439	uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
	440	} else if (cpu_is_omap2420()) {
	441	uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
	442	uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
	443	}
	444	switch (uart->num) {
	445	case 0:
	446	wk_mask = OMAP24XX_ST_UART1_MASK;
	447	break;
	448	case 1:
	449	wk_mask = OMAP24XX_ST_UART2_MASK;
	450	break;
	451	case 2:
	452	wk_mask = OMAP24XX_ST_UART3_MASK;
	453	break;
	454	}
	455	uart->wk_mask = wk_mask;
	456	} else {
	457	uart->wk_en = 0;
	458	uart->wk_st = 0;
	459	uart->wk_mask = 0;
	460	uart->padconf = 0;
	461	}
	462
4af4016c KH	463	p->flags \|= UPF_SHARE_IRQ;
	464	ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
	465	"serial idle", (void *)uart);
	466	WARN_ON(ret);
	467	}
	468
2466211e TK	469	void omap_uart_enable_irqs(int enable)
	470	{
	471	int ret;
	472	struct omap_uart_state *uart;
	473
	474	list_for_each_entry(uart, &uart_list, node) {
	475	if (enable)
	476	ret = request_irq(uart->p->irq, omap_uart_interrupt,
	477	IRQF_SHARED, "serial idle", (void *)uart);
	478	else
	479	free_irq(uart->p->irq, (void *)uart);
	480	}
	481	}
	482
fd455ea8 KH	483	static ssize_t sleep_timeout_show(struct device *dev,
fd455ea8 KH	484	struct device_attribute *attr,
ba87a9be JH	485	char *buf)
ba87a9be JH	486	{
fd455ea8 KH	487	struct platform_device *pdev = container_of(dev,
	488	struct platform_device, dev);
	489	struct omap_uart_state *uart = container_of(pdev,
	490	struct omap_uart_state, pdev);
	491
	492	return sprintf(buf, "%u\n", uart->timeout / HZ);
ba87a9be JH	493	}
ba87a9be JH	494
fd455ea8 KH	495	static ssize_t sleep_timeout_store(struct device *dev,
fd455ea8 KH	496	struct device_attribute *attr,
ba87a9be JH	497	const char *buf, size_t n)
ba87a9be JH	498	{
fd455ea8 KH	499	struct platform_device *pdev = container_of(dev,
	500	struct platform_device, dev);
	501	struct omap_uart_state *uart = container_of(pdev,
	502	struct omap_uart_state, pdev);
ba87a9be JH	503	unsigned int value;
	504
	505	if (sscanf(buf, "%u", &value) != 1) {
	506	printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
	507	return -EINVAL;
	508	}
fd455ea8 KH	509
	510	uart->timeout = value * HZ;
	511	if (uart->timeout)
	512	mod_timer(&uart->timer, jiffies + uart->timeout);
	513	else
	514	/* A zero value means disable timeout feature */
	515	omap_uart_block_sleep(uart);
	516
ba87a9be JH	517	return n;
	518	}
	519
fd455ea8 KH	520	DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
fd455ea8 KH	521	#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
4af4016c KH	522	#else
4af4016c KH	523	static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
fd455ea8	524	#define DEV_CREATE_FILE(dev, attr)
4af4016c KH	525	#endif /* CONFIG_PM */
4af4016c KH	526
fd455ea8 KH	527	static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
	528	{
	529	.pdev = {
	530	.name = "serial8250",
	531	.id = PLAT8250_DEV_PLATFORM,
	532	.dev = {
	533	.platform_data = serial_platform_data0,
	534	},
	535	},
	536	}, {
	537	.pdev = {
	538	.name = "serial8250",
	539	.id = PLAT8250_DEV_PLATFORM1,
	540	.dev = {
	541	.platform_data = serial_platform_data1,
	542	},
	543	},
	544	}, {
	545	.pdev = {
	546	.name = "serial8250",
	547	.id = PLAT8250_DEV_PLATFORM2,
	548	.dev = {
	549	.platform_data = serial_platform_data2,
	550	},
	551	},
2aa57be2 VP	552	},
	553	};
	554
6e81176d	555	void __init omap_serial_init(void)
1dbae815	556	{
fd455ea8	557	int i;
6e81176d	558	char name[16];
1dbae815 TL	559
	560	/*
	561	* Make sure the serial ports are muxed on at this point.
	562	* You have to mux them off in device drivers later on
	563	* if not needed.
	564	*/
	565
1dbae815	566	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
4af4016c	567	struct omap_uart_state *uart = &omap_uart[i];
fd455ea8 KH	568	struct platform_device *pdev = &uart->pdev;
	569	struct device *dev = &pdev->dev;
	570	struct plat_serial8250_port *p = dev->platform_data;
1dbae815	571
6e81176d	572	sprintf(name, "uart%d_ick", i+1);
4af4016c KH	573	uart->ick = clk_get(NULL, name);
4af4016c KH	574	if (IS_ERR(uart->ick)) {
6e81176d	575	printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
4af4016c KH	576	uart->ick = NULL;
4af4016c KH	577	}
6e81176d JH	578
6e81176d JH	579	sprintf(name, "uart%d_fck", i+1);
4af4016c KH	580	uart->fck = clk_get(NULL, name);
4af4016c KH	581	if (IS_ERR(uart->fck)) {
6e81176d	582	printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
4af4016c KH	583	uart->fck = NULL;
	584	}
	585
	586	if (!uart->ick \|\| !uart->fck)
	587	continue;
	588
	589	uart->num = i;
	590	p->private_data = uart;
	591	uart->p = p;
bcf396c4	592	list_add_tail(&uart->node, &uart_list);
1dbae815	593
4789998a KH	594	if (cpu_is_omap44xx())
	595	p->irq += 32;
	596
4af4016c KH	597	omap_uart_enable_clocks(uart);
	598	omap_uart_reset(uart);
	599	omap_uart_idle_init(uart);
970a724d	600
fd455ea8 KH	601	if (WARN_ON(platform_device_register(pdev)))
	602	continue;
	603	if ((cpu_is_omap34xx() && uart->padconf) \|\|
	604	(uart->wk_en && uart->wk_mask)) {
	605	device_init_wakeup(dev, true);
	606	DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
	607	}
	608	}
1dbae815	609	}