[linux-2.6-block.git] / arch / arm / mach-omap2 / sdrc2xxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SDRAM timing related functions for OMAP2xxx
 *
 * Copyright (C) 2005, 2008 Texas Instruments Inc.
 * Copyright (C) 2005, 2008 Nokia Corporation
 *
 * Tony Lindgren <tony@atomide.com>
 * Paul Walmsley
 * Richard Woodruff <r-woodruff2@ti.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prm2xxx.h"
#include "clock.h"
#include "sdrc.h"
#include "sram.h"

/* Memory timing, DLL mode flags */
#define M_DDR		1
#define M_LOCK_CTRL	(1 << 2)
#define M_UNLOCK	0
#define M_LOCK		1


static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
{
	return mem_timings.slow_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
{
	return mem_timings.fast_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_type(void)
{
	return mem_timings.m_type;
}

/*
 * Check the DLL lock state, and return tue if running in unlock mode.
 * This is needed to compensate for the shifted DLL value in unlock mode.
 */
u32 omap2xxx_sdrc_dll_is_unlocked(void)
{
	/* dlla and dllb are a set */
	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);

	if ((dll_state & (1 << 2)) == (1 << 2))
		return 1;
	else
		return 0;
}

/*
 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
 *
 * Used by the clock framework during CORE DPLL changes
 */
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
{
	u32 dll_ctrl, m_type;
	u32 prev = curr_perf_level;
	unsigned long flags;

	if ((curr_perf_level == level) && !force)
		return prev;

	if (level == CORE_CLK_SRC_DPLL)
		dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
	else if (level == CORE_CLK_SRC_DPLL_X2)
		dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
	else
		return prev;

	m_type = omap2xxx_sdrc_get_type();

	local_irq_save(flags);
	/*
	 * XXX These calls should be abstracted out through a
	 * prm2xxx.c function
	 */
	if (cpu_is_omap2420())
		writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
	else
		writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	curr_perf_level = level;
	local_irq_restore(flags);

	return prev;
}

/* Used by the clock framework during CORE DPLL changes */
void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
{
	unsigned long dll_cnt;
	u32 fast_dll = 0;

	/* DDR = 1, SDR = 0 */
	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);

	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	 * In the case of 2422, its ok to use CS1 instead of CS0.
	 */
	if (cpu_is_omap2422())
		mem_timings.base_cs = 1;
	else
		mem_timings.base_cs = 0;

	if (mem_timings.m_type != M_DDR)
		return;

	/* With DDR we need to determine the low frequency DLL value */
	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
		mem_timings.dll_mode = M_UNLOCK;
	else
		mem_timings.dll_mode = M_LOCK;

	if (mem_timings.base_cs == 0) {
		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
	} else {
		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
	}
	if (force_lock_to_unlock_mode) {
		fast_dll &= ~0xff00;
		fast_dll |= dll_cnt;		/* Current lock mode */
	}
	/* set fast timings with DLL filter disabled */
	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));

	/* No disruptions, DDR will be offline & C-ABI not followed */
	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
			    mem_timings.fast_dll_ctrl,
			    mem_timings.base_cs,
			    force_lock_to_unlock_mode);
	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */

	/* Turn status into unlock ctrl */
	mem_timings.slow_dll_ctrl |=
		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));

	/* 90 degree phase for anything below 133MHz + disable DLL filter */
	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
b824efae	2	/*
96609ef4	3	* SDRAM timing related functions for OMAP2xxx
b824efae	4	*
f2ab9977 PW	5	* Copyright (C) 2005, 2008 Texas Instruments Inc.
f2ab9977 PW	6	* Copyright (C) 2005, 2008 Nokia Corporation
b824efae	7	*
b824efae	8	* Tony Lindgren <tony@atomide.com>
f2ab9977 PW	9	* Paul Walmsley
f2ab9977 PW	10	* Richard Woodruff <r-woodruff2@ti.com>
b824efae TL	11	*/
b824efae TL	12
b824efae TL	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/device.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/delay.h>
	19	#include <linux/clk.h>
fced80c7	20	#include <linux/io.h>
b824efae	21
dbc04161	22	#include "soc.h"
ee0839c2 TL	23	#include "iomap.h"
ee0839c2 TL	24	#include "common.h"
139563ad	25	#include "prm2xxx.h"
c0bf3132	26	#include "clock.h"
44595982	27	#include "sdrc.h"
bf027ca1	28	#include "sram.h"
b824efae	29
f8de9b2c PW	30	/* Memory timing, DLL mode flags */
	31	#define M_DDR 1
	32	#define M_LOCK_CTRL (1 << 2)
	33	#define M_UNLOCK 0
	34	#define M_LOCK 1
	35
	36
b824efae	37	static struct memory_timings mem_timings;
44595982	38	static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
b824efae	39
f2ab9977	40	static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
b824efae TL	41	{
	42	return mem_timings.slow_dll_ctrl;
	43	}
	44
f2ab9977	45	static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
b824efae TL	46	{
	47	return mem_timings.fast_dll_ctrl;
	48	}
	49
f2ab9977	50	static u32 omap2xxx_sdrc_get_type(void)
b824efae TL	51	{
	52	return mem_timings.m_type;
	53	}
	54
6b8858a9 PW	55	/*
	56	* Check the DLL lock state, and return tue if running in unlock mode.
	57	* This is needed to compensate for the shifted DLL value in unlock mode.
	58	*/
f2ab9977	59	u32 omap2xxx_sdrc_dll_is_unlocked(void)
6b8858a9 PW	60	{
	61	/* dlla and dllb are a set */
	62	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
	63
	64	if ((dll_state & (1 << 2)) == (1 << 2))
	65	return 1;
	66	else
	67	return 0;
	68	}
	69
	70	/*
	71	* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
	72	* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
	73	* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
f2ab9977 PW	74	*
f2ab9977 PW	75	* Used by the clock framework during CORE DPLL changes
6b8858a9	76	*/
f2ab9977	77	u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
6b8858a9 PW	78	{
	79	u32 dll_ctrl, m_type;
	80	u32 prev = curr_perf_level;
	81	unsigned long flags;
	82
	83	if ((curr_perf_level == level) && !force)
	84	return prev;
	85
96609ef4	86	if (level == CORE_CLK_SRC_DPLL)
f2ab9977	87	dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
96609ef4	88	else if (level == CORE_CLK_SRC_DPLL_X2)
f2ab9977	89	dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
96609ef4	90	else
6b8858a9	91	return prev;
6b8858a9	92
f2ab9977	93	m_type = omap2xxx_sdrc_get_type();
6b8858a9 PW	94
6b8858a9 PW	95	local_irq_save(flags);
c4d7e58f PW	96	/*
	97	* XXX These calls should be abstracted out through a
	98	* prm2xxx.c function
	99	*/
8e3bd351	100	if (cpu_is_omap2420())
edfaf05c	101	writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
8e3bd351	102	else
edfaf05c	103	writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
6b8858a9 PW	104	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	105	curr_perf_level = level;
	106	local_irq_restore(flags);
	107
	108	return prev;
	109	}
	110
f2ab9977 PW	111	/* Used by the clock framework during CORE DPLL changes */
f2ab9977 PW	112	void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
b824efae TL	113	{
	114	unsigned long dll_cnt;
	115	u32 fast_dll = 0;
	116
96609ef4 PW	117	/* DDR = 1, SDR = 0 */
96609ef4 PW	118	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
b824efae TL	119
	120	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	121	* In the case of 2422, its ok to use CS1 instead of CS0.
	122	*/
	123	if (cpu_is_omap2422())
	124	mem_timings.base_cs = 1;
	125	else
	126	mem_timings.base_cs = 0;
	127
	128	if (mem_timings.m_type != M_DDR)
	129	return;
	130
	131	/* With DDR we need to determine the low frequency DLL value */
	132	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
	133	mem_timings.dll_mode = M_UNLOCK;
	134	else
	135	mem_timings.dll_mode = M_LOCK;
	136
	137	if (mem_timings.base_cs == 0) {
44595982 PW	138	fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
44595982 PW	139	dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
b824efae	140	} else {
44595982 PW	141	fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
44595982 PW	142	dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
b824efae TL	143	}
	144	if (force_lock_to_unlock_mode) {
	145	fast_dll &= ~0xff00;
	146	fast_dll \|= dll_cnt; /* Current lock mode */
	147	}
	148	/* set fast timings with DLL filter disabled */
	149	mem_timings.fast_dll_ctrl = (fast_dll \| (3 << 8));
	150
	151	/* No disruptions, DDR will be offline & C-ABI not followed */
	152	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
	153	mem_timings.fast_dll_ctrl,
	154	mem_timings.base_cs,
	155	force_lock_to_unlock_mode);
	156	mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
	157
	158	/* Turn status into unlock ctrl */
	159	mem_timings.slow_dll_ctrl \|=
	160	((mem_timings.fast_dll_ctrl & 0xF) \| (1 << 2));
	161
6a53bc75	162	/* 90 degree phase for anything below 133MHz + disable DLL filter */
b824efae TL	163	mem_timings.slow_dll_ctrl \|= ((1 << 1) \| (3 << 8));
b824efae TL	164	}