Commit | Line | Data |
---|---|---|
b824efae | 1 | /* |
96609ef4 | 2 | * linux/arch/arm/mach-omap2/sdrc2xxx.c |
b824efae | 3 | * |
96609ef4 | 4 | * SDRAM timing related functions for OMAP2xxx |
b824efae TL |
5 | * |
6 | * Copyright (C) 2005 Texas Instruments Inc. | |
7 | * Richard Woodruff <r-woodruff2@ti.com> | |
8 | * | |
9 | * Copyright (C) 2005 Nokia Corporation | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
b824efae TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
fced80c7 | 24 | #include <linux/io.h> |
b824efae | 25 | |
a09e64fb RK |
26 | #include <mach/common.h> |
27 | #include <mach/clock.h> | |
28 | #include <mach/sram.h> | |
b824efae | 29 | |
44595982 PW |
30 | #include "prm.h" |
31 | ||
f8de9b2c | 32 | #include <mach/sdrc.h> |
44595982 | 33 | #include "sdrc.h" |
b824efae | 34 | |
f8de9b2c PW |
35 | /* Memory timing, DLL mode flags */ |
36 | #define M_DDR 1 | |
37 | #define M_LOCK_CTRL (1 << 2) | |
38 | #define M_UNLOCK 0 | |
39 | #define M_LOCK 1 | |
40 | ||
41 | ||
a58caad1 TL |
42 | void __iomem *omap2_sdrc_base; |
43 | void __iomem *omap2_sms_base; | |
33c99075 | 44 | |
b824efae | 45 | static struct memory_timings mem_timings; |
44595982 | 46 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; |
b824efae TL |
47 | |
48 | u32 omap2_memory_get_slow_dll_ctrl(void) | |
49 | { | |
50 | return mem_timings.slow_dll_ctrl; | |
51 | } | |
52 | ||
53 | u32 omap2_memory_get_fast_dll_ctrl(void) | |
54 | { | |
55 | return mem_timings.fast_dll_ctrl; | |
56 | } | |
57 | ||
58 | u32 omap2_memory_get_type(void) | |
59 | { | |
60 | return mem_timings.m_type; | |
61 | } | |
62 | ||
6b8858a9 PW |
63 | /* |
64 | * Check the DLL lock state, and return tue if running in unlock mode. | |
65 | * This is needed to compensate for the shifted DLL value in unlock mode. | |
66 | */ | |
67 | u32 omap2_dll_force_needed(void) | |
68 | { | |
69 | /* dlla and dllb are a set */ | |
70 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); | |
71 | ||
72 | if ((dll_state & (1 << 2)) == (1 << 2)) | |
73 | return 1; | |
74 | else | |
75 | return 0; | |
76 | } | |
77 | ||
78 | /* | |
79 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. | |
80 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or | |
81 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) | |
82 | */ | |
83 | u32 omap2_reprogram_sdrc(u32 level, u32 force) | |
84 | { | |
85 | u32 dll_ctrl, m_type; | |
86 | u32 prev = curr_perf_level; | |
87 | unsigned long flags; | |
88 | ||
89 | if ((curr_perf_level == level) && !force) | |
90 | return prev; | |
91 | ||
96609ef4 | 92 | if (level == CORE_CLK_SRC_DPLL) |
6b8858a9 | 93 | dll_ctrl = omap2_memory_get_slow_dll_ctrl(); |
96609ef4 | 94 | else if (level == CORE_CLK_SRC_DPLL_X2) |
6b8858a9 | 95 | dll_ctrl = omap2_memory_get_fast_dll_ctrl(); |
96609ef4 | 96 | else |
6b8858a9 | 97 | return prev; |
6b8858a9 PW |
98 | |
99 | m_type = omap2_memory_get_type(); | |
100 | ||
101 | local_irq_save(flags); | |
102 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); | |
103 | omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); | |
104 | curr_perf_level = level; | |
105 | local_irq_restore(flags); | |
106 | ||
107 | return prev; | |
108 | } | |
109 | ||
cc26b3b0 SMK |
110 | #if !defined(CONFIG_ARCH_OMAP2) |
111 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |
112 | u32 base_cs, u32 force_unlock) | |
113 | { | |
114 | } | |
115 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | |
116 | u32 mem_type) | |
117 | { | |
118 | } | |
119 | #endif | |
120 | ||
b824efae TL |
121 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) |
122 | { | |
123 | unsigned long dll_cnt; | |
124 | u32 fast_dll = 0; | |
125 | ||
96609ef4 PW |
126 | /* DDR = 1, SDR = 0 */ |
127 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); | |
b824efae TL |
128 | |
129 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. | |
130 | * In the case of 2422, its ok to use CS1 instead of CS0. | |
131 | */ | |
132 | if (cpu_is_omap2422()) | |
133 | mem_timings.base_cs = 1; | |
134 | else | |
135 | mem_timings.base_cs = 0; | |
136 | ||
137 | if (mem_timings.m_type != M_DDR) | |
138 | return; | |
139 | ||
140 | /* With DDR we need to determine the low frequency DLL value */ | |
141 | if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) | |
142 | mem_timings.dll_mode = M_UNLOCK; | |
143 | else | |
144 | mem_timings.dll_mode = M_LOCK; | |
145 | ||
146 | if (mem_timings.base_cs == 0) { | |
44595982 PW |
147 | fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); |
148 | dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; | |
b824efae | 149 | } else { |
44595982 PW |
150 | fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); |
151 | dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; | |
b824efae TL |
152 | } |
153 | if (force_lock_to_unlock_mode) { | |
154 | fast_dll &= ~0xff00; | |
155 | fast_dll |= dll_cnt; /* Current lock mode */ | |
156 | } | |
157 | /* set fast timings with DLL filter disabled */ | |
158 | mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); | |
159 | ||
160 | /* No disruptions, DDR will be offline & C-ABI not followed */ | |
161 | omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, | |
162 | mem_timings.fast_dll_ctrl, | |
163 | mem_timings.base_cs, | |
164 | force_lock_to_unlock_mode); | |
165 | mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ | |
166 | ||
167 | /* Turn status into unlock ctrl */ | |
168 | mem_timings.slow_dll_ctrl |= | |
169 | ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); | |
170 | ||
171 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ | |
172 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); | |
173 | } | |
33c99075 | 174 | |
a58caad1 TL |
175 | void __init omap2_set_globals_memory(struct omap_globals *omap2_globals) |
176 | { | |
177 | omap2_sdrc_base = omap2_globals->sdrc; | |
178 | omap2_sms_base = omap2_globals->sms; | |
179 | } | |
180 | ||
742c53e4 | 181 | /* turn on smart idle modes for SDRAM scheduler and controller */ |
33c99075 JY |
182 | void __init omap2_init_memory(void) |
183 | { | |
184 | u32 l; | |
185 | ||
cc26b3b0 SMK |
186 | if (!cpu_is_omap2420()) |
187 | return; | |
188 | ||
44595982 | 189 | l = sms_read_reg(SMS_SYSCONFIG); |
33c99075 JY |
190 | l &= ~(0x3 << 3); |
191 | l |= (0x2 << 3); | |
44595982 | 192 | sms_write_reg(l, SMS_SYSCONFIG); |
33c99075 | 193 | |
44595982 | 194 | l = sdrc_read_reg(SDRC_SYSCONFIG); |
33c99075 JY |
195 | l &= ~(0x3 << 3); |
196 | l |= (0x2 << 3); | |
44595982 | 197 | sdrc_write_reg(l, SDRC_SYSCONFIG); |
33c99075 | 198 | } |