[linux-block.git] / arch / arm / mach-omap2 / sdrc2xxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * linux/arch/arm/mach-omap2/sdrc2xxx.c
 *
 * SDRAM timing related functions for OMAP2xxx
 *
 * Copyright (C) 2005, 2008 Texas Instruments Inc.
 * Copyright (C) 2005, 2008 Nokia Corporation
 *
 * Tony Lindgren <tony@atomide.com>
 * Paul Walmsley
 * Richard Woodruff <r-woodruff2@ti.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prm2xxx.h"
#include "clock.h"
#include "sdrc.h"
#include "sram.h"

/* Memory timing, DLL mode flags */
#define M_DDR		1
#define M_LOCK_CTRL	(1 << 2)
#define M_UNLOCK	0
#define M_LOCK		1


static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
{
	return mem_timings.slow_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
{
	return mem_timings.fast_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_type(void)
{
	return mem_timings.m_type;
}

/*
 * Check the DLL lock state, and return tue if running in unlock mode.
 * This is needed to compensate for the shifted DLL value in unlock mode.
 */
u32 omap2xxx_sdrc_dll_is_unlocked(void)
{
	/* dlla and dllb are a set */
	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);

	if ((dll_state & (1 << 2)) == (1 << 2))
		return 1;
	else
		return 0;
}

/*
 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
 *
 * Used by the clock framework during CORE DPLL changes
 */
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
{
	u32 dll_ctrl, m_type;
	u32 prev = curr_perf_level;
	unsigned long flags;

	if ((curr_perf_level == level) && !force)
		return prev;

	if (level == CORE_CLK_SRC_DPLL)
		dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
	else if (level == CORE_CLK_SRC_DPLL_X2)
		dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
	else
		return prev;

	m_type = omap2xxx_sdrc_get_type();

	local_irq_save(flags);
	/*
	 * XXX These calls should be abstracted out through a
	 * prm2xxx.c function
	 */
	if (cpu_is_omap2420())
		writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
	else
		writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	curr_perf_level = level;
	local_irq_restore(flags);

	return prev;
}

/* Used by the clock framework during CORE DPLL changes */
void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
{
	unsigned long dll_cnt;
	u32 fast_dll = 0;

	/* DDR = 1, SDR = 0 */
	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);

	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	 * In the case of 2422, its ok to use CS1 instead of CS0.
	 */
	if (cpu_is_omap2422())
		mem_timings.base_cs = 1;
	else
		mem_timings.base_cs = 0;

	if (mem_timings.m_type != M_DDR)
		return;

	/* With DDR we need to determine the low frequency DLL value */
	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
		mem_timings.dll_mode = M_UNLOCK;
	else
		mem_timings.dll_mode = M_LOCK;

	if (mem_timings.base_cs == 0) {
		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
	} else {
		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
	}
	if (force_lock_to_unlock_mode) {
		fast_dll &= ~0xff00;
		fast_dll |= dll_cnt;		/* Current lock mode */
	}
	/* set fast timings with DLL filter disabled */
	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));

	/* No disruptions, DDR will be offline & C-ABI not followed */
	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
			    mem_timings.fast_dll_ctrl,
			    mem_timings.base_cs,
			    force_lock_to_unlock_mode);
	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */

	/* Turn status into unlock ctrl */
	mem_timings.slow_dll_ctrl |=
		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));

	/* 90 degree phase for anything below 133MHz + disable DLL filter */
	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
b824efae	2	/*
96609ef4	3	* linux/arch/arm/mach-omap2/sdrc2xxx.c
b824efae	4	*
96609ef4	5	* SDRAM timing related functions for OMAP2xxx
b824efae	6	*
f2ab9977 PW	7	* Copyright (C) 2005, 2008 Texas Instruments Inc.
f2ab9977 PW	8	* Copyright (C) 2005, 2008 Nokia Corporation
b824efae	9	*
b824efae	10	* Tony Lindgren <tony@atomide.com>
f2ab9977 PW	11	* Paul Walmsley
f2ab9977 PW	12	* Richard Woodruff <r-woodruff2@ti.com>
b824efae TL	13	*/
b824efae TL	14
b824efae TL	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/device.h>
	18	#include <linux/list.h>
	19	#include <linux/errno.h>
	20	#include <linux/delay.h>
	21	#include <linux/clk.h>
fced80c7	22	#include <linux/io.h>
b824efae	23
dbc04161	24	#include "soc.h"
ee0839c2 TL	25	#include "iomap.h"
ee0839c2 TL	26	#include "common.h"
139563ad	27	#include "prm2xxx.h"
c0bf3132	28	#include "clock.h"
44595982	29	#include "sdrc.h"
bf027ca1	30	#include "sram.h"
b824efae	31
f8de9b2c PW	32	/* Memory timing, DLL mode flags */
	33	#define M_DDR 1
	34	#define M_LOCK_CTRL (1 << 2)
	35	#define M_UNLOCK 0
	36	#define M_LOCK 1
	37
	38
b824efae	39	static struct memory_timings mem_timings;
44595982	40	static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
b824efae	41
f2ab9977	42	static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
b824efae TL	43	{
	44	return mem_timings.slow_dll_ctrl;
	45	}
	46
f2ab9977	47	static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
b824efae TL	48	{
	49	return mem_timings.fast_dll_ctrl;
	50	}
	51
f2ab9977	52	static u32 omap2xxx_sdrc_get_type(void)
b824efae TL	53	{
	54	return mem_timings.m_type;
	55	}
	56
6b8858a9 PW	57	/*
	58	* Check the DLL lock state, and return tue if running in unlock mode.
	59	* This is needed to compensate for the shifted DLL value in unlock mode.
	60	*/
f2ab9977	61	u32 omap2xxx_sdrc_dll_is_unlocked(void)
6b8858a9 PW	62	{
	63	/* dlla and dllb are a set */
	64	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
	65
	66	if ((dll_state & (1 << 2)) == (1 << 2))
	67	return 1;
	68	else
	69	return 0;
	70	}
	71
	72	/*
	73	* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
	74	* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
	75	* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
f2ab9977 PW	76	*
f2ab9977 PW	77	* Used by the clock framework during CORE DPLL changes
6b8858a9	78	*/
f2ab9977	79	u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
6b8858a9 PW	80	{
	81	u32 dll_ctrl, m_type;
	82	u32 prev = curr_perf_level;
	83	unsigned long flags;
	84
	85	if ((curr_perf_level == level) && !force)
	86	return prev;
	87
96609ef4	88	if (level == CORE_CLK_SRC_DPLL)
f2ab9977	89	dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
96609ef4	90	else if (level == CORE_CLK_SRC_DPLL_X2)
f2ab9977	91	dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
96609ef4	92	else
6b8858a9	93	return prev;
6b8858a9	94
f2ab9977	95	m_type = omap2xxx_sdrc_get_type();
6b8858a9 PW	96
6b8858a9 PW	97	local_irq_save(flags);
c4d7e58f PW	98	/*
	99	* XXX These calls should be abstracted out through a
	100	* prm2xxx.c function
	101	*/
8e3bd351	102	if (cpu_is_omap2420())
edfaf05c	103	writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
8e3bd351	104	else
edfaf05c	105	writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
6b8858a9 PW	106	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	107	curr_perf_level = level;
	108	local_irq_restore(flags);
	109
	110	return prev;
	111	}
	112
f2ab9977 PW	113	/* Used by the clock framework during CORE DPLL changes */
f2ab9977 PW	114	void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
b824efae TL	115	{
	116	unsigned long dll_cnt;
	117	u32 fast_dll = 0;
	118
96609ef4 PW	119	/* DDR = 1, SDR = 0 */
96609ef4 PW	120	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
b824efae TL	121
	122	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	123	* In the case of 2422, its ok to use CS1 instead of CS0.
	124	*/
	125	if (cpu_is_omap2422())
	126	mem_timings.base_cs = 1;
	127	else
	128	mem_timings.base_cs = 0;
	129
	130	if (mem_timings.m_type != M_DDR)
	131	return;
	132
	133	/* With DDR we need to determine the low frequency DLL value */
	134	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
	135	mem_timings.dll_mode = M_UNLOCK;
	136	else
	137	mem_timings.dll_mode = M_LOCK;
	138
	139	if (mem_timings.base_cs == 0) {
44595982 PW	140	fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
44595982 PW	141	dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
b824efae	142	} else {
44595982 PW	143	fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
44595982 PW	144	dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
b824efae TL	145	}
	146	if (force_lock_to_unlock_mode) {
	147	fast_dll &= ~0xff00;
	148	fast_dll \|= dll_cnt; /* Current lock mode */
	149	}
	150	/* set fast timings with DLL filter disabled */
	151	mem_timings.fast_dll_ctrl = (fast_dll \| (3 << 8));
	152
	153	/* No disruptions, DDR will be offline & C-ABI not followed */
	154	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
	155	mem_timings.fast_dll_ctrl,
	156	mem_timings.base_cs,
	157	force_lock_to_unlock_mode);
	158	mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
	159
	160	/* Turn status into unlock ctrl */
	161	mem_timings.slow_dll_ctrl \|=
	162	((mem_timings.fast_dll_ctrl & 0xF) \| (1 << 2));
	163
6a53bc75	164	/* 90 degree phase for anything below 133MHz + disable DLL filter */
b824efae TL	165	mem_timings.slow_dll_ctrl \|= ((1 << 1) \| (3 << 8));
b824efae TL	166	}