[linux-2.6-block.git] / arch / arm / mach-omap2 / sdrc2xxx.c

/*
 * linux/arch/arm/mach-omap2/sdrc2xxx.c
 *
 * SDRAM timing related functions for OMAP2xxx
 *
 * Copyright (C) 2005, 2008 Texas Instruments Inc.
 * Copyright (C) 2005, 2008 Nokia Corporation
 *
 * Tony Lindgren <tony@atomide.com>
 * Paul Walmsley
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/common.h>
#include <mach/clock.h>
#include <mach/sram.h>

#include "prm.h"
#include "clock.h"
#include <mach/sdrc.h>
#include "sdrc.h"

/* Memory timing, DLL mode flags */
#define M_DDR		1
#define M_LOCK_CTRL	(1 << 2)
#define M_UNLOCK	0
#define M_LOCK		1


static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
{
	return mem_timings.slow_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
{
	return mem_timings.fast_dll_ctrl;
}

static u32 omap2xxx_sdrc_get_type(void)
{
	return mem_timings.m_type;
}

/*
 * Check the DLL lock state, and return tue if running in unlock mode.
 * This is needed to compensate for the shifted DLL value in unlock mode.
 */
u32 omap2xxx_sdrc_dll_is_unlocked(void)
{
	/* dlla and dllb are a set */
	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);

	if ((dll_state & (1 << 2)) == (1 << 2))
		return 1;
	else
		return 0;
}

/*
 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
 *
 * Used by the clock framework during CORE DPLL changes
 */
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
{
	u32 dll_ctrl, m_type;
	u32 prev = curr_perf_level;
	unsigned long flags;

	if ((curr_perf_level == level) && !force)
		return prev;

	if (level == CORE_CLK_SRC_DPLL)
		dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
	else if (level == CORE_CLK_SRC_DPLL_X2)
		dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
	else
		return prev;

	m_type = omap2xxx_sdrc_get_type();

	local_irq_save(flags);
	__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	curr_perf_level = level;
	local_irq_restore(flags);

	return prev;
}

/* Used by the clock framework during CORE DPLL changes */
void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
{
	unsigned long dll_cnt;
	u32 fast_dll = 0;

	/* DDR = 1, SDR = 0 */
	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);

	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	 * In the case of 2422, its ok to use CS1 instead of CS0.
	 */
	if (cpu_is_omap2422())
		mem_timings.base_cs = 1;
	else
		mem_timings.base_cs = 0;

	if (mem_timings.m_type != M_DDR)
		return;

	/* With DDR we need to determine the low frequency DLL value */
	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
		mem_timings.dll_mode = M_UNLOCK;
	else
		mem_timings.dll_mode = M_LOCK;

	if (mem_timings.base_cs == 0) {
		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
	} else {
		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
	}
	if (force_lock_to_unlock_mode) {
		fast_dll &= ~0xff00;
		fast_dll |= dll_cnt;		/* Current lock mode */
	}
	/* set fast timings with DLL filter disabled */
	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));

	/* No disruptions, DDR will be offline & C-ABI not followed */
	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
			    mem_timings.fast_dll_ctrl,
			    mem_timings.base_cs,
			    force_lock_to_unlock_mode);
	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */

	/* Turn status into unlock ctrl */
	mem_timings.slow_dll_ctrl |=
		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));

	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
Commit	Line	Data
b824efae	1	/*
96609ef4	2	* linux/arch/arm/mach-omap2/sdrc2xxx.c
b824efae	3	*
96609ef4	4	* SDRAM timing related functions for OMAP2xxx
b824efae	5	*
f2ab9977 PW	6	* Copyright (C) 2005, 2008 Texas Instruments Inc.
f2ab9977 PW	7	* Copyright (C) 2005, 2008 Nokia Corporation
b824efae	8	*
b824efae	9	* Tony Lindgren <tony@atomide.com>
f2ab9977 PW	10	* Paul Walmsley
f2ab9977 PW	11	* Richard Woodruff <r-woodruff2@ti.com>
b824efae TL	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17
b824efae TL	18	#include <linux/module.h>
	19	#include <linux/kernel.h>
	20	#include <linux/device.h>
	21	#include <linux/list.h>
	22	#include <linux/errno.h>
	23	#include <linux/delay.h>
	24	#include <linux/clk.h>
fced80c7	25	#include <linux/io.h>
b824efae	26
a09e64fb RK	27	#include <mach/common.h>
	28	#include <mach/clock.h>
	29	#include <mach/sram.h>
b824efae	30
44595982	31	#include "prm.h"
c0bf3132	32	#include "clock.h"
f8de9b2c	33	#include <mach/sdrc.h>
44595982	34	#include "sdrc.h"
b824efae	35
f8de9b2c PW	36	/* Memory timing, DLL mode flags */
	37	#define M_DDR 1
	38	#define M_LOCK_CTRL (1 << 2)
	39	#define M_UNLOCK 0
	40	#define M_LOCK 1
	41
	42
b824efae	43	static struct memory_timings mem_timings;
44595982	44	static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
b824efae	45
f2ab9977	46	static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
b824efae TL	47	{
	48	return mem_timings.slow_dll_ctrl;
	49	}
	50
f2ab9977	51	static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
b824efae TL	52	{
	53	return mem_timings.fast_dll_ctrl;
	54	}
	55
f2ab9977	56	static u32 omap2xxx_sdrc_get_type(void)
b824efae TL	57	{
	58	return mem_timings.m_type;
	59	}
	60
6b8858a9 PW	61	/*
	62	* Check the DLL lock state, and return tue if running in unlock mode.
	63	* This is needed to compensate for the shifted DLL value in unlock mode.
	64	*/
f2ab9977	65	u32 omap2xxx_sdrc_dll_is_unlocked(void)
6b8858a9 PW	66	{
	67	/* dlla and dllb are a set */
	68	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
	69
	70	if ((dll_state & (1 << 2)) == (1 << 2))
	71	return 1;
	72	else
	73	return 0;
	74	}
	75
	76	/*
	77	* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
	78	* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
	79	* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
f2ab9977 PW	80	*
f2ab9977 PW	81	* Used by the clock framework during CORE DPLL changes
6b8858a9	82	*/
f2ab9977	83	u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
6b8858a9 PW	84	{
	85	u32 dll_ctrl, m_type;
	86	u32 prev = curr_perf_level;
	87	unsigned long flags;
	88
	89	if ((curr_perf_level == level) && !force)
	90	return prev;
	91
96609ef4	92	if (level == CORE_CLK_SRC_DPLL)
f2ab9977	93	dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
96609ef4	94	else if (level == CORE_CLK_SRC_DPLL_X2)
f2ab9977	95	dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
96609ef4	96	else
6b8858a9	97	return prev;
6b8858a9	98
f2ab9977	99	m_type = omap2xxx_sdrc_get_type();
6b8858a9 PW	100
	101	local_irq_save(flags);
	102	__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
	103	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	104	curr_perf_level = level;
	105	local_irq_restore(flags);
	106
	107	return prev;
	108	}
	109
f2ab9977 PW	110	/* Used by the clock framework during CORE DPLL changes */
f2ab9977 PW	111	void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
b824efae TL	112	{
	113	unsigned long dll_cnt;
	114	u32 fast_dll = 0;
	115
96609ef4 PW	116	/* DDR = 1, SDR = 0 */
96609ef4 PW	117	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
b824efae TL	118
	119	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	120	* In the case of 2422, its ok to use CS1 instead of CS0.
	121	*/
	122	if (cpu_is_omap2422())
	123	mem_timings.base_cs = 1;
	124	else
	125	mem_timings.base_cs = 0;
	126
	127	if (mem_timings.m_type != M_DDR)
	128	return;
	129
	130	/* With DDR we need to determine the low frequency DLL value */
	131	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
	132	mem_timings.dll_mode = M_UNLOCK;
	133	else
	134	mem_timings.dll_mode = M_LOCK;
	135
	136	if (mem_timings.base_cs == 0) {
44595982 PW	137	fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
44595982 PW	138	dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
b824efae	139	} else {
44595982 PW	140	fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
44595982 PW	141	dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
b824efae TL	142	}
	143	if (force_lock_to_unlock_mode) {
	144	fast_dll &= ~0xff00;
	145	fast_dll \|= dll_cnt; /* Current lock mode */
	146	}
	147	/* set fast timings with DLL filter disabled */
	148	mem_timings.fast_dll_ctrl = (fast_dll \| (3 << 8));
	149
	150	/* No disruptions, DDR will be offline & C-ABI not followed */
	151	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
	152	mem_timings.fast_dll_ctrl,
	153	mem_timings.base_cs,
	154	force_lock_to_unlock_mode);
	155	mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
	156
	157	/* Turn status into unlock ctrl */
	158	mem_timings.slow_dll_ctrl \|=
	159	((mem_timings.fast_dll_ctrl & 0xF) \| (1 << 2));
	160
	161	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	162	mem_timings.slow_dll_ctrl \|= ((1 << 1) \| (3 << 8));
	163	}