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1 | /* |
2 | * OMAP3xxx Power/Reset Management (PRM) register definitions | |
3 | * | |
4 | * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. | |
5 | * Copyright (C) 2008-2010 Nokia Corporation | |
6 | * Paul Walmsley | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The PRM hardware modules on the OMAP2/3 are quite similar to each | |
13 | * other. The PRM on OMAP4 has a new register layout, and is handled | |
14 | * in a separate file. | |
15 | */ | |
16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H | |
18 | ||
19 | #include "prcm-common.h" | |
20 | #include "prm.h" | |
21 | #include "prm2xxx_3xxx.h" | |
22 | ||
23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | |
24 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | |
25 | ||
26 | ||
27 | /* | |
28 | * OMAP3-specific global PRM registers | |
29 | * Use __raw_{read,write}l() with these registers. | |
30 | * | |
31 | * With a few exceptions, these are the register names beginning with | |
32 | * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE | |
33 | * bits.) | |
34 | */ | |
35 | ||
36 | #define OMAP3_PRM_REVISION_OFFSET 0x0004 | |
37 | #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) | |
38 | #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 | |
39 | #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) | |
40 | ||
41 | #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 | |
42 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) | |
43 | #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c | |
44 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) | |
45 | ||
46 | ||
47 | #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 | |
48 | #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) | |
49 | #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 | |
50 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) | |
51 | #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 | |
52 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) | |
53 | #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c | |
54 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) | |
55 | #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 | |
56 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) | |
57 | #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 | |
58 | #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) | |
59 | #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 | |
60 | #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) | |
61 | #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c | |
62 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) | |
63 | #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 | |
64 | #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) | |
65 | #define OMAP3_PRM_RSTTIME_OFFSET 0x0054 | |
66 | #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) | |
67 | #define OMAP3_PRM_RSTST_OFFSET 0x0058 | |
68 | #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) | |
69 | #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 | |
70 | #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) | |
71 | #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 | |
72 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) | |
73 | #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 | |
74 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) | |
75 | #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 | |
76 | #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) | |
77 | #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 | |
78 | #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) | |
79 | #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 | |
80 | #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) | |
81 | #define OMAP3_PRM_POLCTRL_OFFSET 0x009c | |
82 | #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) | |
83 | #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 | |
84 | #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) | |
85 | #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 | |
86 | #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) | |
87 | #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 | |
88 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) | |
89 | #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 | |
90 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) | |
91 | #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc | |
92 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) | |
93 | #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 | |
94 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) | |
95 | #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 | |
96 | #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) | |
97 | #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 | |
98 | #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) | |
99 | #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 | |
100 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) | |
101 | #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 | |
102 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) | |
103 | #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc | |
104 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) | |
105 | #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 | |
106 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | |
107 | #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 | |
108 | #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | |
109 | ||
110 | #define OMAP3_PRM_CLKSEL_OFFSET 0x0040 | |
111 | #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | |
112 | #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 | |
113 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | |
114 | ||
115 | /* OMAP3 specific register offsets */ | |
116 | #define OMAP3430ES2_PM_WKEN3 0x00f0 | |
117 | #define OMAP3430ES2_PM_WKST3 0x00b8 | |
118 | ||
119 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | |
120 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | |
121 | #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 | |
122 | ||
123 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 | |
124 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL | |
125 | #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 | |
126 | ||
127 | #define OMAP3430_PM_PREPWSTST 0x00e8 | |
128 | ||
129 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | |
130 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | |
131 | ||
132 | ||
133 | #ifndef __ASSEMBLER__ | |
134 | ||
135 | /* OMAP3-specific VP functions */ | |
136 | u32 omap3_prm_vp_check_txdone(u8 vp_id); | |
137 | void omap3_prm_vp_clear_txdone(u8 vp_id); | |
138 | ||
139 | /* | |
140 | * OMAP3 access functions for voltage controller (VC) and | |
141 | * voltage proccessor (VP) in the PRM. | |
142 | */ | |
143 | extern u32 omap3_prm_vcvp_read(u8 offset); | |
144 | extern void omap3_prm_vcvp_write(u32 val, u8 offset); | |
145 | extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); | |
146 | ||
147 | extern void omap3xxx_prm_reconfigure_io_chain(void); | |
148 | ||
149 | /* PRM interrupt-related functions */ | |
150 | extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); | |
151 | extern void omap3xxx_prm_ocp_barrier(void); | |
152 | extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); | |
153 | extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); | |
154 | ||
155 | #endif /* __ASSEMBLER */ | |
156 | ||
157 | ||
158 | #endif |