[linux-block.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>

#include "soc.h"
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
		[1] = PWRSTS_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_am35x_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_am35x_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,	 /* MEM1RETSTATE */
		[1] = PWRSTS_ON,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_am35x_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain sgx_am35x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_am35x_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain neon_am35x_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain alwon_81xx_pwrdm = {
	.name		  = "alwon_pwrdm",
	.prcm_offs	  = TI81XX_PRM_ALWON_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain device_81xx_pwrdm = {
	.name		  = "device_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEVICE_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain gem_814x_pwrdm = {
	.name		= "gem_pwrdm",
	.prcm_offs	= TI814X_PRM_DSP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain ivahd_814x_pwrdm = {
	.name		= "ivahd_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVICP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "iva" },
};

static struct powerdomain hdvpss_814x_pwrdm = {
	.name		= "hdvpss_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVPSS_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain sgx_814x_pwrdm = {
	.name		= "sgx_pwrdm",
	.prcm_offs	= TI814X_PRM_GFX_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain isp_814x_pwrdm = {
	.name		= "isp_pwrdm",
	.prcm_offs	= TI814X_PRM_ISP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain active_81xx_pwrdm = {
	.name		  = "active_pwrdm",
	.prcm_offs	  = TI816X_PRM_ACTIVE_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain default_81xx_pwrdm = {
	.name		  = "default_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEFAULT_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain ivahd0_816x_pwrdm = {
	.name		  = "ivahd0_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD0_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd1_816x_pwrdm = {
	.name		  = "ivahd1_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD1_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd2_816x_pwrdm = {
	.name		  = "ivahd2_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD2_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain sgx_816x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = TI816X_PRM_SGX_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
	&wkup_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	&gfx_omap2_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	NULL
};

/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	&core_3xxx_pre_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	&core_3xxx_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_am35x[] __initdata = {
	&wkup_omap2_pwrdm,
	&mpu_am35x_pwrdm,
	&neon_am35x_pwrdm,
	&core_am35x_pwrdm,
	&sgx_am35x_pwrdm,
	&dss_am35x_pwrdm,
	&per_am35x_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti814x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&gem_814x_pwrdm,
	&ivahd_814x_pwrdm,
	&hdvpss_814x_pwrdm,
	&sgx_814x_pwrdm,
	&isp_814x_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti816x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&ivahd0_816x_pwrdm,
	&ivahd1_816x_pwrdm,
	&ivahd2_816x_pwrdm,
	&sgx_816x_pwrdm,
	NULL
};

/* TI81XX specific ops */
#define TI81XX_PM_PWSTCTRL				0x0000
#define TI81XX_RM_RSTCTRL				0x0010
#define TI81XX_PM_PWSTST				0x0004

static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
				   (pwrst << OMAP_POWERSTATE_SHIFT),
				   pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
	return 0;
}

static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
					     TI81XX_PM_PWSTCTRL,
					     OMAP_POWERSTATE_MASK);
}

static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP_POWERSTATEST_MASK);
}

static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP3430_LOGICSTATEST_MASK);
}

static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
	u32 c = 0;

	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
				       TI81XX_PM_PWSTST) &
		OMAP_INTRANSITION_MASK) &&
		(c++ < PWRDM_TRANSITION_BAILOUT))
			udelay(1);

	if (c > PWRDM_TRANSITION_BAILOUT) {
		pr_err("powerdomain: %s timeout waiting for transition\n",
		       pwrdm->name);
		return -EAGAIN;
	}

	pr_debug("powerdomain: completed transition in %d loops\n", c);

	return 0;
}

/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
static struct pwrdm_ops ti81xx_pwrdm_operations = {
	.pwrdm_set_next_pwrst	= ti81xx_pwrdm_set_next_pwrst,
	.pwrdm_read_next_pwrst	= ti81xx_pwrdm_read_next_pwrst,
	.pwrdm_read_pwrst	= ti81xx_pwrdm_read_pwrst,
	.pwrdm_read_logic_pwrst	= ti81xx_pwrdm_read_logic_pwrst,
	.pwrdm_wait_transition	= ti81xx_pwrdm_wait_transition,
};

void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
		return;

	/* Only 81xx needs custom pwrdm_operations */
	if (!cpu_is_ti81xx())
		pwrdm_register_platform_funcs(&omap3_pwrdm_operations);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		pwrdm_register_pwrdms(powerdomains_am35x);
	} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
		   rev == TI8148_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti814x);
	} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
			|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti816x);
	} else {
		pwrdm_register_pwrdms(powerdomains_omap3430_common);

		switch (rev) {
		case OMAP3430_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es1);
			break;
		case OMAP3430_REV_ES2_0:
		case OMAP3430_REV_ES2_1:
		case OMAP3430_REV_ES3_0:
		case OMAP3630_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
			break;
		case OMAP3430_REV_ES3_1:
		case OMAP3430_REV_ES3_1_2:
		case OMAP3630_REV_ES1_1:
		case OMAP3630_REV_ES1_2:
			pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
			break;
		default:
			WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
		}
	}

	pwrdm_complete_init();
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
ecb24aa1	2	/*
98fa3d8a	3	* OMAP3 powerdomain definitions
ecb24aa1	4	*
8179488a	5	* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
4cb49fec	6	* Copyright (C) 2007-2011 Nokia Corporation
ecb24aa1	7	*
6e01478a	8	* Paul Walmsley, Jouni Högander
ecb24aa1 PW	9	*/
ecb24aa1 PW	10
6e01478a PW	11	#include <linux/kernel.h>
6e01478a PW	12	#include <linux/init.h>
d9a5f4dd	13	#include <linux/bug.h>
ecb24aa1	14
dbc04161	15	#include "soc.h"
72e06d08	16	#include "powerdomain.h"
6e01478a	17	#include "powerdomains2xxx_3xxx_data.h"
ecb24aa1	18	#include "prcm-common.h"
59fb659b	19	#include "prm2xxx_3xxx.h"
ecb24aa1	20	#include "prm-regbits-34xx.h"
59fb659b	21	#include "cm2xxx_3xxx.h"
ecb24aa1 PW	22	#include "cm-regbits-34xx.h"
	23
	24	/*
	25	* 34XX-specific powerdomains, dependencies
	26	*/
	27
ecb24aa1 PW	28	/*
	29	* Powerdomains
	30	*/
	31
	32	static struct powerdomain iva2_pwrdm = {
	33	.name = "iva2_pwrdm",
	34	.prcm_offs = OMAP3430_IVA2_MOD,
ecb24aa1 PW	35	.pwrsts = PWRSTS_OFF_RET_ON,
	36	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	37	.banks = 4,
	38	.pwrsts_mem_ret = {
	39	[0] = PWRSTS_OFF_RET,
	40	[1] = PWRSTS_OFF_RET,
	41	[2] = PWRSTS_OFF_RET,
	42	[3] = PWRSTS_OFF_RET,
	43	},
	44	.pwrsts_mem_on = {
4cb49fec PW	45	[0] = PWRSTS_ON,
4cb49fec PW	46	[1] = PWRSTS_ON,
ecb24aa1	47	[2] = PWRSTS_OFF_ON,
4cb49fec	48	[3] = PWRSTS_ON,
ecb24aa1	49	},
562e54d1	50	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	51	};
ecb24aa1 PW	52
98fa3d8a	53	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	54	.name = "mpu_pwrdm",
ecb24aa1 PW	55	.prcm_offs = MPU_MOD,
ecb24aa1 PW	56	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	57	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	58	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	59	.banks = 1,
	60	.pwrsts_mem_ret = {
	61	[0] = PWRSTS_OFF_RET,
	62	},
	63	.pwrsts_mem_on = {
	64	[0] = PWRSTS_OFF_ON,
	65	},
562e54d1	66	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	67	};
ecb24aa1 PW	68
ff7ad7e4 MG	69	static struct powerdomain mpu_am35x_pwrdm = {
	70	.name = "mpu_pwrdm",
	71	.prcm_offs = MPU_MOD,
	72	.pwrsts = PWRSTS_ON,
	73	.pwrsts_logic_ret = PWRSTS_ON,
	74	.flags = PWRDM_HAS_MPU_QUIRK,
	75	.banks = 1,
	76	.pwrsts_mem_ret = {
	77	[0] = PWRSTS_ON,
	78	},
	79	.pwrsts_mem_on = {
	80	[0] = PWRSTS_ON,
	81	},
562e54d1	82	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	83	};
ff7ad7e4 MG	84
58dcfb3a AG	85	/*
58dcfb3a AG	86	* The USBTLL Save-and-Restore mechanism is broken on
25985edc	87	* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
58dcfb3a AG	88	* needs to be disabled on these chips.
58dcfb3a AG	89	* Refer: 3430 errata ID i459 and 3630 errata ID i579
447b8da5 JP	90	*
	91	* Note: setting the SAR flag could help for errata ID i478
	92	* which applies to 3430 <= ES3.1, but since the SAR feature
	93	* is broken, do not use it.
58dcfb3a	94	*/
98fa3d8a	95	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	96	.name = "core_pwrdm",
ecb24aa1 PW	97	.prcm_offs = CORE_MOD,
7eb1afc9	98	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	99	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	100	.banks = 2,
	101	.pwrsts_mem_ret = {
	102	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	103	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	104	},
	105	.pwrsts_mem_on = {
	106	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	107	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	108	},
562e54d1	109	.voltdm = { .name = "core" },
7eb1afc9 PW	110	};
7eb1afc9 PW	111
98fa3d8a	112	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	113	.name = "core_pwrdm",
7eb1afc9 PW	114	.prcm_offs = CORE_MOD,
ecb24aa1	115	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	116	.pwrsts_logic_ret = PWRSTS_OFF_RET,
447b8da5 JP	117	/*
	118	* Setting the SAR flag for errata ID i478 which applies
	119	* to 3430 <= ES3.1
	120	*/
7eb1afc9	121	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	122	.banks = 2,
	123	.pwrsts_mem_ret = {
	124	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	125	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	126	},
	127	.pwrsts_mem_on = {
	128	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	129	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	130	},
562e54d1	131	.voltdm = { .name = "core" },
ecb24aa1 PW	132	};
ecb24aa1 PW	133
ff7ad7e4 MG	134	static struct powerdomain core_am35x_pwrdm = {
	135	.name = "core_pwrdm",
	136	.prcm_offs = CORE_MOD,
	137	.pwrsts = PWRSTS_ON,
	138	.pwrsts_logic_ret = PWRSTS_ON,
	139	.banks = 2,
	140	.pwrsts_mem_ret = {
	141	[0] = PWRSTS_ON, /* MEM1RETSTATE */
	142	[1] = PWRSTS_ON, /* MEM2RETSTATE */
	143	},
	144	.pwrsts_mem_on = {
	145	[0] = PWRSTS_ON, /* MEM1ONSTATE */
	146	[1] = PWRSTS_ON, /* MEM2ONSTATE */
	147	},
562e54d1	148	.voltdm = { .name = "core" },
ff7ad7e4 MG	149	};
ff7ad7e4 MG	150
ecb24aa1 PW	151	static struct powerdomain dss_pwrdm = {
ecb24aa1 PW	152	.name = "dss_pwrdm",
ecb24aa1	153	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1	154	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	155	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	156	.banks = 1,
ecb24aa1 PW	157	.pwrsts_mem_ret = {
4cb49fec	158	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	159	},
ecb24aa1 PW	160	.pwrsts_mem_on = {
4cb49fec	161	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	162	},
562e54d1	163	.voltdm = { .name = "core" },
ecb24aa1 PW	164	};
ecb24aa1 PW	165
ff7ad7e4 MG	166	static struct powerdomain dss_am35x_pwrdm = {
	167	.name = "dss_pwrdm",
	168	.prcm_offs = OMAP3430_DSS_MOD,
	169	.pwrsts = PWRSTS_ON,
	170	.pwrsts_logic_ret = PWRSTS_ON,
	171	.banks = 1,
	172	.pwrsts_mem_ret = {
	173	[0] = PWRSTS_ON, /* MEMRETSTATE */
	174	},
	175	.pwrsts_mem_on = {
	176	[0] = PWRSTS_ON, /* MEMONSTATE */
	177	},
562e54d1	178	.voltdm = { .name = "core" },
ff7ad7e4 MG	179	};
ff7ad7e4 MG	180
be48ea74 PW	181	/*
	182	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	183	* possible SGX powerstate, the SGX device itself does not support
	184	* retention.
	185	*/
ecb24aa1 PW	186	static struct powerdomain sgx_pwrdm = {
	187	.name = "sgx_pwrdm",
	188	.prcm_offs = OMAP3430ES2_SGX_MOD,
ecb24aa1	189	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	190	.pwrsts = PWRSTS_OFF_ON,
4cb49fec	191	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	192	.banks = 1,
ecb24aa1 PW	193	.pwrsts_mem_ret = {
4cb49fec	194	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	195	},
ecb24aa1 PW	196	.pwrsts_mem_on = {
4cb49fec	197	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	198	},
562e54d1	199	.voltdm = { .name = "core" },
ecb24aa1 PW	200	};
ecb24aa1 PW	201
ff7ad7e4 MG	202	static struct powerdomain sgx_am35x_pwrdm = {
	203	.name = "sgx_pwrdm",
	204	.prcm_offs = OMAP3430ES2_SGX_MOD,
	205	.pwrsts = PWRSTS_ON,
	206	.pwrsts_logic_ret = PWRSTS_ON,
	207	.banks = 1,
	208	.pwrsts_mem_ret = {
	209	[0] = PWRSTS_ON, /* MEMRETSTATE */
	210	},
	211	.pwrsts_mem_on = {
	212	[0] = PWRSTS_ON, /* MEMONSTATE */
	213	},
562e54d1	214	.voltdm = { .name = "core" },
ff7ad7e4 MG	215	};
ff7ad7e4 MG	216
ecb24aa1 PW	217	static struct powerdomain cam_pwrdm = {
ecb24aa1 PW	218	.name = "cam_pwrdm",
ecb24aa1	219	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1	220	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	221	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	222	.banks = 1,
ecb24aa1 PW	223	.pwrsts_mem_ret = {
4cb49fec	224	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	225	},
ecb24aa1 PW	226	.pwrsts_mem_on = {
4cb49fec	227	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	228	},
562e54d1	229	.voltdm = { .name = "core" },
ecb24aa1 PW	230	};
	231
	232	static struct powerdomain per_pwrdm = {
	233	.name = "per_pwrdm",
	234	.prcm_offs = OMAP3430_PER_MOD,
ecb24aa1 PW	235	.pwrsts = PWRSTS_OFF_RET_ON,
	236	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	237	.banks = 1,
	238	.pwrsts_mem_ret = {
4cb49fec	239	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	240	},
ecb24aa1 PW	241	.pwrsts_mem_on = {
4cb49fec	242	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	243	},
562e54d1	244	.voltdm = { .name = "core" },
ecb24aa1 PW	245	};
ecb24aa1 PW	246
ff7ad7e4 MG	247	static struct powerdomain per_am35x_pwrdm = {
	248	.name = "per_pwrdm",
	249	.prcm_offs = OMAP3430_PER_MOD,
	250	.pwrsts = PWRSTS_ON,
	251	.pwrsts_logic_ret = PWRSTS_ON,
	252	.banks = 1,
	253	.pwrsts_mem_ret = {
	254	[0] = PWRSTS_ON, /* MEMRETSTATE */
	255	},
	256	.pwrsts_mem_on = {
	257	[0] = PWRSTS_ON, /* MEMONSTATE */
	258	},
562e54d1	259	.voltdm = { .name = "core" },
ff7ad7e4 MG	260	};
ff7ad7e4 MG	261
ecb24aa1 PW	262	static struct powerdomain emu_pwrdm = {
	263	.name = "emu_pwrdm",
	264	.prcm_offs = OMAP3430_EMU_MOD,
562e54d1	265	.voltdm = { .name = "core" },
ecb24aa1 PW	266	};
	267
	268	static struct powerdomain neon_pwrdm = {
	269	.name = "neon_pwrdm",
	270	.prcm_offs = OMAP3430_NEON_MOD,
ecb24aa1	271	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	272	.pwrsts_logic_ret = PWRSTS_RET,
562e54d1	273	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	274	};
ecb24aa1 PW	275
ff7ad7e4 MG	276	static struct powerdomain neon_am35x_pwrdm = {
	277	.name = "neon_pwrdm",
	278	.prcm_offs = OMAP3430_NEON_MOD,
	279	.pwrsts = PWRSTS_ON,
	280	.pwrsts_logic_ret = PWRSTS_ON,
562e54d1	281	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	282	};
ff7ad7e4 MG	283
ecb24aa1 PW	284	static struct powerdomain usbhost_pwrdm = {
	285	.name = "usbhost_pwrdm",
	286	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
ecb24aa1	287	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	288	.pwrsts_logic_ret = PWRSTS_RET,
867d320b KJ	289	/*
	290	* REVISIT: Enabling usb host save and restore mechanism seems to
	291	* leave the usb host domain permanently in ACTIVE mode after
	292	* changing the usb host power domain state from OFF to active once.
	293	* Disabling for now.
	294	*/
	295	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	296	.banks = 1,
ecb24aa1 PW	297	.pwrsts_mem_ret = {
4cb49fec	298	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	299	},
ecb24aa1 PW	300	.pwrsts_mem_on = {
4cb49fec	301	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	302	},
562e54d1	303	.voltdm = { .name = "core" },
ecb24aa1 PW	304	};
ecb24aa1 PW	305
46e0ccf8 PW	306	static struct powerdomain dpll1_pwrdm = {
	307	.name = "dpll1_pwrdm",
	308	.prcm_offs = MPU_MOD,
562e54d1	309	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	310	};
	311
	312	static struct powerdomain dpll2_pwrdm = {
	313	.name = "dpll2_pwrdm",
	314	.prcm_offs = OMAP3430_IVA2_MOD,
562e54d1	315	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	316	};
	317
	318	static struct powerdomain dpll3_pwrdm = {
	319	.name = "dpll3_pwrdm",
	320	.prcm_offs = PLL_MOD,
562e54d1	321	.voltdm = { .name = "core" },
46e0ccf8 PW	322	};
	323
	324	static struct powerdomain dpll4_pwrdm = {
	325	.name = "dpll4_pwrdm",
	326	.prcm_offs = PLL_MOD,
562e54d1	327	.voltdm = { .name = "core" },
46e0ccf8 PW	328	};
	329
	330	static struct powerdomain dpll5_pwrdm = {
	331	.name = "dpll5_pwrdm",
	332	.prcm_offs = PLL_MOD,
562e54d1	333	.voltdm = { .name = "core" },
46e0ccf8 PW	334	};
46e0ccf8 PW	335
0f0dd089 AM	336	static struct powerdomain alwon_81xx_pwrdm = {
	337	.name = "alwon_pwrdm",
	338	.prcm_offs = TI81XX_PRM_ALWON_MOD,
	339	.pwrsts = PWRSTS_OFF_ON,
	340	.voltdm = { .name = "core" },
	341	};
	342
c3ed359c AM	343	static struct powerdomain device_81xx_pwrdm = {
	344	.name = "device_pwrdm",
	345	.prcm_offs = TI81XX_PRM_DEVICE_MOD,
	346	.voltdm = { .name = "core" },
	347	};
	348
7c80a3f8 TL	349	static struct powerdomain gem_814x_pwrdm = {
	350	.name = "gem_pwrdm",
	351	.prcm_offs = TI814X_PRM_DSP_MOD,
	352	.pwrsts = PWRSTS_OFF_ON,
	353	.voltdm = { .name = "dsp" },
	354	};
	355
	356	static struct powerdomain ivahd_814x_pwrdm = {
	357	.name = "ivahd_pwrdm",
	358	.prcm_offs = TI814X_PRM_HDVICP_MOD,
	359	.pwrsts = PWRSTS_OFF_ON,
	360	.voltdm = { .name = "iva" },
	361	};
	362
	363	static struct powerdomain hdvpss_814x_pwrdm = {
	364	.name = "hdvpss_pwrdm",
	365	.prcm_offs = TI814X_PRM_HDVPSS_MOD,
	366	.pwrsts = PWRSTS_OFF_ON,
	367	.voltdm = { .name = "dsp" },
	368	};
	369
	370	static struct powerdomain sgx_814x_pwrdm = {
	371	.name = "sgx_pwrdm",
	372	.prcm_offs = TI814X_PRM_GFX_MOD,
	373	.pwrsts = PWRSTS_OFF_ON,
	374	.voltdm = { .name = "core" },
	375	};
	376
	377	static struct powerdomain isp_814x_pwrdm = {
	378	.name = "isp_pwrdm",
	379	.prcm_offs = TI814X_PRM_ISP_MOD,
	380	.pwrsts = PWRSTS_OFF_ON,
	381	.voltdm = { .name = "core" },
	382	};
	383
418d4ebc	384	static struct powerdomain active_81xx_pwrdm = {
c3ed359c AM	385	.name = "active_pwrdm",
	386	.prcm_offs = TI816X_PRM_ACTIVE_MOD,
	387	.pwrsts = PWRSTS_OFF_ON,
	388	.voltdm = { .name = "core" },
	389	};
	390
418d4ebc	391	static struct powerdomain default_81xx_pwrdm = {
c3ed359c AM	392	.name = "default_pwrdm",
	393	.prcm_offs = TI81XX_PRM_DEFAULT_MOD,
	394	.pwrsts = PWRSTS_OFF_ON,
	395	.voltdm = { .name = "core" },
	396	};
	397
	398	static struct powerdomain ivahd0_816x_pwrdm = {
	399	.name = "ivahd0_pwrdm",
	400	.prcm_offs = TI816X_PRM_IVAHD0_MOD,
	401	.pwrsts = PWRSTS_OFF_ON,
	402	.voltdm = { .name = "mpu_iva" },
	403	};
	404
	405	static struct powerdomain ivahd1_816x_pwrdm = {
	406	.name = "ivahd1_pwrdm",
	407	.prcm_offs = TI816X_PRM_IVAHD1_MOD,
	408	.pwrsts = PWRSTS_OFF_ON,
	409	.voltdm = { .name = "mpu_iva" },
	410	};
	411
	412	static struct powerdomain ivahd2_816x_pwrdm = {
	413	.name = "ivahd2_pwrdm",
	414	.prcm_offs = TI816X_PRM_IVAHD2_MOD,
	415	.pwrsts = PWRSTS_OFF_ON,
	416	.voltdm = { .name = "mpu_iva" },
	417	};
	418
	419	static struct powerdomain sgx_816x_pwrdm = {
	420	.name = "sgx_pwrdm",
	421	.prcm_offs = TI816X_PRM_SGX_MOD,
	422	.pwrsts = PWRSTS_OFF_ON,
	423	.voltdm = { .name = "core" },
	424	};
	425
6e01478a	426	/* As powerdomains are added or removed above, this list must also be changed */
8179488a	427	static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
6e01478a	428	&wkup_omap2_pwrdm,
6e01478a PW	429	&iva2_pwrdm,
	430	&mpu_3xxx_pwrdm,
	431	&neon_pwrdm,
6e01478a PW	432	&cam_pwrdm,
	433	&dss_pwrdm,
	434	&per_pwrdm,
	435	&emu_pwrdm,
6e01478a PW	436	&dpll1_pwrdm,
	437	&dpll2_pwrdm,
	438	&dpll3_pwrdm,
	439	&dpll4_pwrdm,
8179488a PW	440	NULL
	441	};
	442
	443	static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	444	&gfx_omap2_pwrdm,
	445	&core_3xxx_pre_es3_1_pwrdm,
	446	NULL
	447	};
	448
	449	/* also includes 3630ES1.0 */
	450	static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	451	&core_3xxx_pre_es3_1_pwrdm,
	452	&sgx_pwrdm,
	453	&usbhost_pwrdm,
6e01478a	454	&dpll5_pwrdm,
6e01478a PW	455	NULL
6e01478a PW	456	};
ecb24aa1	457
8179488a PW	458	/* also includes 3630ES1.1+ */
	459	static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	460	&core_3xxx_es3_1_pwrdm,
	461	&sgx_pwrdm,
	462	&usbhost_pwrdm,
	463	&dpll5_pwrdm,
	464	NULL
	465	};
ecb24aa1	466
ff7ad7e4 MG	467	static struct powerdomain *powerdomains_am35x[] __initdata = {
	468	&wkup_omap2_pwrdm,
	469	&mpu_am35x_pwrdm,
	470	&neon_am35x_pwrdm,
	471	&core_am35x_pwrdm,
	472	&sgx_am35x_pwrdm,
	473	&dss_am35x_pwrdm,
	474	&per_am35x_pwrdm,
	475	&emu_pwrdm,
	476	&dpll1_pwrdm,
	477	&dpll3_pwrdm,
	478	&dpll4_pwrdm,
	479	&dpll5_pwrdm,
	480	NULL
	481	};
	482
7c80a3f8 TL	483	static struct powerdomain *powerdomains_ti814x[] __initdata = {
	484	&alwon_81xx_pwrdm,
	485	&device_81xx_pwrdm,
418d4ebc TL	486	&active_81xx_pwrdm,
418d4ebc TL	487	&default_81xx_pwrdm,
7c80a3f8 TL	488	&gem_814x_pwrdm,
	489	&ivahd_814x_pwrdm,
	490	&hdvpss_814x_pwrdm,
	491	&sgx_814x_pwrdm,
	492	&isp_814x_pwrdm,
	493	NULL
	494	};
	495
	496	static struct powerdomain *powerdomains_ti816x[] __initdata = {
0f0dd089	497	&alwon_81xx_pwrdm,
c3ed359c	498	&device_81xx_pwrdm,
418d4ebc TL	499	&active_81xx_pwrdm,
418d4ebc TL	500	&default_81xx_pwrdm,
c3ed359c AM	501	&ivahd0_816x_pwrdm,
	502	&ivahd1_816x_pwrdm,
	503	&ivahd2_816x_pwrdm,
	504	&sgx_816x_pwrdm,
	505	NULL
	506	};
	507
7c80a3f8 TL	508	/* TI81XX specific ops */
	509	#define TI81XX_PM_PWSTCTRL 0x0000
	510	#define TI81XX_RM_RSTCTRL 0x0010
	511	#define TI81XX_PM_PWSTST 0x0004
	512
	513	static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
	514	{
	515	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
	516	(pwrst << OMAP_POWERSTATE_SHIFT),
	517	pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
	518	return 0;
	519	}
	520
	521	static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
	522	{
	523	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	524	TI81XX_PM_PWSTCTRL,
	525	OMAP_POWERSTATE_MASK);
	526	}
	527
	528	static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
	529	{
	530	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	531	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	532	TI81XX_PM_PWSTST,
	533	OMAP_POWERSTATEST_MASK);
	534	}
	535
	536	static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
	537	{
	538	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	539	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	540	TI81XX_PM_PWSTST,
	541	OMAP3430_LOGICSTATEST_MASK);
	542	}
	543
	544	static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
	545	{
	546	u32 c = 0;
	547
	548	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
	549	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	550	TI81XX_PM_PWSTST) &
	551	OMAP_INTRANSITION_MASK) &&
	552	(c++ < PWRDM_TRANSITION_BAILOUT))
	553	udelay(1);
	554
	555	if (c > PWRDM_TRANSITION_BAILOUT) {
	556	pr_err("powerdomain: %s timeout waiting for transition\n",
	557	pwrdm->name);
	558	return -EAGAIN;
	559	}
	560
	561	pr_debug("powerdomain: completed transition in %d loops\n", c);
	562
	563	return 0;
	564	}
	565
	566	/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
	567	static struct pwrdm_ops ti81xx_pwrdm_operations = {
	568	.pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
	569	.pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
	570	.pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
	571	.pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
572	.pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
573	};
574
6e01478a PW	575	void __init omap3xxx_powerdomains_init(void)
6e01478a PW	576	{
8179488a PW	577	unsigned int rev;
8179488a PW	578
c27964b5	579	if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
8179488a PW	580	return;
8179488a PW	581
9610c8ab TL	582	/* Only 81xx needs custom pwrdm_operations */
9610c8ab TL	583	if (!cpu_is_ti81xx())
ae428a72	584	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
8179488a PW	585
	586	rev = omap_rev();
	587
ff7ad7e4 MG	588	if (rev == AM35XX_REV_ES1_0 \|\| rev == AM35XX_REV_ES1_1) {
ff7ad7e4 MG	589	pwrdm_register_pwrdms(powerdomains_am35x);
7c80a3f8 TL	590	} else if (rev == TI8148_REV_ES1_0 \|\| rev == TI8148_REV_ES2_0 \|\|
7c80a3f8 TL	591	rev == TI8148_REV_ES2_1) {
9610c8ab	592	pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
7c80a3f8	593	pwrdm_register_pwrdms(powerdomains_ti814x);
c3ed359c AM	594	} else if (rev == TI8168_REV_ES1_0 \|\| rev == TI8168_REV_ES1_1
c3ed359c AM	595	\|\| rev == TI8168_REV_ES2_0 \|\| rev == TI8168_REV_ES2_1) {
9610c8ab	596	pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
7c80a3f8	597	pwrdm_register_pwrdms(powerdomains_ti816x);
ff7ad7e4 MG	598	} else {
	599	pwrdm_register_pwrdms(powerdomains_omap3430_common);
	600
	601	switch (rev) {
	602	case OMAP3430_REV_ES1_0:
	603	pwrdm_register_pwrdms(powerdomains_omap3430es1);
	604	break;
	605	case OMAP3430_REV_ES2_0:
	606	case OMAP3430_REV_ES2_1:
	607	case OMAP3430_REV_ES3_0:
	608	case OMAP3630_REV_ES1_0:
	609	pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
	610	break;
	611	case OMAP3430_REV_ES3_1:
	612	case OMAP3430_REV_ES3_1_2:
	613	case OMAP3630_REV_ES1_1:
	614	case OMAP3630_REV_ES1_2:
	615	pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
	616	break;
	617	default:
	618	WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
	619	}
	620	}
8179488a	621
129c65ee	622	pwrdm_complete_init();
6e01478a	623	}