Commit | Line | Data |
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ad67ef68 | 1 | /* |
a64bb9cd | 2 | * OMAP2/3/4 powerdomain control |
ad67ef68 | 3 | * |
72e06d08 | 4 | * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. |
694606c4 | 5 | * Copyright (C) 2007-2011 Nokia Corporation |
ad67ef68 | 6 | * |
72e06d08 | 7 | * Paul Walmsley |
ad67ef68 PW |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
6e01478a PW |
12 | * |
13 | * XXX This should be moved to the mach-omap2/ directory at the earliest | |
14 | * opportunity. | |
ad67ef68 PW |
15 | */ |
16 | ||
72e06d08 PW |
17 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H |
18 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H | |
ad67ef68 PW |
19 | |
20 | #include <linux/types.h> | |
21 | #include <linux/list.h> | |
3a090284 | 22 | #include <linux/spinlock.h> |
ad67ef68 | 23 | |
8f1bec24 KH |
24 | #include "voltage.h" |
25 | ||
ad67ef68 PW |
26 | /* Powerdomain basic power states */ |
27 | #define PWRDM_POWER_OFF 0x0 | |
28 | #define PWRDM_POWER_RET 0x1 | |
29 | #define PWRDM_POWER_INACTIVE 0x2 | |
30 | #define PWRDM_POWER_ON 0x3 | |
31 | ||
2354eb5a PW |
32 | #define PWRDM_MAX_PWRSTS 4 |
33 | ||
ad67ef68 | 34 | /* Powerdomain allowable state bitfields */ |
d3353e16 | 35 | #define PWRSTS_ON (1 << PWRDM_POWER_ON) |
694606c4 PW |
36 | #define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE) |
37 | #define PWRSTS_RET (1 << PWRDM_POWER_RET) | |
bb722f33 | 38 | #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) |
ad67ef68 | 39 | |
694606c4 PW |
40 | #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) |
41 | #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) | |
42 | #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) | |
43 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) | |
ad67ef68 PW |
44 | |
45 | ||
562e54d1 PW |
46 | /* |
47 | * Powerdomain flags (struct powerdomain.flags) | |
48 | * | |
49 | * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support | |
50 | * | |
51 | * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM | |
52 | * bank 1 position. This is true for OMAP3430 | |
53 | * | |
54 | * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state | |
55 | * to a lower sleep state without waking up the powerdomain | |
56 | */ | |
57 | #define PWRDM_HAS_HDWR_SAR BIT(0) | |
58 | #define PWRDM_HAS_MPU_QUIRK BIT(1) | |
59 | #define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2) | |
0b7cbfb5 | 60 | |
ad67ef68 | 61 | /* |
38900c27 AP |
62 | * Number of memory banks that are power-controllable. On OMAP4430, the |
63 | * maximum is 5. | |
ad67ef68 | 64 | */ |
38900c27 | 65 | #define PWRDM_MAX_MEM_BANKS 5 |
ad67ef68 | 66 | |
8420bb13 PW |
67 | /* |
68 | * Maximum number of clockdomains that can be associated with a powerdomain. | |
3f0ea764 | 69 | * PER powerdomain on AM33XX is the worst case |
8420bb13 | 70 | */ |
3f0ea764 | 71 | #define PWRDM_MAX_CLKDMS 11 |
8420bb13 | 72 | |
ad67ef68 PW |
73 | /* XXX A completely arbitrary number. What is reasonable here? */ |
74 | #define PWRDM_TRANSITION_BAILOUT 100000 | |
75 | ||
8420bb13 | 76 | struct clockdomain; |
ad67ef68 PW |
77 | struct powerdomain; |
78 | ||
f0271d65 PW |
79 | /** |
80 | * struct powerdomain - OMAP powerdomain | |
81 | * @name: Powerdomain name | |
8f1bec24 | 82 | * @voltdm: voltagedomain containing this powerdomain |
f0271d65 | 83 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE |
a64bb9cd | 84 | * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs |
f0271d65 PW |
85 | * @pwrsts: Possible powerdomain power states |
86 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION | |
87 | * @flags: Powerdomain flags | |
88 | * @banks: Number of software-controllable memory banks in this powerdomain | |
89 | * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION | |
90 | * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON | |
91 | * @pwrdm_clkdms: Clockdomains in this powerdomain | |
92 | * @node: list_head linking all powerdomains | |
e69c22b1 | 93 | * @voltdm_node: list_head linking all powerdomains in a voltagedomain |
3f0ea764 VH |
94 | * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs |
95 | * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs | |
96 | * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield | |
97 | * in @pwrstctrl_offs | |
98 | * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs | |
99 | * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs | |
100 | * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs | |
101 | * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield | |
102 | * in @pwrstctrl_offs | |
f0271d65 PW |
103 | * @state: |
104 | * @state_counter: | |
105 | * @timer: | |
106 | * @state_timer: | |
3a090284 PW |
107 | * @_lock: spinlock used to serialize powerdomain and some clockdomain ops |
108 | * @_lock_flags: stored flags when @_lock is taken | |
a64bb9cd PW |
109 | * |
110 | * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. | |
f0271d65 | 111 | */ |
ad67ef68 | 112 | struct powerdomain { |
ad67ef68 | 113 | const char *name; |
8f1bec24 KH |
114 | union { |
115 | const char *name; | |
116 | struct voltagedomain *ptr; | |
117 | } voltdm; | |
e0594b44 | 118 | const s16 prcm_offs; |
ad67ef68 | 119 | const u8 pwrsts; |
ad67ef68 | 120 | const u8 pwrsts_logic_ret; |
0b7cbfb5 | 121 | const u8 flags; |
ad67ef68 | 122 | const u8 banks; |
ad67ef68 | 123 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
ad67ef68 | 124 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
a64bb9cd | 125 | const u8 prcm_partition; |
8420bb13 | 126 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
ad67ef68 | 127 | struct list_head node; |
e69c22b1 | 128 | struct list_head voltdm_node; |
ba20bb12 | 129 | int state; |
2354eb5a | 130 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
cde08f81 TG |
131 | unsigned ret_logic_off_counter; |
132 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | |
3a090284 PW |
133 | spinlock_t _lock; |
134 | unsigned long _lock_flags; | |
3f0ea764 VH |
135 | const u8 pwrstctrl_offs; |
136 | const u8 pwrstst_offs; | |
137 | const u32 logicretstate_mask; | |
138 | const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; | |
139 | const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; | |
140 | const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; | |
141 | const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; | |
142 | ||
331b93f4 PDS |
143 | #ifdef CONFIG_PM_DEBUG |
144 | s64 timer; | |
2354eb5a | 145 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
331b93f4 | 146 | #endif |
ad67ef68 PW |
147 | }; |
148 | ||
3b1e8b21 | 149 | /** |
25985edc | 150 | * struct pwrdm_ops - Arch specific function implementations |
3b1e8b21 RN |
151 | * @pwrdm_set_next_pwrst: Set the target power state for a pd |
152 | * @pwrdm_read_next_pwrst: Read the target power state set for a pd | |
153 | * @pwrdm_read_pwrst: Read the current power state of a pd | |
154 | * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd | |
155 | * @pwrdm_set_logic_retst: Set the logic state in RET for a pd | |
156 | * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd | |
157 | * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd | |
158 | * @pwrdm_read_logic_pwrst: Read the current logic state of a pd | |
159 | * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd | |
160 | * @pwrdm_read_logic_retst: Read the logic state in RET for a pd | |
161 | * @pwrdm_read_mem_pwrst: Read the current memory state of a pd | |
162 | * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd | |
163 | * @pwrdm_read_mem_retst: Read the memory state in RET for a pd | |
164 | * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd | |
165 | * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd | |
166 | * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd | |
167 | * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep | |
168 | * @pwrdm_wait_transition: Wait for a pd state transition to complete | |
cd8abed1 | 169 | * @pwrdm_has_voltdm: Check if a voltdm association is needed |
c4978fba PW |
170 | * |
171 | * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family | |
172 | * chips, a powerdomain's power state is not allowed to directly | |
173 | * transition from one low-power state (e.g., CSWR) to another | |
174 | * low-power state (e.g., OFF) without first waking up the | |
175 | * powerdomain. This wastes energy. So OMAP4 chips support the | |
176 | * ability to transition a powerdomain power state directly from one | |
177 | * low-power state to another. The function pointed to by | |
178 | * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4 | |
179 | * hardware powerdomain state machine to enable this feature. | |
3b1e8b21 RN |
180 | */ |
181 | struct pwrdm_ops { | |
182 | int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); | |
183 | int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); | |
184 | int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); | |
185 | int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); | |
186 | int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); | |
187 | int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
188 | int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
189 | int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); | |
190 | int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); | |
191 | int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); | |
192 | int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | |
193 | int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | |
194 | int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); | |
195 | int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); | |
196 | int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); | |
197 | int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); | |
198 | int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); | |
199 | int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); | |
cd8abed1 | 200 | int (*pwrdm_has_voltdm)(void); |
3b1e8b21 | 201 | }; |
ad67ef68 | 202 | |
129c65ee PW |
203 | int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); |
204 | int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list); | |
205 | int pwrdm_complete_init(void); | |
ad67ef68 | 206 | |
ad67ef68 PW |
207 | struct powerdomain *pwrdm_lookup(const char *name); |
208 | ||
a23456e9 PDS |
209 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
210 | void *user); | |
ee894b18 AB |
211 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), |
212 | void *user); | |
ad67ef68 | 213 | |
8420bb13 PW |
214 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
215 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); | |
216 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |
217 | int (*fn)(struct powerdomain *pwrdm, | |
218 | struct clockdomain *clkdm)); | |
048a7034 | 219 | struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); |
8420bb13 | 220 | |
ad67ef68 PW |
221 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); |
222 | ||
223 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | |
224 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | |
fecb494b | 225 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); |
ad67ef68 PW |
226 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
227 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | |
228 | ||
229 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); | |
230 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
231 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
232 | ||
233 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | |
234 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | |
1e3d0d2b | 235 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); |
ad67ef68 PW |
236 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
237 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | |
1e3d0d2b | 238 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); |
ad67ef68 | 239 | |
0b7cbfb5 PW |
240 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
241 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | |
242 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); | |
243 | ||
3a090284 | 244 | int pwrdm_state_switch_nolock(struct powerdomain *pwrdm); |
ba20bb12 | 245 | int pwrdm_state_switch(struct powerdomain *pwrdm); |
e0555489 KH |
246 | int pwrdm_pre_transition(struct powerdomain *pwrdm); |
247 | int pwrdm_post_transition(struct powerdomain *pwrdm); | |
fc013873 | 248 | int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); |
694606c4 | 249 | bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); |
ba20bb12 | 250 | |
c4978fba PW |
251 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state); |
252 | ||
8179488a PW |
253 | extern void omap242x_powerdomains_init(void); |
254 | extern void omap243x_powerdomains_init(void); | |
6e01478a | 255 | extern void omap3xxx_powerdomains_init(void); |
3f0ea764 | 256 | extern void am33xx_powerdomains_init(void); |
6e01478a | 257 | extern void omap44xx_powerdomains_init(void); |
411f968f | 258 | extern void omap54xx_powerdomains_init(void); |
97dd16b1 | 259 | extern void dra7xx_powerdomains_init(void); |
eadc62fc | 260 | void am43xx_powerdomains_init(void); |
6e01478a | 261 | |
72e06d08 PW |
262 | extern struct pwrdm_ops omap2_pwrdm_operations; |
263 | extern struct pwrdm_ops omap3_pwrdm_operations; | |
3f0ea764 | 264 | extern struct pwrdm_ops am33xx_pwrdm_operations; |
72e06d08 PW |
265 | extern struct pwrdm_ops omap4_pwrdm_operations; |
266 | ||
267 | /* Common Internal functions used across OMAP rev's */ | |
268 | extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); | |
269 | extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); | |
270 | extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); | |
271 | ||
272 | extern struct powerdomain wkup_omap2_pwrdm; | |
273 | extern struct powerdomain gfx_omap2_pwrdm; | |
274 | ||
3a090284 PW |
275 | extern void pwrdm_lock(struct powerdomain *pwrdm); |
276 | extern void pwrdm_unlock(struct powerdomain *pwrdm); | |
72e06d08 | 277 | |
ad67ef68 | 278 | #endif |