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Fix common misspellings
[linux-block.git] / arch / arm / mach-omap2 / powerdomain.h
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ad67ef68 1/*
a64bb9cd 2 * OMAP2/3/4 powerdomain control
ad67ef68 3 *
72e06d08 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 5 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 6 *
72e06d08 7 * Paul Walmsley
ad67ef68
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
72e06d08
PW		 17#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
22
72e06d08 23#include <linux/atomic.h>
ad67ef68 24
ce491cf8 25#include <plat/cpu.h>
ad67ef68 26
ad67ef68
PW		 27/* Powerdomain basic power states */
28#define PWRDM_POWER_OFF 0x0
29#define PWRDM_POWER_RET 0x1
30#define PWRDM_POWER_INACTIVE 0x2
31#define PWRDM_POWER_ON 0x3
32
2354eb5a
PW		 33#define PWRDM_MAX_PWRSTS 4
34
ad67ef68 35/* Powerdomain allowable state bitfields */
d3353e16 36#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 37#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
38#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 39#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 40
694606c4
PW		 41#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
42#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
ad67ef68
PW		 45
46
0b7cbfb5
PW		 47/* Powerdomain flags */
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
3863c74b
TG		 49#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
50 * in MEM bank 1 position. This is
51 * true for OMAP3430
52 */
90dbc7b0
RN		 53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
0b7cbfb5 59
ad67ef68 60/*
38900c27
AP		 61 * Number of memory banks that are power-controllable. On OMAP4430, the
62 * maximum is 5.
ad67ef68 63 */
38900c27 64#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 65
8420bb13
PW		 66/*
67 * Maximum number of clockdomains that can be associated with a powerdomain.
38900c27 68 * CORE powerdomain on OMAP4 is the worst case
8420bb13 69 */
38900c27 70#define PWRDM_MAX_CLKDMS 9
8420bb13 71
ad67ef68
PW		 72/* XXX A completely arbitrary number. What is reasonable here? */
73#define PWRDM_TRANSITION_BAILOUT 100000
74
8420bb13 75struct clockdomain;
ad67ef68
PW		 76struct powerdomain;
77
f0271d65
PW		 78/**
79 * struct powerdomain - OMAP powerdomain
80 * @name: Powerdomain name
81 * @omap_chip: represents the OMAP chip types containing this pwrdm
82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 83 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 84 * @pwrsts: Possible powerdomain power states
85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
86 * @flags: Powerdomain flags
87 * @banks: Number of software-controllable memory banks in this powerdomain
88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
90 * @pwrdm_clkdms: Clockdomains in this powerdomain
91 * @node: list_head linking all powerdomains
92 * @state:
93 * @state_counter:
94 * @timer:
95 * @state_timer:
a64bb9cd
PW		 96 *
97 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 98 */
ad67ef68 99struct powerdomain {
ad67ef68 100 const char *name;
ad67ef68 101 const struct omap_chip_id omap_chip;
e0594b44 102 const s16 prcm_offs;
ad67ef68 103 const u8 pwrsts;
ad67ef68 104 const u8 pwrsts_logic_ret;
0b7cbfb5 105 const u8 flags;
ad67ef68 106 const u8 banks;
ad67ef68 107 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 108 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 109 const u8 prcm_partition;
8420bb13 110 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 111 struct list_head node;
ba20bb12 112 int state;
2354eb5a 113 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 114 unsigned ret_logic_off_counter;
115 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
331b93f4
PDS		 116
117#ifdef CONFIG_PM_DEBUG
118 s64 timer;
2354eb5a 119 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 120#endif
ad67ef68
PW		 121};
122
3b1e8b21 123/**
25985edc 124 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 125 * @pwrdm_set_next_pwrst: Set the target power state for a pd
126 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
127 * @pwrdm_read_pwrst: Read the current power state of a pd
128 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
129 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
130 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
131 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
132 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
133 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
134 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
135 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
136 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
137 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
138 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
139 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
140 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
141 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
142 * @pwrdm_wait_transition: Wait for a pd state transition to complete
143 */
144struct pwrdm_ops {
145 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
146 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
147 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
148 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
149 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
150 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
151 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
152 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
153 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
154 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
155 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
156 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
157 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
158 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
159 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
160 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
161 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
162 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
163};
ad67ef68 164
3b1e8b21 165void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
ad67ef68 166
ad67ef68
PW		 167struct powerdomain *pwrdm_lookup(const char *name);
168
a23456e9
PDS		 169int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
170 void *user);
ee894b18
AB		 171int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
172 void *user);
ad67ef68 173
8420bb13
PW		 174int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
175int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
176int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
177 int (*fn)(struct powerdomain *pwrdm,
178 struct clockdomain *clkdm));
179
ad67ef68
PW		 180int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
181
182int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
183int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 184int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 185int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
186int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
187
188int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
189int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
190int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
191
192int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
193int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 194int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 195int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
196int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 197int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 198
0b7cbfb5
PW		 199int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
200int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
201bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
202
ad67ef68
PW		 203int pwrdm_wait_transition(struct powerdomain *pwrdm);
204
ba20bb12
PDS		 205int pwrdm_state_switch(struct powerdomain *pwrdm);
206int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
207int pwrdm_pre_transition(void);
208int pwrdm_post_transition(void);
04aeae77 209int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
7f595674 210u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 211bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 212
6e01478a
PW		 213extern void omap2xxx_powerdomains_init(void);
214extern void omap3xxx_powerdomains_init(void);
215extern void omap44xx_powerdomains_init(void);
216
72e06d08
PW		 217extern struct pwrdm_ops omap2_pwrdm_operations;
218extern struct pwrdm_ops omap3_pwrdm_operations;
219extern struct pwrdm_ops omap4_pwrdm_operations;
220
221/* Common Internal functions used across OMAP rev's */
222extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
223extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
224extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
225
226extern struct powerdomain wkup_omap2_pwrdm;
227extern struct powerdomain gfx_omap2_pwrdm;
228
229
ad67ef68 230#endif
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