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Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / arch / arm / mach-omap2 / powerdomain.h
CommitLineData
ad67ef68 1/*
a64bb9cd 2 * OMAP2/3/4 powerdomain control
ad67ef68 3 *
72e06d08 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 5 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 6 *
72e06d08 7 * Paul Walmsley
ad67ef68
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
72e06d08
PW		 17#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
3a090284 22#include <linux/spinlock.h>
ad67ef68 23
ad67ef68
PW		 24/* Powerdomain basic power states */
25#define PWRDM_POWER_OFF 0x0
26#define PWRDM_POWER_RET 0x1
27#define PWRDM_POWER_INACTIVE 0x2
28#define PWRDM_POWER_ON 0x3
29
2354eb5a
PW		 30#define PWRDM_MAX_PWRSTS 4
31
ad67ef68 32/* Powerdomain allowable state bitfields */
d3353e16 33#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 34#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
35#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 36#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 37
694606c4
PW		 38#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
39#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
40#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
41#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
cafc8cb5 42#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
ad67ef68
PW		 43
44
562e54d1
PW		 45/*
46 * Powerdomain flags (struct powerdomain.flags)
47 *
48 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
49 *
50 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
51 * bank 1 position. This is true for OMAP3430
52 *
53 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
54 * to a lower sleep state without waking up the powerdomain
55 */
56#define PWRDM_HAS_HDWR_SAR BIT(0)
57#define PWRDM_HAS_MPU_QUIRK BIT(1)
58#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
0b7cbfb5 59
ad67ef68 60/*
38900c27
AP		 61 * Number of memory banks that are power-controllable. On OMAP4430, the
62 * maximum is 5.
ad67ef68 63 */
38900c27 64#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 65
8420bb13
PW		 66/*
67 * Maximum number of clockdomains that can be associated with a powerdomain.
3f0ea764 68 * PER powerdomain on AM33XX is the worst case
8420bb13 69 */
3f0ea764 70#define PWRDM_MAX_CLKDMS 11
8420bb13 71
ad67ef68
PW		 72/* XXX A completely arbitrary number. What is reasonable here? */
73#define PWRDM_TRANSITION_BAILOUT 100000
74
8420bb13 75struct clockdomain;
ad67ef68 76struct powerdomain;
4794208c 77struct voltagedomain;
ad67ef68 78
f0271d65
PW		 79/**
80 * struct powerdomain - OMAP powerdomain
81 * @name: Powerdomain name
8f1bec24 82 * @voltdm: voltagedomain containing this powerdomain
f0271d65 83 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 84 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 85 * @pwrsts: Possible powerdomain power states
86 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
87 * @flags: Powerdomain flags
88 * @banks: Number of software-controllable memory banks in this powerdomain
89 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
90 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
91 * @pwrdm_clkdms: Clockdomains in this powerdomain
92 * @node: list_head linking all powerdomains
e69c22b1 93 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
3f0ea764
VH		 94 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
95 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
96 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
97 * in @pwrstctrl_offs
98 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
99 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
100 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
101 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
102 * in @pwrstctrl_offs
f0271d65
PW		 103 * @state:
104 * @state_counter:
105 * @timer:
106 * @state_timer:
3a090284
PW		 107 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
108 * @_lock_flags: stored flags when @_lock is taken
a64bb9cd
PW		 109 *
110 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 111 */
ad67ef68 112struct powerdomain {
ad67ef68 113 const char *name;
8f1bec24
KH		 114 union {
115 const char *name;
116 struct voltagedomain *ptr;
117 } voltdm;
e0594b44 118 const s16 prcm_offs;
ad67ef68 119 const u8 pwrsts;
ad67ef68 120 const u8 pwrsts_logic_ret;
0b7cbfb5 121 const u8 flags;
ad67ef68 122 const u8 banks;
ad67ef68 123 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 124 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 125 const u8 prcm_partition;
8420bb13 126 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 127 struct list_head node;
e69c22b1 128 struct list_head voltdm_node;
ba20bb12 129 int state;
2354eb5a 130 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 131 unsigned ret_logic_off_counter;
132 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
3a090284
PW		 133 spinlock_t _lock;
134 unsigned long _lock_flags;
3f0ea764
VH		 135 const u8 pwrstctrl_offs;
136 const u8 pwrstst_offs;
137 const u32 logicretstate_mask;
138 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
139 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
140 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
141 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
142
331b93f4
PDS		 143#ifdef CONFIG_PM_DEBUG
144 s64 timer;
2354eb5a 145 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 146#endif
485995b0 147 u32 context;
ad67ef68
PW		 148};
149
3b1e8b21 150/**
25985edc 151 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 152 * @pwrdm_set_next_pwrst: Set the target power state for a pd
153 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
154 * @pwrdm_read_pwrst: Read the current power state of a pd
155 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
156 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
157 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
158 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
159 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
160 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
161 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
162 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
163 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
164 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
165 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
166 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
167 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
168 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
169 * @pwrdm_wait_transition: Wait for a pd state transition to complete
cd8abed1 170 * @pwrdm_has_voltdm: Check if a voltdm association is needed
c4978fba
PW		 171 *
172 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
173 * chips, a powerdomain's power state is not allowed to directly
174 * transition from one low-power state (e.g., CSWR) to another
175 * low-power state (e.g., OFF) without first waking up the
176 * powerdomain. This wastes energy. So OMAP4 chips support the
177 * ability to transition a powerdomain power state directly from one
178 * low-power state to another. The function pointed to by
179 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
180 * hardware powerdomain state machine to enable this feature.
3b1e8b21
RN		 181 */
182struct pwrdm_ops {
183 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
184 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
185 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
186 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
187 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
188 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
189 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
190 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
191 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
192 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
193 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
194 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
195 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
196 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
197 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
198 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
199 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
200 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
cd8abed1 201 int (*pwrdm_has_voltdm)(void);
485995b0
RD		 202 void (*pwrdm_save_context)(struct powerdomain *pwrdm);
203 void (*pwrdm_restore_context)(struct powerdomain *pwrdm);
3b1e8b21 204};
ad67ef68 205
129c65ee
PW		 206int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
207int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
208int pwrdm_complete_init(void);
ad67ef68 209
ad67ef68
PW		 210struct powerdomain *pwrdm_lookup(const char *name);
211
a23456e9
PDS		 212int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
213 void *user);
ee894b18
AB		 214int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
215 void *user);
ad67ef68 216
8420bb13 217int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
8420bb13 218
ad67ef68
PW		 219int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
220
bd002d7b
NM		 221u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
222 bool is_logic_state, u8 req_state);
223
ad67ef68
PW		 224int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
225int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 226int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 227int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
228int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
229
230int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
231int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
232int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
233
234int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
235int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 236int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 237int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
238int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 239int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 240
0b7cbfb5
PW		 241int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
242int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
243bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
244
3a090284 245int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
ba20bb12 246int pwrdm_state_switch(struct powerdomain *pwrdm);
e0555489
KH		 247int pwrdm_pre_transition(struct powerdomain *pwrdm);
248int pwrdm_post_transition(struct powerdomain *pwrdm);
fc013873 249int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 250bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 251
c4978fba
PW		 252extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
253
8179488a
PW		 254extern void omap242x_powerdomains_init(void);
255extern void omap243x_powerdomains_init(void);
6e01478a 256extern void omap3xxx_powerdomains_init(void);
3f0ea764 257extern void am33xx_powerdomains_init(void);
6e01478a 258extern void omap44xx_powerdomains_init(void);
411f968f 259extern void omap54xx_powerdomains_init(void);
97dd16b1 260extern void dra7xx_powerdomains_init(void);
eadc62fc 261void am43xx_powerdomains_init(void);
6e01478a 262
72e06d08
PW		 263extern struct pwrdm_ops omap2_pwrdm_operations;
264extern struct pwrdm_ops omap3_pwrdm_operations;
3f0ea764 265extern struct pwrdm_ops am33xx_pwrdm_operations;
72e06d08
PW		 266extern struct pwrdm_ops omap4_pwrdm_operations;
267
268/* Common Internal functions used across OMAP rev's */
269extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
270extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
271extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
272
273extern struct powerdomain wkup_omap2_pwrdm;
274extern struct powerdomain gfx_omap2_pwrdm;
275
3a090284
PW		 276extern void pwrdm_lock(struct powerdomain *pwrdm);
277extern void pwrdm_unlock(struct powerdomain *pwrdm);
72e06d08 278
485995b0
RD		 279extern void pwrdms_save_context(void);
280extern void pwrdms_restore_context(void);
281
282extern void pwrdms_lost_power(void);
ad67ef68 283#endif
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