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OMAP4: UART: cleanup special case IRQ handling
[linux-2.6-block.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * Based on pm.c for omap1
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/pm.h>
19#include <linux/suspend.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/err.h>
24#include <linux/gpio.h>
25
26#include <mach/sram.h>
27#include <mach/clockdomain.h>
28#include <mach/powerdomain.h>
29#include <mach/control.h>
4af4016c 30#include <mach/serial.h>
8bd22949
KH		 31
32#include "cm.h"
33#include "cm-regbits-34xx.h"
34#include "prm-regbits-34xx.h"
35
36#include "prm.h"
37#include "pm.h"
38
39struct power_state {
40 struct powerdomain *pwrdm;
41 u32 next_state;
10f90ed2 42#ifdef CONFIG_SUSPEND
8bd22949 43 u32 saved_state;
10f90ed2 44#endif
8bd22949
KH		 45 struct list_head node;
46};
47
48static LIST_HEAD(pwrst_list);
49
50static void (*_omap_sram_idle)(u32 *addr, int save_state);
51
52static struct powerdomain *mpu_pwrdm;
53
54/* PRCM Interrupt Handler for wakeups */
55static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
56{
57 u32 wkst, irqstatus_mpu;
58 u32 fclk, iclk;
59
60 /* WKUP */
61 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
62 if (wkst) {
63 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
64 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
65 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
66 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
67 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
68 while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
69 cpu_relax();
70 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
71 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
72 }
73
74 /* CORE */
75 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
76 if (wkst) {
77 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
78 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
79 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
80 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
81 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
82 while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
83 cpu_relax();
84 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
85 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
86 }
87 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
88 if (wkst) {
89 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
90 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
92 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
93 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
94 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
95 cpu_relax();
96 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
97 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
98 }
99
100 /* PER */
101 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
102 if (wkst) {
103 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
104 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
106 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
107 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
108 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
109 cpu_relax();
110 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
111 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
112 }
113
114 if (omap_rev() > OMAP3430_REV_ES1_0) {
115 /* USBHOST */
116 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
117 if (wkst) {
118 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
119 CM_ICLKEN);
120 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
121 CM_FCLKEN);
122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
123 CM_ICLKEN);
124 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
125 CM_FCLKEN);
126 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
127 PM_WKST);
128 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
129 PM_WKST))
130 cpu_relax();
131 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
132 CM_ICLKEN);
133 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
134 CM_FCLKEN);
135 }
136 }
137
138 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
139 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
140 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
141 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
142
143 while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
144 cpu_relax();
145
146 return IRQ_HANDLED;
147}
148
149static void omap_sram_idle(void)
150{
151 /* Variable to tell what needs to be saved and restored
152 * in omap_sram_idle*/
153 /* save_state = 0 => Nothing to save and restored */
154 /* save_state = 1 => Only L1 and logic lost */
155 /* save_state = 2 => Only L2 lost */
156 /* save_state = 3 => L1, L2 and logic lost */
157 int save_state = 0, mpu_next_state;
158
159 if (!_omap_sram_idle)
160 return;
161
162 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
163 switch (mpu_next_state) {
164 case PWRDM_POWER_RET:
165 /* No need to save context */
166 save_state = 0;
167 break;
168 default:
169 /* Invalid state */
170 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
171 return;
172 }
173 omap2_gpio_prepare_for_retention();
4af4016c
KH		 174 omap_uart_prepare_idle(0);
175 omap_uart_prepare_idle(1);
176 omap_uart_prepare_idle(2);
8bd22949
KH		 177
178 _omap_sram_idle(NULL, save_state);
179 cpu_init();
180
4af4016c
KH		 181 omap_uart_resume_idle(2);
182 omap_uart_resume_idle(1);
183 omap_uart_resume_idle(0);
8bd22949
KH		 184 omap2_gpio_resume_after_retention();
185}
186
187/*
188 * Check if functional clocks are enabled before entering
189 * sleep. This function could be behind CONFIG_PM_DEBUG
190 * when all drivers are configuring their sysconfig registers
191 * properly and using their clocks properly.
192 */
193static int omap3_fclks_active(void)
194{
195 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
196 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
197
198 fck_core1 = cm_read_mod_reg(CORE_MOD,
199 CM_FCLKEN1);
200 if (omap_rev() > OMAP3430_REV_ES1_0) {
201 fck_core3 = cm_read_mod_reg(CORE_MOD,
202 OMAP3430ES2_CM_FCLKEN3);
203 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
204 CM_FCLKEN);
205 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
206 CM_FCLKEN);
207 } else
208 fck_sgx = cm_read_mod_reg(GFX_MOD,
209 OMAP3430ES2_CM_FCLKEN3);
210 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
211 CM_FCLKEN);
212 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
213 CM_FCLKEN);
214 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
215 CM_FCLKEN);
4af4016c
KH		 216
217 /* Ignore UART clocks. These are handled by UART core (serial.c) */
218 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
219 fck_per &= ~OMAP3430_EN_UART3;
220
8bd22949
KH		 221 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
222 fck_cam | fck_per | fck_usbhost)
223 return 1;
224 return 0;
225}
226
227static int omap3_can_sleep(void)
228{
4af4016c
KH		 229 if (!omap_uart_can_sleep())
230 return 0;
8bd22949
KH		 231 if (omap3_fclks_active())
232 return 0;
233 return 1;
234}
235
236/* This sets pwrdm state (other than mpu & core. Currently only ON &
237 * RET are supported. Function is assuming that clkdm doesn't have
238 * hw_sup mode enabled. */
239static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
240{
241 u32 cur_state;
242 int sleep_switch = 0;
243 int ret = 0;
244
245 if (pwrdm == NULL || IS_ERR(pwrdm))
246 return -EINVAL;
247
248 while (!(pwrdm->pwrsts & (1 << state))) {
249 if (state == PWRDM_POWER_OFF)
250 return ret;
251 state--;
252 }
253
254 cur_state = pwrdm_read_next_pwrst(pwrdm);
255 if (cur_state == state)
256 return ret;
257
258 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
259 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
260 sleep_switch = 1;
261 pwrdm_wait_transition(pwrdm);
262 }
263
264 ret = pwrdm_set_next_pwrst(pwrdm, state);
265 if (ret) {
266 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
267 pwrdm->name);
268 goto err;
269 }
270
271 if (sleep_switch) {
272 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
273 pwrdm_wait_transition(pwrdm);
274 }
275
276err:
277 return ret;
278}
279
280static void omap3_pm_idle(void)
281{
282 local_irq_disable();
283 local_fiq_disable();
284
285 if (!omap3_can_sleep())
286 goto out;
287
288 if (omap_irq_pending())
289 goto out;
290
291 omap_sram_idle();
292
293out:
294 local_fiq_enable();
295 local_irq_enable();
296}
297
10f90ed2 298#ifdef CONFIG_SUSPEND
8bd22949
KH		 299static int omap3_pm_prepare(void)
300{
301 disable_hlt();
302 return 0;
303}
304
305static int omap3_pm_suspend(void)
306{
307 struct power_state *pwrst;
308 int state, ret = 0;
309
310 /* Read current next_pwrsts */
311 list_for_each_entry(pwrst, &pwrst_list, node)
312 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
313 /* Set ones wanted by suspend */
314 list_for_each_entry(pwrst, &pwrst_list, node) {
315 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
316 goto restore;
317 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
318 goto restore;
319 }
320
4af4016c 321 omap_uart_prepare_suspend();
8bd22949
KH		 322 omap_sram_idle();
323
324restore:
325 /* Restore next_pwrsts */
326 list_for_each_entry(pwrst, &pwrst_list, node) {
327 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
328 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
329 if (state > pwrst->next_state) {
330 printk(KERN_INFO "Powerdomain (%s) didn't enter "
331 "target state %d\n",
332 pwrst->pwrdm->name, pwrst->next_state);
333 ret = -1;
334 }
335 }
336 if (ret)
337 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
338 else
339 printk(KERN_INFO "Successfully put all powerdomains "
340 "to target state\n");
341
342 return ret;
343}
344
345static int omap3_pm_enter(suspend_state_t state)
346{
347 int ret = 0;
348
349 switch (state) {
350 case PM_SUSPEND_STANDBY:
351 case PM_SUSPEND_MEM:
352 ret = omap3_pm_suspend();
353 break;
354 default:
355 ret = -EINVAL;
356 }
357
358 return ret;
359}
360
361static void omap3_pm_finish(void)
362{
363 enable_hlt();
364}
365
366static struct platform_suspend_ops omap_pm_ops = {
367 .prepare = omap3_pm_prepare,
368 .enter = omap3_pm_enter,
369 .finish = omap3_pm_finish,
370 .valid = suspend_valid_only_mem,
371};
10f90ed2 372#endif /* CONFIG_SUSPEND */
8bd22949 373
1155e426
KH		 374
375/**
376 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
377 * retention
378 *
379 * In cases where IVA2 is activated by bootcode, it may prevent
380 * full-chip retention or off-mode because it is not idle. This
381 * function forces the IVA2 into idle state so it can go
382 * into retention/off and thus allow full-chip retention/off.
383 *
384 **/
385static void __init omap3_iva_idle(void)
386{
387 /* ensure IVA2 clock is disabled */
388 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
389
390 /* if no clock activity, nothing else to do */
391 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
392 OMAP3430_CLKACTIVITY_IVA2_MASK))
393 return;
394
395 /* Reset IVA2 */
396 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
397 OMAP3430_RST2_IVA2 |
398 OMAP3430_RST3_IVA2,
399 OMAP3430_IVA2_MOD, RM_RSTCTRL);
400
401 /* Enable IVA2 clock */
402 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
403 OMAP3430_IVA2_MOD, CM_FCLKEN);
404
405 /* Set IVA2 boot mode to 'idle' */
406 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
407 OMAP343X_CONTROL_IVA2_BOOTMOD);
408
409 /* Un-reset IVA2 */
410 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
411
412 /* Disable IVA2 clock */
413 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
414
415 /* Reset IVA2 */
416 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
417 OMAP3430_RST2_IVA2 |
418 OMAP3430_RST3_IVA2,
419 OMAP3430_IVA2_MOD, RM_RSTCTRL);
420}
421
8111b221 422static void __init omap3_d2d_idle(void)
8bd22949 423{
8111b221
KH		 424 u16 mask, padconf;
425
426 /* In a stand alone OMAP3430 where there is not a stacked
427 * modem for the D2D Idle Ack and D2D MStandby must be pulled
428 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
429 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
430 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
431 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
432 padconf |= mask;
433 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
434
435 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
436 padconf |= mask;
437 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
438
8bd22949
KH		 439 /* reset modem */
440 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
441 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
442 CORE_MOD, RM_RSTCTRL);
443 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221 444}
8bd22949 445
8111b221
KH		 446static void __init prcm_setup_regs(void)
447{
8bd22949
KH		 448 /* XXX Reset all wkdeps. This should be done when initializing
449 * powerdomains */
450 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
451 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
452 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
453 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
454 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
455 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
456 if (omap_rev() > OMAP3430_REV_ES1_0) {
457 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
458 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
459 } else
460 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
461
462 /*
463 * Enable interface clock autoidle for all modules.
464 * Note that in the long run this should be done by clockfw
465 */
466 cm_write_mod_reg(
8111b221 467 OMAP3430_AUTO_MODEM |
8bd22949
KH		 468 OMAP3430ES2_AUTO_MMC3 |
469 OMAP3430ES2_AUTO_ICR |
470 OMAP3430_AUTO_AES2 |
471 OMAP3430_AUTO_SHA12 |
472 OMAP3430_AUTO_DES2 |
473 OMAP3430_AUTO_MMC2 |
474 OMAP3430_AUTO_MMC1 |
475 OMAP3430_AUTO_MSPRO |
476 OMAP3430_AUTO_HDQ |
477 OMAP3430_AUTO_MCSPI4 |
478 OMAP3430_AUTO_MCSPI3 |
479 OMAP3430_AUTO_MCSPI2 |
480 OMAP3430_AUTO_MCSPI1 |
481 OMAP3430_AUTO_I2C3 |
482 OMAP3430_AUTO_I2C2 |
483 OMAP3430_AUTO_I2C1 |
484 OMAP3430_AUTO_UART2 |
485 OMAP3430_AUTO_UART1 |
486 OMAP3430_AUTO_GPT11 |
487 OMAP3430_AUTO_GPT10 |
488 OMAP3430_AUTO_MCBSP5 |
489 OMAP3430_AUTO_MCBSP1 |
490 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
491 OMAP3430_AUTO_MAILBOXES |
492 OMAP3430_AUTO_OMAPCTRL |
493 OMAP3430ES1_AUTO_FSHOSTUSB |
494 OMAP3430_AUTO_HSOTGUSB |
8111b221 495 OMAP3430_AUTO_SAD2D |
8bd22949
KH		 496 OMAP3430_AUTO_SSI,
497 CORE_MOD, CM_AUTOIDLE1);
498
499 cm_write_mod_reg(
500 OMAP3430_AUTO_PKA |
501 OMAP3430_AUTO_AES1 |
502 OMAP3430_AUTO_RNG |
503 OMAP3430_AUTO_SHA11 |
504 OMAP3430_AUTO_DES1,
505 CORE_MOD, CM_AUTOIDLE2);
506
507 if (omap_rev() > OMAP3430_REV_ES1_0) {
508 cm_write_mod_reg(
8111b221 509 OMAP3430_AUTO_MAD2D |
8bd22949
KH		 510 OMAP3430ES2_AUTO_USBTLL,
511 CORE_MOD, CM_AUTOIDLE3);
512 }
513
514 cm_write_mod_reg(
515 OMAP3430_AUTO_WDT2 |
516 OMAP3430_AUTO_WDT1 |
517 OMAP3430_AUTO_GPIO1 |
518 OMAP3430_AUTO_32KSYNC |
519 OMAP3430_AUTO_GPT12 |
520 OMAP3430_AUTO_GPT1 ,
521 WKUP_MOD, CM_AUTOIDLE);
522
523 cm_write_mod_reg(
524 OMAP3430_AUTO_DSS,
525 OMAP3430_DSS_MOD,
526 CM_AUTOIDLE);
527
528 cm_write_mod_reg(
529 OMAP3430_AUTO_CAM,
530 OMAP3430_CAM_MOD,
531 CM_AUTOIDLE);
532
533 cm_write_mod_reg(
534 OMAP3430_AUTO_GPIO6 |
535 OMAP3430_AUTO_GPIO5 |
536 OMAP3430_AUTO_GPIO4 |
537 OMAP3430_AUTO_GPIO3 |
538 OMAP3430_AUTO_GPIO2 |
539 OMAP3430_AUTO_WDT3 |
540 OMAP3430_AUTO_UART3 |
541 OMAP3430_AUTO_GPT9 |
542 OMAP3430_AUTO_GPT8 |
543 OMAP3430_AUTO_GPT7 |
544 OMAP3430_AUTO_GPT6 |
545 OMAP3430_AUTO_GPT5 |
546 OMAP3430_AUTO_GPT4 |
547 OMAP3430_AUTO_GPT3 |
548 OMAP3430_AUTO_GPT2 |
549 OMAP3430_AUTO_MCBSP4 |
550 OMAP3430_AUTO_MCBSP3 |
551 OMAP3430_AUTO_MCBSP2,
552 OMAP3430_PER_MOD,
553 CM_AUTOIDLE);
554
555 if (omap_rev() > OMAP3430_REV_ES1_0) {
556 cm_write_mod_reg(
557 OMAP3430ES2_AUTO_USBHOST,
558 OMAP3430ES2_USBHOST_MOD,
559 CM_AUTOIDLE);
560 }
561
562 /*
563 * Set all plls to autoidle. This is needed until autoidle is
564 * enabled by clockfw
565 */
566 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
567 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
568 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
569 MPU_MOD,
570 CM_AUTOIDLE2);
571 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
572 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
573 PLL_MOD,
574 CM_AUTOIDLE);
575 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
576 PLL_MOD,
577 CM_AUTOIDLE2);
578
579 /*
580 * Enable control of expternal oscillator through
581 * sys_clkreq. In the long run clock framework should
582 * take care of this.
583 */
584 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
585 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
586 OMAP3430_GR_MOD,
587 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
588
589 /* setup wakup source */
590 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
591 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
592 WKUP_MOD, PM_WKEN);
593 /* No need to write EN_IO, that is always enabled */
594 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
595 OMAP3430_EN_GPT12,
596 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
597 /* For some reason IO doesn't generate wakeup event even if
598 * it is selected to mpu wakeup goup */
599 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
600 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426 601
d3fd3290
KH		 602 /* Don't attach IVA interrupts */
603 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
604 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
605 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
606 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
607
b1340d17
KH		 608 /* Clear any pending 'reset' flags */
609 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
610 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
611 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
612 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
613 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
614 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
615 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
616
014c46db
KH		 617 /* Clear any pending PRCM interrupts */
618 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
619
040fed05
KH		 620 /* Don't attach IVA interrupts */
621 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
622 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
623 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
624 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
625
3a07ae30
KH		 626 /* Clear any pending 'reset' flags */
627 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
628 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
629 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
630 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
631 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
632 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
633 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
634
3a6667ac
KH		 635 /* Clear any pending PRCM interrupts */
636 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
637
1155e426 638 omap3_iva_idle();
8111b221 639 omap3_d2d_idle();
8bd22949
KH		 640}
641
642static int __init pwrdms_setup(struct powerdomain *pwrdm)
643{
644 struct power_state *pwrst;
645
646 if (!pwrdm->pwrsts)
647 return 0;
648
649 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
650 if (!pwrst)
651 return -ENOMEM;
652 pwrst->pwrdm = pwrdm;
653 pwrst->next_state = PWRDM_POWER_RET;
654 list_add(&pwrst->node, &pwrst_list);
655
656 if (pwrdm_has_hdwr_sar(pwrdm))
657 pwrdm_enable_hdwr_sar(pwrdm);
658
659 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
660}
661
662/*
663 * Enable hw supervised mode for all clockdomains if it's
664 * supported. Initiate sleep transition for other clockdomains, if
665 * they are not used
666 */
667static int __init clkdms_setup(struct clockdomain *clkdm)
668{
669 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
670 omap2_clkdm_allow_idle(clkdm);
671 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
672 atomic_read(&clkdm->usecount) == 0)
673 omap2_clkdm_sleep(clkdm);
674 return 0;
675}
676
7cc515f7 677static int __init omap3_pm_init(void)
8bd22949
KH		 678{
679 struct power_state *pwrst, *tmp;
680 int ret;
681
682 if (!cpu_is_omap34xx())
683 return -ENODEV;
684
685 printk(KERN_ERR "Power Management for TI OMAP3.\n");
686
687 /* XXX prcm_setup_regs needs to be before enabling hw
688 * supervised mode for powerdomains */
689 prcm_setup_regs();
690
691 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
692 (irq_handler_t)prcm_interrupt_handler,
693 IRQF_DISABLED, "prcm", NULL);
694 if (ret) {
695 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
696 INT_34XX_PRCM_MPU_IRQ);
697 goto err1;
698 }
699
700 ret = pwrdm_for_each(pwrdms_setup);
701 if (ret) {
702 printk(KERN_ERR "Failed to setup powerdomains\n");
703 goto err2;
704 }
705
706 (void) clkdm_for_each(clkdms_setup);
707
708 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
709 if (mpu_pwrdm == NULL) {
710 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
711 goto err2;
712 }
713
714 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
715 omap34xx_cpu_suspend_sz);
716
10f90ed2 717#ifdef CONFIG_SUSPEND
8bd22949 718 suspend_set_ops(&omap_pm_ops);
10f90ed2 719#endif /* CONFIG_SUSPEND */
8bd22949
KH		 720
721 pm_idle = omap3_pm_idle;
722
723err1:
724 return ret;
725err2:
726 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
727 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
728 list_del(&pwrst->node);
729 kfree(pwrst);
730 }
731 return ret;
732}
733
734late_initcall(omap3_pm_init);
Linux 6.x block layer and io_uring tree(s)