[linux-block.git] / arch / arm / mach-omap2 / pm34xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP3 Power Management Routines
 *
 * Copyright (C) 2006-2008 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 * Jouni Hogander
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap1
 */

#include <linux/cpu_pm.h>
#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/of.h>

#include <trace/events/power.h>

#include <asm/fncpy.h>
#include <asm/suspend.h>
#include <asm/system_misc.h>

#include "clockdomain.h"
#include "powerdomain.h"
#include "soc.h"
#include "common.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "prm3xxx.h"
#include "pm.h"
#include "sdrc.h"
#include "omap-secure.h"
#include "sram.h"
#include "control.h"
#include "vc.h"

/* pm34xx errata defined in pm.h */
u16 pm34xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
#endif
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

void (*omap3_do_wfi_sram)(void);

static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;

static void omap3_core_save_context(void)
{
	omap3_ctrl_save_padconf();

	/*
	 * Force write last pad into memory, as this can fail in some
	 * cases according to errata 1.157, 1.185
	 */
	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);

	/* Save the Interrupt controller context */
	omap_intc_save_context();
	/* Save the system control module context, padconf already save above*/
	omap3_control_save_context();
}

static void omap3_core_restore_context(void)
{
	/* Restore the control module context, padconf restored by h/w */
	omap3_control_restore_context();
	/* Restore the interrupt controller context */
	omap_intc_restore_context();
}

/*
 * FIXME: This function should be called before entering off-mode after
 * OMAP3 secure services have been accessed. Currently it is only called
 * once during boot sequence, but this works as we are not using secure
 * services.
 */
static void omap3_save_secure_ram_context(void)
{
	u32 ret;
	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);

	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		/*
		 * MPU next state must be set to POWER_ON temporarily,
		 * otherwise the WFI executed inside the ROM code
		 * will hang the system.
		 */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
		ret = omap3_save_secure_ram(omap3_secure_ram_storage,
					    OMAP3_SAVE_SECURE_RAM_SZ);
		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
		/* Following is for error tracking, it should not happen */
		if (ret) {
			pr_err("save_secure_sram() returns %08x\n", ret);
			while (1)
				;
		}
	}
}

static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
{
	int c;

	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
				    OMAP3430_ST_IO_CHAIN_MASK);

	return c ? IRQ_HANDLED : IRQ_NONE;
}

static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
{
	int c;

	/*
	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
	 * these are handled in a separate handler to avoid acking
	 * IO events before parsing in mux code
	 */
	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
						   OMAP3430_ST_IO_CHAIN_MASK));
	c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
	c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
		c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
	}

	return c ? IRQ_HANDLED : IRQ_NONE;
}

static void omap34xx_save_context(u32 *save)
{
	u32 val;

	/* Read Auxiliary Control Register */
	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
	*save++ = 1;
	*save++ = val;

	/* Read L2 AUX ctrl register */
	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
	*save++ = 1;
	*save++ = val;
}

static int omap34xx_do_sram_idle(unsigned long save_state)
{
	omap34xx_cpu_suspend(save_state);
	return 0;
}

void omap_sram_idle(void)
{
	/* Variable to tell what needs to be saved and restored
	 * in omap_sram_idle*/
	/* save_state = 0 => Nothing to save and restored */
	/* save_state = 1 => Only L1 and logic lost */
	/* save_state = 2 => Only L2 lost */
	/* save_state = 3 => L1, L2 and logic lost */
	int save_state = 0;
	int mpu_next_state = PWRDM_POWER_ON;
	int per_next_state = PWRDM_POWER_ON;
	int core_next_state = PWRDM_POWER_ON;
	u32 sdrc_pwr = 0;
	int error;

	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
	switch (mpu_next_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_RET:
		/* No need to save context */
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		save_state = 3;
		break;
	default:
		/* Invalid state */
		pr_err("Invalid mpu state in sram_idle\n");
		return;
	}

	/* NEON control */
	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
		pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);

	/* Enable IO-PAD and IO-CHAIN wakeups */
	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);

	pwrdm_pre_transition(NULL);

	/* PER */
	if (per_next_state == PWRDM_POWER_OFF) {
		error = cpu_cluster_pm_enter();
		if (error)
			return;
	}

	/* CORE */
	if (core_next_state < PWRDM_POWER_ON) {
		if (core_next_state == PWRDM_POWER_OFF) {
			omap3_core_save_context();
			omap3_cm_save_context();
		}
	}

	/* Configure PMIC signaling for I2C4 or sys_off_mode */
	omap3_vc_set_pmic_signaling(core_next_state);

	omap3_intc_prepare_idle();

	/*
	 * On EMU/HS devices ROM code restores a SRDC value
	 * from scratchpad which has automatic self refresh on timeout
	 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	 * Hence store/restore the SDRC_POWER register here.
	 */
	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	    core_next_state == PWRDM_POWER_OFF)
		sdrc_pwr = sdrc_read_reg(SDRC_POWER);

	/*
	 * omap3_arm_context is the location where some ARM context
	 * get saved. The rest is placed on the stack, and restored
	 * from there before resuming.
	 */
	if (save_state)
		omap34xx_save_context(omap3_arm_context);
	if (save_state == 1 || save_state == 3)
		cpu_suspend(save_state, omap34xx_do_sram_idle);
	else
		omap34xx_do_sram_idle(save_state);

	/* Restore normal SDRC POWER settings */
	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	    core_next_state == PWRDM_POWER_OFF)
		sdrc_write_reg(sdrc_pwr, SDRC_POWER);

	/* CORE */
	if (core_next_state < PWRDM_POWER_ON &&
	    pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
		omap3_core_restore_context();
		omap3_cm_restore_context();
		omap3_sram_restore_context();
		omap2_sms_restore_context();
	} else {
		/*
		 * In off-mode resume path above, omap3_core_restore_context
		 * also handles the INTC autoidle restore done here so limit
		 * this to non-off mode resume paths so we don't do it twice.
		 */
		omap3_intc_resume_idle();
	}

	pwrdm_post_transition(NULL);

	/* PER */
	if (per_next_state == PWRDM_POWER_OFF)
		cpu_cluster_pm_exit();
}

static void omap3_pm_idle(void)
{
	if (omap_irq_pending())
		return;

	omap_sram_idle();
}

#ifdef CONFIG_SUSPEND
static int omap3_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;

	/* Read current next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node)
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	/* Set ones wanted by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
			goto restore;
		if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
			goto restore;
	}

	omap3_intc_suspend();

	omap_sram_idle();

restore:
	/* Restore next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
	}
	if (ret)
		pr_err("Could not enter target state in pm_suspend\n");
	else
		pr_info("Successfully put all powerdomains to target state\n");

	return ret;
}
#else
#define omap3_pm_suspend NULL
#endif /* CONFIG_SUSPEND */

static void __init prcm_setup_regs(void)
{
	omap3_ctrl_init();

	omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
}

void omap3_pm_off_mode_enable(int enable)
{
	struct power_state *pwrst;
	u32 state;

	if (enable)
		state = PWRDM_POWER_OFF;
	else
		state = PWRDM_POWER_RET;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
				pwrst->pwrdm == core_pwrdm &&
				state == PWRDM_POWER_OFF) {
			pwrst->next_state = PWRDM_POWER_RET;
			pr_warn("%s: Core OFF disabled due to errata i583\n",
				__func__);
		} else {
			pwrst->next_state = state;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
	}
}

int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm)
			return pwrst->next_state;
	}
	return -EINVAL;
}

int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm) {
			pwrst->next_state = state;
			return 0;
		}
	}
	return -EINVAL;
}

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;
	pwrst->pwrdm = pwrdm;

	if (enable_off_mode)
		pwrst->next_state = PWRDM_POWER_OFF;
	else
		pwrst->next_state = PWRDM_POWER_RET;

	list_add(&pwrst->node, &pwrst_list);

	if (pwrdm_has_hdwr_sar(pwrdm))
		pwrdm_enable_hdwr_sar(pwrdm);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/*
 * Push functions to SRAM
 *
 * The minimum set of functions is pushed to SRAM for execution:
 * - omap3_do_wfi for erratum i581 WA,
 */
void omap_push_sram_idle(void)
{
	omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
}

static void __init pm_errata_configure(void)
{
	if (cpu_is_omap3630()) {
		pm34xx_errata |= PM_RTA_ERRATUM_i608;
		/* Enable the l2 cache toggling in sleep logic */
		enable_omap3630_toggle_l2_on_restore();
		if (omap_rev() < OMAP3630_REV_ES1_2)
			pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
					  PM_PER_MEMORIES_ERRATUM_i582);
	} else if (cpu_is_omap34xx()) {
		pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
	}
}

static void __init omap3_pm_check_pmic(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
	if (!np)
		np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");

	if (np) {
		of_node_put(np);
		enable_off_mode = 1;
	} else {
		enable_off_mode = 0;
	}
}

int __init omap3_pm_init(void)
{
	struct power_state *pwrst, *tmp;
	struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
	int ret;

	if (!omap3_has_io_chain_ctrl())
		pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");

	pm_errata_configure();

	/* XXX prcm_setup_regs needs to be before enabling hw
	 * supervised mode for powerdomains */
	prcm_setup_regs();

	ret = request_irq(omap_prcm_event_to_irq("wkup"),
		_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);

	if (ret) {
		pr_err("pm: Failed to request pm_wkup irq\n");
		goto err1;
	}

	/* IO interrupt is shared with mux code */
	ret = request_irq(omap_prcm_event_to_irq("io"),
		_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
		omap3_pm_init);

	if (ret) {
		pr_err("pm: Failed to request pm_io irq\n");
		goto err2;
	}

	omap3_pm_check_pmic();

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains\n");
		goto err3;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (mpu_pwrdm == NULL) {
		pr_err("Failed to get mpu_pwrdm\n");
		ret = -EINVAL;
		goto err3;
	}

	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
	per_pwrdm = pwrdm_lookup("per_pwrdm");
	core_pwrdm = pwrdm_lookup("core_pwrdm");

	neon_clkdm = clkdm_lookup("neon_clkdm");
	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	per_clkdm = clkdm_lookup("per_clkdm");
	wkup_clkdm = clkdm_lookup("wkup_clkdm");

	omap_common_suspend_init(omap3_pm_suspend);

	arm_pm_idle = omap3_pm_idle;
	omap3_idle_init();

	/*
	 * RTA is disabled during initialization as per erratum i608
	 * it is safer to disable RTA by the bootloader, but we would like
	 * to be doubly sure here and prevent any mishaps.
	 */
	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
		omap3630_ctrl_disable_rta();

	/*
	 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
	 * not correctly reset when the PER powerdomain comes back
	 * from OFF or OSWR when the CORE powerdomain is kept active.
	 * See OMAP36xx Erratum i582 "PER Domain reset issue after
	 * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
	 * complete workaround.  The kernel must also prevent the PER
	 * powerdomain from going to OSWR/OFF while the CORE
	 * powerdomain is not going to OSWR/OFF.  And if PER last
	 * power state was off while CORE last power state was ON, the
	 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
	 * self-test using their loopback tests; if that fails, those
	 * devices are unusable until the PER/CORE can complete a transition
	 * from ON to OSWR/OFF and then back to ON.
	 *
	 * XXX Technically this workaround is only needed if off-mode
	 * or OSWR is enabled.
	 */
	if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
		clkdm_add_wkdep(per_clkdm, wkup_clkdm);

	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		omap3_secure_ram_storage =
			kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
		if (!omap3_secure_ram_storage)
			pr_err("Memory allocation failed when allocating for secure sram context\n");

		local_irq_disable();

		omap3_save_secure_ram_context();

		local_irq_enable();
	}

	omap3_save_scratchpad_contents();
	return ret;

err3:
	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
		list_del(&pwrst->node);
		kfree(pwrst);
	}
	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
err2:
	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
err1:
	return ret;
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
8bd22949 KH	2	/*
	3	* OMAP3 Power Management Routines
	4	*
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	* Tony Lindgren <tony@atomide.com>
	7	* Jouni Hogander
	8	*
2f5939c3 RN	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Rajendra Nayak <rnayak@ti.com>
	11	*
8bd22949 KH	12	* Copyright (C) 2005 Texas Instruments, Inc.
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	*
	15	* Based on pm.c for omap1
8bd22949 KH	16	*/
8bd22949 KH	17
b764a586	18	#include <linux/cpu_pm.h>
8bd22949 KH	19	#include <linux/pm.h>
	20	#include <linux/suspend.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/module.h>
	23	#include <linux/list.h>
	24	#include <linux/err.h>
c40552bc	25	#include <linux/clk.h>
dccaad89	26	#include <linux/delay.h>
5a0e3ad6	27	#include <linux/slab.h>
fb2c599f	28	#include <linux/of.h>
4b25408f	29
5e7c58dc	30	#include <trace/events/power.h>
8bd22949	31
bf027ca1	32	#include <asm/fncpy.h>
2c74a0ce	33	#include <asm/suspend.h>
9f97da78	34	#include <asm/system_misc.h>
2c74a0ce	35
1540f214	36	#include "clockdomain.h"
72e06d08	37	#include "powerdomain.h"
e4c060db	38	#include "soc.h"
4e65331c	39	#include "common.h"
ff4ae5d9	40	#include "cm3xxx.h"
8bd22949 KH	41	#include "cm-regbits-34xx.h"
8bd22949 KH	42	#include "prm-regbits-34xx.h"
139563ad	43	#include "prm3xxx.h"
8bd22949	44	#include "pm.h"
13a6fe0f	45	#include "sdrc.h"
d09220a8	46	#include "omap-secure.h"
bf027ca1	47	#include "sram.h"
4814ced5	48	#include "control.h"
3b8c4ebb	49	#include "vc.h"
13a6fe0f	50
8cdfd834 NM	51	/* pm34xx errata defined in pm.h */
	52	u16 pm34xx_errata;
	53
8bd22949 KH	54	struct power_state {
	55	struct powerdomain *pwrdm;
	56	u32 next_state;
10f90ed2	57	#ifdef CONFIG_SUSPEND
8bd22949	58	u32 saved_state;
10f90ed2	59	#endif
8bd22949 KH	60	struct list_head node;
	61	};
	62
	63	static LIST_HEAD(pwrst_list);
	64
46e130d2	65	void (*omap3_do_wfi_sram)(void);
27d59a4a	66
fa3c2a4f RN	67	static struct powerdomain mpu_pwrdm, neon_pwrdm;
fa3c2a4f RN	68	static struct powerdomain core_pwrdm, per_pwrdm;
3a7ec26b	69
2f5939c3 RN	70	static void omap3_core_save_context(void)
2f5939c3 RN	71	{
596efe47	72	omap3_ctrl_save_padconf();
dccaad89 TK	73
	74	/*
	75	* Force write last pad into memory, as this can fail in some
83521291	76	* cases according to errata 1.157, 1.185
dccaad89 TK	77	*/
	78	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
	79	OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
	80
2f5939c3 RN	81	/* Save the Interrupt controller context */
2f5939c3 RN	82	omap_intc_save_context();
2f5939c3 RN	83	/* Save the system control module context, padconf already save above*/
	84	omap3_control_save_context();
	85	}
	86
	87	static void omap3_core_restore_context(void)
	88	{
	89	/* Restore the control module context, padconf restored by h/w */
	90	omap3_control_restore_context();
2f5939c3 RN	91	/* Restore the interrupt controller context */
	92	omap_intc_restore_context();
	93	}
	94
9d97140b TK	95	/*
	96	* FIXME: This function should be called before entering off-mode after
	97	* OMAP3 secure services have been accessed. Currently it is only called
	98	* once during boot sequence, but this works as we are not using secure
	99	* services.
	100	*/
617fcc98	101	static void omap3_save_secure_ram_context(void)
27d59a4a TK	102	{
27d59a4a TK	103	u32 ret;
617fcc98	104	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
27d59a4a TK	105
27d59a4a TK	106	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a TK	107	/*
	108	* MPU next state must be set to POWER_ON temporarily,
	109	* otherwise the WFI executed inside the ROM code
	110	* will hang the system.
	111	*/
	112	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
d09220a8 TL	113	ret = omap3_save_secure_ram(omap3_secure_ram_storage,
d09220a8 TL	114	OMAP3_SAVE_SECURE_RAM_SZ);
617fcc98	115	pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
27d59a4a TK	116	/* Following is for error tracking, it should not happen */
27d59a4a TK	117	if (ret) {
98179856	118	pr_err("save_secure_sram() returns %08x\n", ret);
27d59a4a TK	119	while (1)
	120	;
	121	}
	122	}
	123	}
	124
22f51371	125	static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
8cb0ac99 PW	126	{
	127	int c;
	128
9cb6d363 TK	129	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK \|
9cb6d363 TK	130	OMAP3430_ST_IO_CHAIN_MASK);
8cb0ac99	131
22f51371	132	return c ? IRQ_HANDLED : IRQ_NONE;
77da2d91	133	}
8bd22949	134
22f51371	135	static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
77da2d91	136	{
22f51371	137	int c;
d6290a3e	138
22f51371 TK	139	/*
	140	* Clear all except ST_IO and ST_IO_CHAIN for wkup module,
	141	* these are handled in a separate handler to avoid acking
	142	* IO events before parsing in mux code
	143	*/
9cb6d363 TK	144	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK \|
	145	OMAP3430_ST_IO_CHAIN_MASK));
	146	c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
	147	c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
22f51371	148	if (omap_rev() > OMAP3430_REV_ES1_0) {
9cb6d363 TK	149	c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
9cb6d363 TK	150	c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
22f51371	151	}
8bd22949	152
22f51371	153	return c ? IRQ_HANDLED : IRQ_NONE;
8bd22949 KH	154	}
8bd22949 KH	155
cbe26349 RK	156	static void omap34xx_save_context(u32 *save)
	157	{
	158	u32 val;
	159
	160	/* Read Auxiliary Control Register */
	161	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
	162	*save++ = 1;
	163	*save++ = val;
	164
	165	/* Read L2 AUX ctrl register */
	166	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
	167	*save++ = 1;
	168	*save++ = val;
	169	}
	170
29cb3cd2	171	static int omap34xx_do_sram_idle(unsigned long save_state)
57f277b0	172	{
cbe26349	173	omap34xx_cpu_suspend(save_state);
29cb3cd2	174	return 0;
57f277b0 RN	175	}
57f277b0 RN	176
99e6a4d2	177	void omap_sram_idle(void)
8bd22949 KH	178	{
	179	/* Variable to tell what needs to be saved and restored
	180	* in omap_sram_idle*/
	181	/* save_state = 0 => Nothing to save and restored */
	182	/* save_state = 1 => Only L1 and logic lost */
	183	/* save_state = 2 => Only L2 lost */
	184	/* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f RN	185	int save_state = 0;
	186	int mpu_next_state = PWRDM_POWER_ON;
	187	int per_next_state = PWRDM_POWER_ON;
	188	int core_next_state = PWRDM_POWER_ON;
13a6fe0f	189	u32 sdrc_pwr = 0;
55be2f50	190	int error;
8bd22949	191
8bd22949 KH	192	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
8bd22949 KH	193	switch (mpu_next_state) {
fa3c2a4f	194	case PWRDM_POWER_ON:
8bd22949 KH	195	case PWRDM_POWER_RET:
	196	/* No need to save context */
	197	save_state = 0;
	198	break;
61255ab9 RN	199	case PWRDM_POWER_OFF:
	200	save_state = 3;
	201	break;
8bd22949 KH	202	default:
8bd22949 KH	203	/* Invalid state */
98179856	204	pr_err("Invalid mpu state in sram_idle\n");
8bd22949 KH	205	return;
8bd22949 KH	206	}
fe617af7	207
fa3c2a4f RN	208	/* NEON control */
fa3c2a4f RN	209	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
7139178e	210	pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
fa3c2a4f	211
40742fa8	212	/* Enable IO-PAD and IO-CHAIN wakeups */
658ce97e	213	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0	214	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
40742fa8	215
e0e29fd7	216	pwrdm_pre_transition(NULL);
ff2f8e5f	217
40742fa8	218	/* PER */
55be2f50 TL	219	if (per_next_state == PWRDM_POWER_OFF) {
	220	error = cpu_cluster_pm_enter();
	221	if (error)
	222	return;
	223	}
658ce97e KH	224
658ce97e KH	225	/* CORE */
fa3c2a4f	226	if (core_next_state < PWRDM_POWER_ON) {
2f5939c3 RN	227	if (core_next_state == PWRDM_POWER_OFF) {
2f5939c3 RN	228	omap3_core_save_context();
f0611a5c	229	omap3_cm_save_context();
2f5939c3	230	}
fa3c2a4f	231	}
40742fa8	232
3b8c4ebb TL	233	/* Configure PMIC signaling for I2C4 or sys_off_mode */
	234	omap3_vc_set_pmic_signaling(core_next_state);
	235
f18cc2ff	236	omap3_intc_prepare_idle();
8bd22949	237
13a6fe0f	238	/*
30474544 PW	239	* On EMU/HS devices ROM code restores a SRDC value
	240	* from scratchpad which has automatic self refresh on timeout
	241	* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	242	* Hence store/restore the SDRC_POWER register here.
	243	*/
	244	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	245	(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
	246	omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
f265dc4c	247	core_next_state == PWRDM_POWER_OFF)
13a6fe0f	248	sdrc_pwr = sdrc_read_reg(SDRC_POWER);
13a6fe0f	249
61255ab9	250	/*
076f2cc4 RK	251	* omap3_arm_context is the location where some ARM context
	252	* get saved. The rest is placed on the stack, and restored
	253	* from there before resuming.
61255ab9	254	*/
cbe26349 RK	255	if (save_state)
cbe26349 RK	256	omap34xx_save_context(omap3_arm_context);
076f2cc4	257	if (save_state == 1 \|\| save_state == 3)
2c74a0ce	258	cpu_suspend(save_state, omap34xx_do_sram_idle);
076f2cc4 RK	259	else
076f2cc4 RK	260	omap34xx_do_sram_idle(save_state);
8bd22949	261
f265dc4c	262	/* Restore normal SDRC POWER settings */
30474544 PW	263	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	264	(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
	265	omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
13a6fe0f TK	266	core_next_state == PWRDM_POWER_OFF)
	267	sdrc_write_reg(sdrc_pwr, SDRC_POWER);
	268
658ce97e	269	/* CORE */
1560d158 DG	270	if (core_next_state < PWRDM_POWER_ON &&
	271	pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
	272	omap3_core_restore_context();
	273	omap3_cm_restore_context();
	274	omap3_sram_restore_context();
	275	omap2_sms_restore_context();
	276	} else {
	277	/*
	278	* In off-mode resume path above, omap3_core_restore_context
	279	* also handles the INTC autoidle restore done here so limit
	280	* this to non-off mode resume paths so we don't do it twice.
	281	*/
	282	omap3_intc_resume_idle();
658ce97e KH	283	}
658ce97e KH	284
e0e29fd7 KH	285	pwrdm_post_transition(NULL);
e0e29fd7 KH	286
658ce97e	287	/* PER */
b764a586 TL	288	if (per_next_state == PWRDM_POWER_OFF)
b764a586 TL	289	cpu_cluster_pm_exit();
8bd22949 KH	290	}
8bd22949 KH	291
8bd22949 KH	292	static void omap3_pm_idle(void)
8bd22949 KH	293	{
0bcd24b0	294	if (omap_irq_pending())
6b85638b	295	return;
8bd22949 KH	296
8bd22949 KH	297	omap_sram_idle();
8bd22949 KH	298	}
8bd22949 KH	299
10f90ed2	300	#ifdef CONFIG_SUSPEND
8bd22949 KH	301	static int omap3_pm_suspend(void)
	302	{
	303	struct power_state *pwrst;
	304	int state, ret = 0;
	305
	306	/* Read current next_pwrsts */
	307	list_for_each_entry(pwrst, &pwrst_list, node)
	308	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	309	/* Set ones wanted by suspend */
	310	list_for_each_entry(pwrst, &pwrst_list, node) {
eb6a2c75	311	if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
8bd22949 KH	312	goto restore;
	313	if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
	314	goto restore;
	315	}
	316
2bbe3af3 TK	317	omap3_intc_suspend();
2bbe3af3 TK	318
8bd22949 KH	319	omap_sram_idle();
	320
	321	restore:
	322	/* Restore next_pwrsts */
	323	list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949 KH	324	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
8bd22949 KH	325	if (state > pwrst->next_state) {
7852ec05 PW	326	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	327	pwrst->pwrdm->name, pwrst->next_state);
8bd22949 KH	328	ret = -1;
8bd22949 KH	329	}
eb6a2c75	330	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949 KH	331	}
8bd22949 KH	332	if (ret)
98179856	333	pr_err("Could not enter target state in pm_suspend\n");
8bd22949	334	else
98179856	335	pr_info("Successfully put all powerdomains to target state\n");
8bd22949 KH	336
	337	return ret;
	338	}
2e4b62dc DG	339	#else
2e4b62dc DG	340	#define omap3_pm_suspend NULL
10f90ed2	341	#endif /* CONFIG_SUSPEND */
8bd22949	342
8111b221 KH	343	static void __init prcm_setup_regs(void)
8111b221 KH	344	{
ba12c242	345	omap3_ctrl_init();
b296c811	346
c5180a2b	347	omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
8bd22949 KH	348	}
8bd22949 KH	349
c40552bc KH	350	void omap3_pm_off_mode_enable(int enable)
	351	{
	352	struct power_state *pwrst;
	353	u32 state;
	354
	355	if (enable)
	356	state = PWRDM_POWER_OFF;
	357	else
	358	state = PWRDM_POWER_RET;
	359
	360	list_for_each_entry(pwrst, &pwrst_list, node) {
cc1b6028 EV	361	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
	362	pwrst->pwrdm == core_pwrdm &&
	363	state == PWRDM_POWER_OFF) {
	364	pwrst->next_state = PWRDM_POWER_RET;
e16b41bf	365	pr_warn("%s: Core OFF disabled due to errata i583\n",
cc1b6028 EV	366	__func__);
	367	} else {
	368	pwrst->next_state = state;
	369	}
	370	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
c40552bc KH	371	}
	372	}
	373
68d4778c TK	374	int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
	375	{
	376	struct power_state *pwrst;
	377
	378	list_for_each_entry(pwrst, &pwrst_list, node) {
	379	if (pwrst->pwrdm == pwrdm)
	380	return pwrst->next_state;
	381	}
	382	return -EINVAL;
	383	}
	384
	385	int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
	386	{
	387	struct power_state *pwrst;
	388
	389	list_for_each_entry(pwrst, &pwrst_list, node) {
	390	if (pwrst->pwrdm == pwrdm) {
	391	pwrst->next_state = state;
	392	return 0;
	393	}
	394	}
	395	return -EINVAL;
	396	}
	397
a23456e9	398	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
8bd22949 KH	399	{
	400	struct power_state *pwrst;
	401
	402	if (!pwrdm->pwrsts)
	403	return 0;
	404
d3d381c6	405	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949 KH	406	if (!pwrst)
	407	return -ENOMEM;
	408	pwrst->pwrdm = pwrdm;
fb2c599f AK	409
	410	if (enable_off_mode)
	411	pwrst->next_state = PWRDM_POWER_OFF;
	412	else
	413	pwrst->next_state = PWRDM_POWER_RET;
	414
8bd22949 KH	415	list_add(&pwrst->node, &pwrst_list);
	416
	417	if (pwrdm_has_hdwr_sar(pwrdm))
	418	pwrdm_enable_hdwr_sar(pwrdm);
	419
eb6a2c75	420	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
8bd22949 KH	421	}
8bd22949 KH	422
46e130d2 JP	423	/*
	424	* Push functions to SRAM
	425	*
	426	* The minimum set of functions is pushed to SRAM for execution:
	427	* - omap3_do_wfi for erratum i581 WA,
46e130d2	428	*/
3231fc88 RN	429	void omap_push_sram_idle(void)
3231fc88 RN	430	{
46e130d2	431	omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
3231fc88 RN	432	}
3231fc88 RN	433
8cdfd834 NM	434	static void __init pm_errata_configure(void)
8cdfd834 NM	435	{
c4236d2e	436	if (cpu_is_omap3630()) {
458e999e	437	pm34xx_errata \|= PM_RTA_ERRATUM_i608;
c4236d2e PDS	438	/* Enable the l2 cache toggling in sleep logic */
c4236d2e PDS	439	enable_omap3630_toggle_l2_on_restore();
cc1b6028	440	if (omap_rev() < OMAP3630_REV_ES1_2)
856c3c5b PW	441	pm34xx_errata \|= (PM_SDRC_WAKEUP_ERRATUM_i583 \|
	442	PM_PER_MEMORIES_ERRATUM_i582);
	443	} else if (cpu_is_omap34xx()) {
	444	pm34xx_errata \|= PM_PER_MEMORIES_ERRATUM_i582;
c4236d2e	445	}
8cdfd834 NM	446	}
8cdfd834 NM	447
fb2c599f AK	448	static void __init omap3_pm_check_pmic(void)
	449	{
	450	struct device_node *np;
	451
	452	np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
	453	if (!np)
	454	np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
	455
	456	if (np) {
	457	of_node_put(np);
	458	enable_off_mode = 1;
	459	} else {
	460	enable_off_mode = 0;
	461	}
	462	}
	463
bbd707ac	464	int __init omap3_pm_init(void)
8bd22949 KH	465	{
8bd22949 KH	466	struct power_state pwrst, tmp;
856c3c5b	467	struct clockdomain neon_clkdm, mpu_clkdm, per_clkdm, wkup_clkdm;
8bd22949 KH	468	int ret;
8bd22949 KH	469
b02b9172	470	if (!omap3_has_io_chain_ctrl())
3d0cb73e	471	pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
b02b9172	472
8cdfd834 NM	473	pm_errata_configure();
8cdfd834 NM	474
8bd22949 KH	475	/* XXX prcm_setup_regs needs to be before enabling hw
	476	* supervised mode for powerdomains */
	477	prcm_setup_regs();
	478
22f51371 TK	479	ret = request_irq(omap_prcm_event_to_irq("wkup"),
	480	_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
	481
	482	if (ret) {
	483	pr_err("pm: Failed to request pm_wkup irq\n");
	484	goto err1;
	485	}
	486
	487	/* IO interrupt is shared with mux code */
	488	ret = request_irq(omap_prcm_event_to_irq("io"),
	489	_prcm_int_handle_io, IRQF_SHARED \| IRQF_NO_SUSPEND, "pm_io",
	490	omap3_pm_init);
	491
8bd22949	492	if (ret) {
22f51371	493	pr_err("pm: Failed to request pm_io irq\n");
ce229c5d	494	goto err2;
8bd22949 KH	495	}
8bd22949 KH	496
fb2c599f AK	497	omap3_pm_check_pmic();
fb2c599f AK	498
a23456e9	499	ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949	500	if (ret) {
98179856	501	pr_err("Failed to setup powerdomains\n");
ce229c5d	502	goto err3;
8bd22949 KH	503	}
8bd22949 KH	504
92206fd2	505	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
8bd22949 KH	506
	507	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	508	if (mpu_pwrdm == NULL) {
98179856	509	pr_err("Failed to get mpu_pwrdm\n");
ce229c5d MG	510	ret = -EINVAL;
ce229c5d MG	511	goto err3;
8bd22949 KH	512	}
8bd22949 KH	513
fa3c2a4f RN	514	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
	515	per_pwrdm = pwrdm_lookup("per_pwrdm");
	516	core_pwrdm = pwrdm_lookup("core_pwrdm");
	517
55ed9694 PW	518	neon_clkdm = clkdm_lookup("neon_clkdm");
55ed9694 PW	519	mpu_clkdm = clkdm_lookup("mpu_clkdm");
856c3c5b PW	520	per_clkdm = clkdm_lookup("per_clkdm");
856c3c5b PW	521	wkup_clkdm = clkdm_lookup("wkup_clkdm");
55ed9694	522
2e4b62dc	523	omap_common_suspend_init(omap3_pm_suspend);
8bd22949	524
0bcd24b0	525	arm_pm_idle = omap3_pm_idle;
0343371e	526	omap3_idle_init();
8bd22949	527
458e999e NM	528	/*
	529	* RTA is disabled during initialization as per erratum i608
	530	* it is safer to disable RTA by the bootloader, but we would like
	531	* to be doubly sure here and prevent any mishaps.
	532	*/
	533	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
	534	omap3630_ctrl_disable_rta();
	535
856c3c5b PW	536	/*
	537	* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
	538	* not correctly reset when the PER powerdomain comes back
	539	* from OFF or OSWR when the CORE powerdomain is kept active.
	540	* See OMAP36xx Erratum i582 "PER Domain reset issue after
	541	* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
	542	* complete workaround. The kernel must also prevent the PER
	543	* powerdomain from going to OSWR/OFF while the CORE
	544	* powerdomain is not going to OSWR/OFF. And if PER last
	545	* power state was off while CORE last power state was ON, the
	546	* UART3/4 and McBSP2/3 SIDETONE devices need to run a
	547	* self-test using their loopback tests; if that fails, those
	548	* devices are unusable until the PER/CORE can complete a transition
	549	* from ON to OSWR/OFF and then back to ON.
	550	*
	551	* XXX Technically this workaround is only needed if off-mode
	552	* or OSWR is enabled.
	553	*/
	554	if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
	555	clkdm_add_wkdep(per_clkdm, wkup_clkdm);
	556
55ed9694	557	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
27d59a4a TK	558	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a TK	559	omap3_secure_ram_storage =
d09220a8	560	kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
27d59a4a	561	if (!omap3_secure_ram_storage)
7852ec05	562	pr_err("Memory allocation failed when allocating for secure sram context\n");
9d97140b TK	563
9d97140b TK	564	local_irq_disable();
9d97140b	565
617fcc98	566	omap3_save_secure_ram_context();
9d97140b TK	567
9d97140b TK	568	local_irq_enable();
27d59a4a	569	}
27d59a4a	570
9d97140b	571	omap3_save_scratchpad_contents();
8bd22949	572	return ret;
ce229c5d MG	573
ce229c5d MG	574	err3:
8bd22949 KH	575	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
	576	list_del(&pwrst->node);
	577	kfree(pwrst);
	578	}
ce229c5d MG	579	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
	580	err2:
	581	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
	582	err1:
8bd22949 KH	583	return ret;
8bd22949 KH	584	}