Commit | Line | Data |
---|---|---|
8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
4b25408f TL |
31 | #include <linux/platform_data/gpio-omap.h> |
32 | ||
5e7c58dc | 33 | #include <trace/events/power.h> |
8bd22949 | 34 | |
2c74a0ce | 35 | #include <asm/suspend.h> |
9f97da78 | 36 | #include <asm/system_misc.h> |
2c74a0ce | 37 | |
ce491cf8 | 38 | #include <plat/sram.h> |
1540f214 | 39 | #include "clockdomain.h" |
72e06d08 | 40 | #include "powerdomain.h" |
61255ab9 | 41 | #include <plat/sdrc.h> |
2f5939c3 RN |
42 | #include <plat/prcm.h> |
43 | #include <plat/gpmc.h> | |
f2d11858 | 44 | #include <plat/dma.h> |
8bd22949 | 45 | |
4e65331c | 46 | #include "common.h" |
59fb659b | 47 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
48 | #include "cm-regbits-34xx.h" |
49 | #include "prm-regbits-34xx.h" | |
50 | ||
59fb659b | 51 | #include "prm2xxx_3xxx.h" |
8bd22949 | 52 | #include "pm.h" |
13a6fe0f | 53 | #include "sdrc.h" |
4814ced5 | 54 | #include "control.h" |
13a6fe0f | 55 | |
8cdfd834 NM |
56 | /* pm34xx errata defined in pm.h */ |
57 | u16 pm34xx_errata; | |
58 | ||
8bd22949 KH |
59 | struct power_state { |
60 | struct powerdomain *pwrdm; | |
61 | u32 next_state; | |
10f90ed2 | 62 | #ifdef CONFIG_SUSPEND |
8bd22949 | 63 | u32 saved_state; |
10f90ed2 | 64 | #endif |
8bd22949 KH |
65 | struct list_head node; |
66 | }; | |
67 | ||
68 | static LIST_HEAD(pwrst_list); | |
69 | ||
27d59a4a | 70 | static int (*_omap_save_secure_sram)(u32 *addr); |
46e130d2 | 71 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 72 | |
fa3c2a4f RN |
73 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
74 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
3a7ec26b | 75 | |
2f5939c3 RN |
76 | static void omap3_core_save_context(void) |
77 | { | |
596efe47 | 78 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
79 | |
80 | /* | |
81 | * Force write last pad into memory, as this can fail in some | |
83521291 | 82 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
83 | */ |
84 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
85 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
86 | ||
2f5939c3 RN |
87 | /* Save the Interrupt controller context */ |
88 | omap_intc_save_context(); | |
89 | /* Save the GPMC context */ | |
90 | omap3_gpmc_save_context(); | |
91 | /* Save the system control module context, padconf already save above*/ | |
92 | omap3_control_save_context(); | |
f2d11858 | 93 | omap_dma_global_context_save(); |
2f5939c3 RN |
94 | } |
95 | ||
96 | static void omap3_core_restore_context(void) | |
97 | { | |
98 | /* Restore the control module context, padconf restored by h/w */ | |
99 | omap3_control_restore_context(); | |
100 | /* Restore the GPMC context */ | |
101 | omap3_gpmc_restore_context(); | |
102 | /* Restore the interrupt controller context */ | |
103 | omap_intc_restore_context(); | |
f2d11858 | 104 | omap_dma_global_context_restore(); |
2f5939c3 RN |
105 | } |
106 | ||
9d97140b TK |
107 | /* |
108 | * FIXME: This function should be called before entering off-mode after | |
109 | * OMAP3 secure services have been accessed. Currently it is only called | |
110 | * once during boot sequence, but this works as we are not using secure | |
111 | * services. | |
112 | */ | |
617fcc98 | 113 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
114 | { |
115 | u32 ret; | |
617fcc98 | 116 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
117 | |
118 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
119 | /* |
120 | * MPU next state must be set to POWER_ON temporarily, | |
121 | * otherwise the WFI executed inside the ROM code | |
122 | * will hang the system. | |
123 | */ | |
124 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
125 | ret = _omap_save_secure_sram((u32 *) | |
126 | __pa(omap3_secure_ram_storage)); | |
617fcc98 | 127 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
128 | /* Following is for error tracking, it should not happen */ |
129 | if (ret) { | |
98179856 | 130 | pr_err("save_secure_sram() returns %08x\n", ret); |
27d59a4a TK |
131 | while (1) |
132 | ; | |
133 | } | |
134 | } | |
135 | } | |
136 | ||
77da2d91 JH |
137 | /* |
138 | * PRCM Interrupt Handler Helper Function | |
139 | * | |
140 | * The purpose of this function is to clear any wake-up events latched | |
141 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
142 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
143 | * set another bit in this register. A while loop is used to ensure | |
144 | * that any peripheral wake-up events occurring while attempting to | |
145 | * clear the PM_WKST_x are detected and cleared. | |
146 | */ | |
22f51371 | 147 | static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) |
8bd22949 | 148 | { |
71a80775 | 149 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
150 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
151 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
152 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
153 | u16 grpsel_off = (regs == 3) ? |
154 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 155 | int c = 0; |
8bd22949 | 156 | |
c4d7e58f PW |
157 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
158 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | |
22f51371 | 159 | wkst &= ~ignore_bits; |
8bd22949 | 160 | if (wkst) { |
c4d7e58f PW |
161 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
162 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | |
77da2d91 | 163 | while (wkst) { |
71a80775 | 164 | clken = wkst; |
c4d7e58f | 165 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
71a80775 VP |
166 | /* |
167 | * For USBHOST, we don't know whether HOST1 or | |
168 | * HOST2 woke us up, so enable both f-clocks | |
169 | */ | |
170 | if (module == OMAP3430ES2_USBHOST_MOD) | |
171 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
c4d7e58f PW |
172 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
173 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | |
174 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | |
22f51371 | 175 | wkst &= ~ignore_bits; |
8cb0ac99 | 176 | c++; |
77da2d91 | 177 | } |
c4d7e58f PW |
178 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
179 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 180 | } |
8cb0ac99 PW |
181 | |
182 | return c; | |
183 | } | |
184 | ||
22f51371 | 185 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
8cb0ac99 PW |
186 | { |
187 | int c; | |
188 | ||
22f51371 TK |
189 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, |
190 | ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); | |
8cb0ac99 | 191 | |
22f51371 | 192 | return c ? IRQ_HANDLED : IRQ_NONE; |
77da2d91 | 193 | } |
8bd22949 | 194 | |
22f51371 | 195 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
77da2d91 | 196 | { |
22f51371 | 197 | int c; |
d6290a3e | 198 | |
22f51371 TK |
199 | /* |
200 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, | |
201 | * these are handled in a separate handler to avoid acking | |
202 | * IO events before parsing in mux code | |
203 | */ | |
204 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, | |
205 | OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); | |
206 | c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); | |
207 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | |
208 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
209 | c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); | |
210 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); | |
211 | } | |
8bd22949 | 212 | |
22f51371 | 213 | return c ? IRQ_HANDLED : IRQ_NONE; |
8bd22949 KH |
214 | } |
215 | ||
cbe26349 RK |
216 | static void omap34xx_save_context(u32 *save) |
217 | { | |
218 | u32 val; | |
219 | ||
220 | /* Read Auxiliary Control Register */ | |
221 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
222 | *save++ = 1; | |
223 | *save++ = val; | |
224 | ||
225 | /* Read L2 AUX ctrl register */ | |
226 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
227 | *save++ = 1; | |
228 | *save++ = val; | |
229 | } | |
230 | ||
29cb3cd2 | 231 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 232 | { |
cbe26349 | 233 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 234 | return 0; |
57f277b0 RN |
235 | } |
236 | ||
99e6a4d2 | 237 | void omap_sram_idle(void) |
8bd22949 KH |
238 | { |
239 | /* Variable to tell what needs to be saved and restored | |
240 | * in omap_sram_idle*/ | |
241 | /* save_state = 0 => Nothing to save and restored */ | |
242 | /* save_state = 1 => Only L1 and logic lost */ | |
243 | /* save_state = 2 => Only L2 lost */ | |
244 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
245 | int save_state = 0; |
246 | int mpu_next_state = PWRDM_POWER_ON; | |
247 | int per_next_state = PWRDM_POWER_ON; | |
248 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 249 | int per_going_off; |
eeb3711b | 250 | int core_prev_state; |
13a6fe0f | 251 | u32 sdrc_pwr = 0; |
8bd22949 | 252 | |
8bd22949 KH |
253 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
254 | switch (mpu_next_state) { | |
fa3c2a4f | 255 | case PWRDM_POWER_ON: |
8bd22949 KH |
256 | case PWRDM_POWER_RET: |
257 | /* No need to save context */ | |
258 | save_state = 0; | |
259 | break; | |
61255ab9 RN |
260 | case PWRDM_POWER_OFF: |
261 | save_state = 3; | |
262 | break; | |
8bd22949 KH |
263 | default: |
264 | /* Invalid state */ | |
98179856 | 265 | pr_err("Invalid mpu state in sram_idle\n"); |
8bd22949 KH |
266 | return; |
267 | } | |
fe617af7 | 268 | |
fa3c2a4f RN |
269 | /* NEON control */ |
270 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 271 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 272 | |
40742fa8 | 273 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 274 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 275 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
40742fa8 | 276 | |
e0e29fd7 | 277 | pwrdm_pre_transition(NULL); |
ff2f8e5f | 278 | |
40742fa8 | 279 | /* PER */ |
658ce97e | 280 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 281 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
72e06d08 | 282 | omap2_gpio_prepare_for_idle(per_going_off); |
658ce97e KH |
283 | } |
284 | ||
285 | /* CORE */ | |
fa3c2a4f | 286 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
287 | if (core_next_state == PWRDM_POWER_OFF) { |
288 | omap3_core_save_context(); | |
f0611a5c | 289 | omap3_cm_save_context(); |
2f5939c3 | 290 | } |
fa3c2a4f | 291 | } |
40742fa8 | 292 | |
f18cc2ff | 293 | omap3_intc_prepare_idle(); |
8bd22949 | 294 | |
13a6fe0f | 295 | /* |
30474544 PW |
296 | * On EMU/HS devices ROM code restores a SRDC value |
297 | * from scratchpad which has automatic self refresh on timeout | |
298 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
299 | * Hence store/restore the SDRC_POWER register here. | |
300 | */ | |
301 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
302 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
303 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 304 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 305 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 306 | |
61255ab9 | 307 | /* |
076f2cc4 RK |
308 | * omap3_arm_context is the location where some ARM context |
309 | * get saved. The rest is placed on the stack, and restored | |
310 | * from there before resuming. | |
61255ab9 | 311 | */ |
cbe26349 RK |
312 | if (save_state) |
313 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 314 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 315 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
316 | else |
317 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 318 | |
f265dc4c | 319 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
320 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
321 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
322 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
323 | core_next_state == PWRDM_POWER_OFF) |
324 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
325 | ||
658ce97e | 326 | /* CORE */ |
fa3c2a4f | 327 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
328 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
329 | if (core_prev_state == PWRDM_POWER_OFF) { | |
330 | omap3_core_restore_context(); | |
f0611a5c | 331 | omap3_cm_restore_context(); |
2f5939c3 | 332 | omap3_sram_restore_context(); |
8a917d2f | 333 | omap2_sms_restore_context(); |
2f5939c3 | 334 | } |
658ce97e | 335 | if (core_next_state == PWRDM_POWER_OFF) |
c4d7e58f | 336 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
658ce97e KH |
337 | OMAP3430_GR_MOD, |
338 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
339 | } | |
f18cc2ff | 340 | omap3_intc_resume_idle(); |
658ce97e | 341 | |
e0e29fd7 KH |
342 | pwrdm_post_transition(NULL); |
343 | ||
658ce97e | 344 | /* PER */ |
e0e29fd7 | 345 | if (per_next_state < PWRDM_POWER_ON) |
43ffcd9a | 346 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
347 | } |
348 | ||
8bd22949 KH |
349 | static void omap3_pm_idle(void) |
350 | { | |
8bd22949 KH |
351 | local_fiq_disable(); |
352 | ||
0bcd24b0 | 353 | if (omap_irq_pending()) |
8bd22949 KH |
354 | goto out; |
355 | ||
5e7c58dc JP |
356 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
357 | trace_cpu_idle(1, smp_processor_id()); | |
358 | ||
8bd22949 KH |
359 | omap_sram_idle(); |
360 | ||
5e7c58dc JP |
361 | trace_power_end(smp_processor_id()); |
362 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
363 | ||
8bd22949 KH |
364 | out: |
365 | local_fiq_enable(); | |
8bd22949 KH |
366 | } |
367 | ||
10f90ed2 | 368 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
369 | static int omap3_pm_suspend(void) |
370 | { | |
371 | struct power_state *pwrst; | |
372 | int state, ret = 0; | |
373 | ||
374 | /* Read current next_pwrsts */ | |
375 | list_for_each_entry(pwrst, &pwrst_list, node) | |
376 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
377 | /* Set ones wanted by suspend */ | |
378 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 379 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
380 | goto restore; |
381 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
382 | goto restore; | |
383 | } | |
384 | ||
2bbe3af3 TK |
385 | omap3_intc_suspend(); |
386 | ||
8bd22949 KH |
387 | omap_sram_idle(); |
388 | ||
389 | restore: | |
390 | /* Restore next_pwrsts */ | |
391 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
392 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
393 | if (state > pwrst->next_state) { | |
7852ec05 PW |
394 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
395 | pwrst->pwrdm->name, pwrst->next_state); | |
8bd22949 KH |
396 | ret = -1; |
397 | } | |
eb6a2c75 | 398 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
399 | } |
400 | if (ret) | |
98179856 | 401 | pr_err("Could not enter target state in pm_suspend\n"); |
8bd22949 | 402 | else |
98179856 | 403 | pr_info("Successfully put all powerdomains to target state\n"); |
8bd22949 KH |
404 | |
405 | return ret; | |
406 | } | |
407 | ||
10f90ed2 | 408 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 409 | |
1155e426 KH |
410 | |
411 | /** | |
412 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
413 | * retention | |
414 | * | |
415 | * In cases where IVA2 is activated by bootcode, it may prevent | |
416 | * full-chip retention or off-mode because it is not idle. This | |
417 | * function forces the IVA2 into idle state so it can go | |
418 | * into retention/off and thus allow full-chip retention/off. | |
419 | * | |
420 | **/ | |
421 | static void __init omap3_iva_idle(void) | |
422 | { | |
423 | /* ensure IVA2 clock is disabled */ | |
c4d7e58f | 424 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
425 | |
426 | /* if no clock activity, nothing else to do */ | |
c4d7e58f | 427 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
1155e426 KH |
428 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
429 | return; | |
430 | ||
431 | /* Reset IVA2 */ | |
c4d7e58f | 432 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
433 | OMAP3430_RST2_IVA2_MASK | |
434 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 435 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
436 | |
437 | /* Enable IVA2 clock */ | |
c4d7e58f | 438 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
1155e426 KH |
439 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
440 | ||
441 | /* Set IVA2 boot mode to 'idle' */ | |
442 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
443 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
444 | ||
445 | /* Un-reset IVA2 */ | |
c4d7e58f | 446 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
447 | |
448 | /* Disable IVA2 clock */ | |
c4d7e58f | 449 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
450 | |
451 | /* Reset IVA2 */ | |
c4d7e58f | 452 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
453 | OMAP3430_RST2_IVA2_MASK | |
454 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 455 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
456 | } |
457 | ||
8111b221 | 458 | static void __init omap3_d2d_idle(void) |
8bd22949 | 459 | { |
8111b221 KH |
460 | u16 mask, padconf; |
461 | ||
462 | /* In a stand alone OMAP3430 where there is not a stacked | |
463 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
464 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
465 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
466 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
467 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
468 | padconf |= mask; | |
469 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
470 | ||
471 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
472 | padconf |= mask; | |
473 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
474 | ||
8bd22949 | 475 | /* reset modem */ |
c4d7e58f | 476 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
2bc4ef71 | 477 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
37903009 | 478 | CORE_MOD, OMAP2_RM_RSTCTRL); |
c4d7e58f | 479 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
8111b221 | 480 | } |
8bd22949 | 481 | |
8111b221 KH |
482 | static void __init prcm_setup_regs(void) |
483 | { | |
e5863689 G |
484 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
485 | OMAP3630_EN_UART4_MASK : 0; | |
486 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | |
487 | OMAP3630_GRPSEL_UART4_MASK : 0; | |
488 | ||
4ef70c06 | 489 | /* XXX This should be handled by hwmod code or SCM init code */ |
2fd0f75c | 490 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
b296c811 | 491 | |
8bd22949 KH |
492 | /* |
493 | * Enable control of expternal oscillator through | |
494 | * sys_clkreq. In the long run clock framework should | |
495 | * take care of this. | |
496 | */ | |
c4d7e58f | 497 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
8bd22949 KH |
498 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
499 | OMAP3430_GR_MOD, | |
500 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
501 | ||
502 | /* setup wakup source */ | |
c4d7e58f | 503 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
2fd0f75c | 504 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
8bd22949 KH |
505 | WKUP_MOD, PM_WKEN); |
506 | /* No need to write EN_IO, that is always enabled */ | |
c4d7e58f | 507 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
275f675c PW |
508 | OMAP3430_GRPSEL_GPT1_MASK | |
509 | OMAP3430_GRPSEL_GPT12_MASK, | |
8bd22949 | 510 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
1155e426 | 511 | |
b92c5721 | 512 | /* Enable PM_WKEN to support DSS LPR */ |
c4d7e58f | 513 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
b92c5721 SV |
514 | OMAP3430_DSS_MOD, PM_WKEN); |
515 | ||
b427f92f | 516 | /* Enable wakeups in PER */ |
c4d7e58f | 517 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
e5863689 | 518 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
2fd0f75c PW |
519 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
520 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | |
521 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | |
522 | OMAP3430_EN_MCBSP4_MASK, | |
b427f92f | 523 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 | 524 | /* and allow them to wake up MPU */ |
c4d7e58f | 525 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
e5863689 | 526 | OMAP3430_GRPSEL_GPIO2_MASK | |
275f675c PW |
527 | OMAP3430_GRPSEL_GPIO3_MASK | |
528 | OMAP3430_GRPSEL_GPIO4_MASK | | |
529 | OMAP3430_GRPSEL_GPIO5_MASK | | |
530 | OMAP3430_GRPSEL_GPIO6_MASK | | |
531 | OMAP3430_GRPSEL_UART3_MASK | | |
532 | OMAP3430_GRPSEL_MCBSP2_MASK | | |
533 | OMAP3430_GRPSEL_MCBSP3_MASK | | |
534 | OMAP3430_GRPSEL_MCBSP4_MASK, | |
eb350f74 KH |
535 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
536 | ||
d3fd3290 | 537 | /* Don't attach IVA interrupts */ |
a819c4f1 MG |
538 | if (omap3_has_iva()) { |
539 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | |
540 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
541 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
542 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, | |
543 | OMAP3430_PM_IVAGRPSEL); | |
544 | } | |
d3fd3290 | 545 | |
b1340d17 | 546 | /* Clear any pending 'reset' flags */ |
c4d7e58f PW |
547 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
548 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | |
549 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | |
550 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | |
551 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | |
552 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | |
553 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | |
b1340d17 | 554 | |
014c46db | 555 | /* Clear any pending PRCM interrupts */ |
c4d7e58f | 556 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
014c46db | 557 | |
a819c4f1 MG |
558 | if (omap3_has_iva()) |
559 | omap3_iva_idle(); | |
560 | ||
8111b221 | 561 | omap3_d2d_idle(); |
8bd22949 KH |
562 | } |
563 | ||
c40552bc KH |
564 | void omap3_pm_off_mode_enable(int enable) |
565 | { | |
566 | struct power_state *pwrst; | |
567 | u32 state; | |
568 | ||
569 | if (enable) | |
570 | state = PWRDM_POWER_OFF; | |
571 | else | |
572 | state = PWRDM_POWER_RET; | |
573 | ||
574 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
575 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
576 | pwrst->pwrdm == core_pwrdm && | |
577 | state == PWRDM_POWER_OFF) { | |
578 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 579 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
580 | __func__); |
581 | } else { | |
582 | pwrst->next_state = state; | |
583 | } | |
584 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
585 | } |
586 | } | |
587 | ||
68d4778c TK |
588 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
589 | { | |
590 | struct power_state *pwrst; | |
591 | ||
592 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
593 | if (pwrst->pwrdm == pwrdm) | |
594 | return pwrst->next_state; | |
595 | } | |
596 | return -EINVAL; | |
597 | } | |
598 | ||
599 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
600 | { | |
601 | struct power_state *pwrst; | |
602 | ||
603 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
604 | if (pwrst->pwrdm == pwrdm) { | |
605 | pwrst->next_state = state; | |
606 | return 0; | |
607 | } | |
608 | } | |
609 | return -EINVAL; | |
610 | } | |
611 | ||
a23456e9 | 612 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
613 | { |
614 | struct power_state *pwrst; | |
615 | ||
616 | if (!pwrdm->pwrsts) | |
617 | return 0; | |
618 | ||
d3d381c6 | 619 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
620 | if (!pwrst) |
621 | return -ENOMEM; | |
622 | pwrst->pwrdm = pwrdm; | |
623 | pwrst->next_state = PWRDM_POWER_RET; | |
624 | list_add(&pwrst->node, &pwrst_list); | |
625 | ||
626 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
627 | pwrdm_enable_hdwr_sar(pwrdm); | |
628 | ||
eb6a2c75 | 629 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
630 | } |
631 | ||
46e130d2 JP |
632 | /* |
633 | * Push functions to SRAM | |
634 | * | |
635 | * The minimum set of functions is pushed to SRAM for execution: | |
636 | * - omap3_do_wfi for erratum i581 WA, | |
637 | * - save_secure_ram_context for security extensions. | |
638 | */ | |
3231fc88 RN |
639 | void omap_push_sram_idle(void) |
640 | { | |
46e130d2 JP |
641 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
642 | ||
27d59a4a TK |
643 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
644 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
645 | save_secure_ram_context_sz); | |
3231fc88 RN |
646 | } |
647 | ||
8cdfd834 NM |
648 | static void __init pm_errata_configure(void) |
649 | { | |
c4236d2e | 650 | if (cpu_is_omap3630()) { |
458e999e | 651 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
652 | /* Enable the l2 cache toggling in sleep logic */ |
653 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 | 654 | if (omap_rev() < OMAP3630_REV_ES1_2) |
856c3c5b PW |
655 | pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | |
656 | PM_PER_MEMORIES_ERRATUM_i582); | |
657 | } else if (cpu_is_omap34xx()) { | |
658 | pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; | |
c4236d2e | 659 | } |
8cdfd834 NM |
660 | } |
661 | ||
bbd707ac | 662 | int __init omap3_pm_init(void) |
8bd22949 KH |
663 | { |
664 | struct power_state *pwrst, *tmp; | |
856c3c5b | 665 | struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; |
8bd22949 KH |
666 | int ret; |
667 | ||
b02b9172 PW |
668 | if (!omap3_has_io_chain_ctrl()) |
669 | pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); | |
670 | ||
8cdfd834 NM |
671 | pm_errata_configure(); |
672 | ||
8bd22949 KH |
673 | /* XXX prcm_setup_regs needs to be before enabling hw |
674 | * supervised mode for powerdomains */ | |
675 | prcm_setup_regs(); | |
676 | ||
22f51371 TK |
677 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
678 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); | |
679 | ||
680 | if (ret) { | |
681 | pr_err("pm: Failed to request pm_wkup irq\n"); | |
682 | goto err1; | |
683 | } | |
684 | ||
685 | /* IO interrupt is shared with mux code */ | |
686 | ret = request_irq(omap_prcm_event_to_irq("io"), | |
687 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", | |
688 | omap3_pm_init); | |
99b59df0 | 689 | enable_irq(omap_prcm_event_to_irq("io")); |
22f51371 | 690 | |
8bd22949 | 691 | if (ret) { |
22f51371 | 692 | pr_err("pm: Failed to request pm_io irq\n"); |
ce229c5d | 693 | goto err2; |
8bd22949 KH |
694 | } |
695 | ||
a23456e9 | 696 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 | 697 | if (ret) { |
98179856 | 698 | pr_err("Failed to setup powerdomains\n"); |
ce229c5d | 699 | goto err3; |
8bd22949 KH |
700 | } |
701 | ||
92206fd2 | 702 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
8bd22949 KH |
703 | |
704 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
705 | if (mpu_pwrdm == NULL) { | |
98179856 | 706 | pr_err("Failed to get mpu_pwrdm\n"); |
ce229c5d MG |
707 | ret = -EINVAL; |
708 | goto err3; | |
8bd22949 KH |
709 | } |
710 | ||
fa3c2a4f RN |
711 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
712 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
713 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
714 | ||
55ed9694 PW |
715 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
716 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
856c3c5b PW |
717 | per_clkdm = clkdm_lookup("per_clkdm"); |
718 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
55ed9694 | 719 | |
10f90ed2 | 720 | #ifdef CONFIG_SUSPEND |
1416408d PW |
721 | omap_pm_suspend = omap3_pm_suspend; |
722 | #endif | |
8bd22949 | 723 | |
0bcd24b0 | 724 | arm_pm_idle = omap3_pm_idle; |
0343371e | 725 | omap3_idle_init(); |
8bd22949 | 726 | |
458e999e NM |
727 | /* |
728 | * RTA is disabled during initialization as per erratum i608 | |
729 | * it is safer to disable RTA by the bootloader, but we would like | |
730 | * to be doubly sure here and prevent any mishaps. | |
731 | */ | |
732 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
733 | omap3630_ctrl_disable_rta(); | |
734 | ||
856c3c5b PW |
735 | /* |
736 | * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are | |
737 | * not correctly reset when the PER powerdomain comes back | |
738 | * from OFF or OSWR when the CORE powerdomain is kept active. | |
739 | * See OMAP36xx Erratum i582 "PER Domain reset issue after | |
740 | * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a | |
741 | * complete workaround. The kernel must also prevent the PER | |
742 | * powerdomain from going to OSWR/OFF while the CORE | |
743 | * powerdomain is not going to OSWR/OFF. And if PER last | |
744 | * power state was off while CORE last power state was ON, the | |
745 | * UART3/4 and McBSP2/3 SIDETONE devices need to run a | |
746 | * self-test using their loopback tests; if that fails, those | |
747 | * devices are unusable until the PER/CORE can complete a transition | |
748 | * from ON to OSWR/OFF and then back to ON. | |
749 | * | |
750 | * XXX Technically this workaround is only needed if off-mode | |
751 | * or OSWR is enabled. | |
752 | */ | |
753 | if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) | |
754 | clkdm_add_wkdep(per_clkdm, wkup_clkdm); | |
755 | ||
55ed9694 | 756 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
757 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
758 | omap3_secure_ram_storage = | |
759 | kmalloc(0x803F, GFP_KERNEL); | |
760 | if (!omap3_secure_ram_storage) | |
7852ec05 | 761 | pr_err("Memory allocation failed when allocating for secure sram context\n"); |
9d97140b TK |
762 | |
763 | local_irq_disable(); | |
764 | local_fiq_disable(); | |
765 | ||
766 | omap_dma_global_context_save(); | |
617fcc98 | 767 | omap3_save_secure_ram_context(); |
9d97140b TK |
768 | omap_dma_global_context_restore(); |
769 | ||
770 | local_irq_enable(); | |
771 | local_fiq_enable(); | |
27d59a4a | 772 | } |
27d59a4a | 773 | |
9d97140b | 774 | omap3_save_scratchpad_contents(); |
8bd22949 | 775 | return ret; |
ce229c5d MG |
776 | |
777 | err3: | |
8bd22949 KH |
778 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
779 | list_del(&pwrst->node); | |
780 | kfree(pwrst); | |
781 | } | |
ce229c5d MG |
782 | free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
783 | err2: | |
784 | free_irq(omap_prcm_event_to_irq("wkup"), NULL); | |
785 | err1: | |
8bd22949 KH |
786 | return ret; |
787 | } |