Commit | Line | Data |
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d8a94458 | 1 | /* |
ca6eccb3 | 2 | * opp2430_data.c - old-style "OPP" table for OMAP2430 |
d8a94458 PW |
3 | * |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | |
5 | * Copyright (C) 2004-2009 Nokia Corporation | |
6 | * | |
7 | * Richard Woodruff <r-woodruff2@ti.com> | |
8 | * | |
9 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | |
10 | * These configurations are characterized by voltage and speed for clocks. | |
11 | * The device is only validated for certain combinations. One way to express | |
ca6eccb3 | 12 | * these combinations is via the 'ratios' which the clocks operate with |
d8a94458 | 13 | * respect to each other. These ratio sets are for a given voltage/DPLL |
ca6eccb3 | 14 | * setting. All configurations can be described by a DPLL setting and a ratio. |
d8a94458 PW |
15 | * |
16 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | |
17 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | |
18 | * 2430 (iva2.1, NOdsp, mdm) | |
19 | * | |
20 | * XXX Missing voltage data. | |
ca6eccb3 | 21 | * XXX Missing 19.2MHz sys_clk rate sets. |
d8a94458 PW |
22 | * |
23 | * THe format described in this file is deprecated. Once a reasonable | |
24 | * OPP API exists, the data in this file should be converted to use it. | |
25 | * | |
26 | * This is technically part of the OMAP2xxx clock code. | |
27 | */ | |
28 | ||
29 | #include "opp2xxx.h" | |
30 | #include "sdrc.h" | |
31 | #include "clock.h" | |
32 | ||
ca6eccb3 PW |
33 | /* |
34 | * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. | |
d8a94458 PW |
35 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, |
36 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | |
37 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | |
38 | * | |
ca6eccb3 PW |
39 | * Filling in table based on 2430-SDPs variants available. There are |
40 | * quite a few more rate combinations which could be defined. | |
d8a94458 | 41 | * |
ca6eccb3 PW |
42 | * When multiple values are defined the start up will try and choose |
43 | * the fastest one. If a 'fast' value is defined, then automatically, | |
44 | * the /2 one should be included as it can be used. Generally having | |
45 | * more than one fast set does not make sense, as static timings need | |
46 | * to be changed to change the set. The exception is the bypass | |
47 | * setting which is available for low power bypass. | |
d8a94458 PW |
48 | * |
49 | * Note: This table needs to be sorted, fastest to slowest. | |
ca6eccb3 | 50 | */ |
d8a94458 PW |
51 | const struct prcm_config omap2430_rate_table[] = { |
52 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ | |
53 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ | |
54 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | |
55 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | |
56 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | |
57 | SDRC_RFR_CTRL_133MHz, | |
58 | RATE_IN_243X}, | |
59 | ||
60 | /* PRCM #2 - ratio1 (ES2) - FAST */ | |
61 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | |
62 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
63 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | |
64 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
65 | SDRC_RFR_CTRL_165MHz, | |
66 | RATE_IN_243X}, | |
67 | ||
68 | /* PRCM #5a - ratio1 - FAST */ | |
69 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | |
70 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
71 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | |
72 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
73 | SDRC_RFR_CTRL_133MHz, | |
74 | RATE_IN_243X}, | |
75 | ||
76 | /* PRCM #5b - ratio1 - FAST */ | |
77 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | |
78 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
79 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | |
80 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
81 | SDRC_RFR_CTRL_100MHz, | |
82 | RATE_IN_243X}, | |
83 | ||
84 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ | |
85 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | |
86 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | |
87 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | |
88 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | |
89 | SDRC_RFR_CTRL_133MHz, | |
90 | RATE_IN_243X}, | |
91 | ||
92 | /* PRCM #2 - ratio1 (ES2) - SLOW */ | |
93 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | |
94 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
95 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | |
96 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
97 | SDRC_RFR_CTRL_165MHz, | |
98 | RATE_IN_243X}, | |
99 | ||
100 | /* PRCM #5a - ratio1 - SLOW */ | |
101 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | |
102 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
103 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | |
104 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
105 | SDRC_RFR_CTRL_133MHz, | |
106 | RATE_IN_243X}, | |
107 | ||
108 | /* PRCM #5b - ratio1 - SLOW*/ | |
109 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ | |
110 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | |
111 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | |
112 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | |
113 | SDRC_RFR_CTRL_100MHz, | |
114 | RATE_IN_243X}, | |
115 | ||
116 | /* PRCM-boot/bypass */ | |
117 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ | |
118 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | |
119 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | |
120 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | |
121 | SDRC_RFR_CTRL_BYPASS, | |
122 | RATE_IN_243X}, | |
123 | ||
124 | /* PRCM-boot/bypass */ | |
125 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ | |
126 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | |
127 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | |
128 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | |
129 | SDRC_RFR_CTRL_BYPASS, | |
130 | RATE_IN_243X}, | |
131 | ||
132 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
133 | }; |