Commit | Line | Data |
---|---|---|
4d38bd12 TL |
1 | /* |
2 | * DM81xx hwmod data. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ | |
5 | * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/platform_data/gpio-omap.h> | |
19 | #include <linux/platform_data/hsmmc-omap.h> | |
20 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
21 | #include <plat/dmtimer.h> | |
22 | ||
23 | #include "omap_hwmod_common_data.h" | |
24 | #include "cm81xx.h" | |
25 | #include "ti81xx.h" | |
26 | #include "wd_timer.h" | |
27 | ||
28 | /* | |
29 | * DM816X hardware modules integration data | |
30 | * | |
31 | * Note: This is incomplete and at present, not generated from h/w database. | |
32 | */ | |
33 | ||
34 | /* | |
7e1b11d1 TL |
35 | * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" |
36 | * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. | |
4d38bd12 | 37 | */ |
7e1b11d1 TL |
38 | #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 |
39 | #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 | |
40 | #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 | |
41 | #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c | |
42 | #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 | |
43 | #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 | |
44 | #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 | |
45 | #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c | |
46 | #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 | |
47 | #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 | |
48 | #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 | |
49 | #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c | |
50 | #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 | |
51 | #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 | |
52 | #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 | |
53 | #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c | |
54 | #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 | |
55 | #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 | |
56 | #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 | |
57 | #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 | |
58 | #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 | |
59 | #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 | |
60 | #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec | |
61 | #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 | |
62 | #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 | |
63 | #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 | |
64 | #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc | |
65 | #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 | |
66 | #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 | |
67 | ||
68 | /* Registers specific to dm814x */ | |
69 | #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c | |
70 | #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 | |
71 | #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 | |
72 | #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 | |
73 | #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 | |
74 | #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 | |
75 | #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 | |
76 | #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 | |
77 | #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 | |
78 | #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc | |
79 | #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 | |
80 | #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 | |
81 | #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c | |
82 | #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 | |
83 | #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 | |
84 | #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 | |
85 | ||
86 | /* Registers specific to dm816x */ | |
4d38bd12 | 87 | #define DM816X_DM_ALWON_BASE 0x1400 |
4d38bd12 TL |
88 | #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) |
89 | #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) | |
90 | #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) | |
91 | #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) | |
92 | #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) | |
93 | #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) | |
94 | #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
95 | #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) |
96 | #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) | |
97 | #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
98 | #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) |
99 | #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
100 | #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) |
101 | #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) | |
102 | ||
103 | /* | |
104 | * The default .clkctrl_offs field is offset from CM_DEFAULT, that's | |
105 | * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 | |
106 | */ | |
f53850b5 TL |
107 | #define DM81XX_CM_DEFAULT_OFFSET 0x500 |
108 | #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) | |
4d38bd12 TL |
109 | |
110 | /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ | |
7e1b11d1 | 111 | static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { |
4d38bd12 TL |
112 | .name = "alwon_l3_slow", |
113 | .clkdm_name = "alwon_l3s_clkdm", | |
114 | .class = &l3_hwmod_class, | |
115 | .flags = HWMOD_NO_IDLEST, | |
116 | }; | |
117 | ||
7e1b11d1 | 118 | static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { |
4d38bd12 TL |
119 | .name = "default_l3_slow", |
120 | .clkdm_name = "default_l3_slow_clkdm", | |
121 | .class = &l3_hwmod_class, | |
122 | .flags = HWMOD_NO_IDLEST, | |
123 | }; | |
124 | ||
7e1b11d1 | 125 | static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { |
4d38bd12 TL |
126 | .name = "l3_med", |
127 | .clkdm_name = "alwon_l3_med_clkdm", | |
128 | .class = &l3_hwmod_class, | |
129 | .flags = HWMOD_NO_IDLEST, | |
130 | }; | |
131 | ||
7e1b11d1 | 132 | static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { |
4d38bd12 TL |
133 | .name = "l3_fast", |
134 | .clkdm_name = "alwon_l3_fast_clkdm", | |
135 | .class = &l3_hwmod_class, | |
136 | .flags = HWMOD_NO_IDLEST, | |
137 | }; | |
138 | ||
139 | /* | |
140 | * L4 standard peripherals, see TRM table 1-12 for devices using this. | |
141 | * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. | |
142 | */ | |
7e1b11d1 | 143 | static struct omap_hwmod dm81xx_l4_ls_hwmod = { |
4d38bd12 TL |
144 | .name = "l4_ls", |
145 | .clkdm_name = "alwon_l3s_clkdm", | |
146 | .class = &l4_hwmod_class, | |
29f5b34c | 147 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
148 | }; |
149 | ||
150 | /* | |
151 | * L4 high-speed peripherals. For devices using this, please see the TRM | |
152 | * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM | |
153 | * table 1-73 for devices using 250MHz SYSCLK5 clock. | |
154 | */ | |
7e1b11d1 | 155 | static struct omap_hwmod dm81xx_l4_hs_hwmod = { |
4d38bd12 TL |
156 | .name = "l4_hs", |
157 | .clkdm_name = "alwon_l3_med_clkdm", | |
158 | .class = &l4_hwmod_class, | |
29f5b34c | 159 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
160 | }; |
161 | ||
162 | /* L3 slow -> L4 ls peripheral interface running at 125MHz */ | |
7e1b11d1 TL |
163 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { |
164 | .master = &dm81xx_alwon_l3_slow_hwmod, | |
165 | .slave = &dm81xx_l4_ls_hwmod, | |
4d38bd12 TL |
166 | .user = OCP_USER_MPU, |
167 | }; | |
168 | ||
169 | /* L3 med -> L4 fast peripheral interface running at 250MHz */ | |
7e1b11d1 TL |
170 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { |
171 | .master = &dm81xx_alwon_l3_med_hwmod, | |
172 | .slave = &dm81xx_l4_hs_hwmod, | |
4d38bd12 TL |
173 | .user = OCP_USER_MPU, |
174 | }; | |
175 | ||
176 | /* MPU */ | |
0f3ccb24 TL |
177 | static struct omap_hwmod dm814x_mpu_hwmod = { |
178 | .name = "mpu", | |
179 | .clkdm_name = "alwon_l3s_clkdm", | |
180 | .class = &mpu_hwmod_class, | |
181 | .flags = HWMOD_INIT_NO_IDLE, | |
182 | .main_clk = "mpu_ck", | |
183 | .prcm = { | |
184 | .omap4 = { | |
185 | .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, | |
186 | .modulemode = MODULEMODE_SWCTRL, | |
187 | }, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { | |
192 | .master = &dm814x_mpu_hwmod, | |
193 | .slave = &dm81xx_alwon_l3_slow_hwmod, | |
194 | .user = OCP_USER_MPU, | |
195 | }; | |
196 | ||
197 | /* L3 med peripheral interface running at 200MHz */ | |
198 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { | |
199 | .master = &dm814x_mpu_hwmod, | |
200 | .slave = &dm81xx_alwon_l3_med_hwmod, | |
201 | .user = OCP_USER_MPU, | |
202 | }; | |
203 | ||
4d38bd12 TL |
204 | static struct omap_hwmod dm816x_mpu_hwmod = { |
205 | .name = "mpu", | |
206 | .clkdm_name = "alwon_mpu_clkdm", | |
207 | .class = &mpu_hwmod_class, | |
208 | .flags = HWMOD_INIT_NO_IDLE, | |
209 | .main_clk = "mpu_ck", | |
210 | .prcm = { | |
211 | .omap4 = { | |
212 | .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, | |
213 | .modulemode = MODULEMODE_SWCTRL, | |
214 | }, | |
215 | }, | |
216 | }; | |
217 | ||
218 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { | |
219 | .master = &dm816x_mpu_hwmod, | |
7e1b11d1 | 220 | .slave = &dm81xx_alwon_l3_slow_hwmod, |
4d38bd12 TL |
221 | .user = OCP_USER_MPU, |
222 | }; | |
223 | ||
224 | /* L3 med peripheral interface running at 250MHz */ | |
225 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { | |
226 | .master = &dm816x_mpu_hwmod, | |
7e1b11d1 | 227 | .slave = &dm81xx_alwon_l3_med_hwmod, |
4d38bd12 TL |
228 | .user = OCP_USER_MPU, |
229 | }; | |
230 | ||
c5803246 TL |
231 | /* RTC */ |
232 | static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = { | |
233 | .rev_offs = 0x74, | |
234 | .sysc_offs = 0x78, | |
235 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
236 | .idlemodes = SIDLE_FORCE | SIDLE_NO | | |
237 | SIDLE_SMART | SIDLE_SMART_WKUP, | |
238 | .sysc_fields = &omap_hwmod_sysc_type3, | |
239 | }; | |
240 | ||
241 | static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { | |
242 | .name = "rtc", | |
243 | .sysc = &ti81xx_rtc_sysc, | |
244 | }; | |
245 | ||
246 | struct omap_hwmod ti81xx_rtc_hwmod = { | |
247 | .name = "rtc", | |
248 | .class = &ti81xx_rtc_hwmod_class, | |
249 | .clkdm_name = "alwon_l3s_clkdm", | |
250 | .flags = HWMOD_NO_IDLEST, | |
251 | .main_clk = "sysclk18_ck", | |
252 | .prcm = { | |
253 | .omap4 = { | |
254 | .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, | |
255 | .modulemode = MODULEMODE_SWCTRL, | |
256 | }, | |
257 | }, | |
258 | }; | |
259 | ||
260 | static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = { | |
261 | .master = &dm81xx_l4_ls_hwmod, | |
262 | .slave = &ti81xx_rtc_hwmod, | |
263 | .clk = "sysclk6_ck", | |
264 | .user = OCP_USER_MPU, | |
265 | }; | |
266 | ||
4d38bd12 TL |
267 | /* UART common */ |
268 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
269 | .rev_offs = 0x50, | |
270 | .sysc_offs = 0x54, | |
271 | .syss_offs = 0x58, | |
272 | .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
273 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
274 | SYSS_HAS_RESET_STATUS, | |
275 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
276 | MSTANDBY_SMART_WKUP, | |
277 | .sysc_fields = &omap_hwmod_sysc_type1, | |
278 | }; | |
279 | ||
280 | static struct omap_hwmod_class uart_class = { | |
281 | .name = "uart", | |
282 | .sysc = &uart_sysc, | |
283 | }; | |
284 | ||
7e1b11d1 | 285 | static struct omap_hwmod dm81xx_uart1_hwmod = { |
4d38bd12 TL |
286 | .name = "uart1", |
287 | .clkdm_name = "alwon_l3s_clkdm", | |
288 | .main_clk = "sysclk10_ck", | |
289 | .prcm = { | |
290 | .omap4 = { | |
7e1b11d1 | 291 | .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, |
4d38bd12 TL |
292 | .modulemode = MODULEMODE_SWCTRL, |
293 | }, | |
294 | }, | |
295 | .class = &uart_class, | |
296 | .flags = DEBUG_TI81XXUART1_FLAGS, | |
297 | }; | |
298 | ||
7e1b11d1 TL |
299 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { |
300 | .master = &dm81xx_l4_ls_hwmod, | |
301 | .slave = &dm81xx_uart1_hwmod, | |
4d38bd12 TL |
302 | .clk = "sysclk6_ck", |
303 | .user = OCP_USER_MPU, | |
304 | }; | |
305 | ||
7e1b11d1 | 306 | static struct omap_hwmod dm81xx_uart2_hwmod = { |
4d38bd12 TL |
307 | .name = "uart2", |
308 | .clkdm_name = "alwon_l3s_clkdm", | |
309 | .main_clk = "sysclk10_ck", | |
310 | .prcm = { | |
311 | .omap4 = { | |
7e1b11d1 | 312 | .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, |
4d38bd12 TL |
313 | .modulemode = MODULEMODE_SWCTRL, |
314 | }, | |
315 | }, | |
316 | .class = &uart_class, | |
317 | .flags = DEBUG_TI81XXUART2_FLAGS, | |
318 | }; | |
319 | ||
7e1b11d1 TL |
320 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { |
321 | .master = &dm81xx_l4_ls_hwmod, | |
322 | .slave = &dm81xx_uart2_hwmod, | |
4d38bd12 TL |
323 | .clk = "sysclk6_ck", |
324 | .user = OCP_USER_MPU, | |
325 | }; | |
326 | ||
7e1b11d1 | 327 | static struct omap_hwmod dm81xx_uart3_hwmod = { |
4d38bd12 TL |
328 | .name = "uart3", |
329 | .clkdm_name = "alwon_l3s_clkdm", | |
330 | .main_clk = "sysclk10_ck", | |
331 | .prcm = { | |
332 | .omap4 = { | |
7e1b11d1 | 333 | .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, |
4d38bd12 TL |
334 | .modulemode = MODULEMODE_SWCTRL, |
335 | }, | |
336 | }, | |
337 | .class = &uart_class, | |
338 | .flags = DEBUG_TI81XXUART3_FLAGS, | |
339 | }; | |
340 | ||
7e1b11d1 TL |
341 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { |
342 | .master = &dm81xx_l4_ls_hwmod, | |
343 | .slave = &dm81xx_uart3_hwmod, | |
4d38bd12 TL |
344 | .clk = "sysclk6_ck", |
345 | .user = OCP_USER_MPU, | |
346 | }; | |
347 | ||
348 | static struct omap_hwmod_class_sysconfig wd_timer_sysc = { | |
349 | .rev_offs = 0x0, | |
350 | .sysc_offs = 0x10, | |
351 | .syss_offs = 0x14, | |
352 | .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
353 | SYSS_HAS_RESET_STATUS, | |
354 | .sysc_fields = &omap_hwmod_sysc_type1, | |
355 | }; | |
356 | ||
357 | static struct omap_hwmod_class wd_timer_class = { | |
358 | .name = "wd_timer", | |
359 | .sysc = &wd_timer_sysc, | |
360 | .pre_shutdown = &omap2_wd_timer_disable, | |
361 | .reset = &omap2_wd_timer_reset, | |
362 | }; | |
363 | ||
7e1b11d1 | 364 | static struct omap_hwmod dm81xx_wd_timer_hwmod = { |
4d38bd12 TL |
365 | .name = "wd_timer", |
366 | .clkdm_name = "alwon_l3s_clkdm", | |
367 | .main_clk = "sysclk18_ck", | |
368 | .flags = HWMOD_NO_IDLEST, | |
369 | .prcm = { | |
370 | .omap4 = { | |
7e1b11d1 | 371 | .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, |
4d38bd12 TL |
372 | .modulemode = MODULEMODE_SWCTRL, |
373 | }, | |
374 | }, | |
375 | .class = &wd_timer_class, | |
376 | }; | |
377 | ||
7e1b11d1 TL |
378 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { |
379 | .master = &dm81xx_l4_ls_hwmod, | |
380 | .slave = &dm81xx_wd_timer_hwmod, | |
4d38bd12 TL |
381 | .clk = "sysclk6_ck", |
382 | .user = OCP_USER_MPU, | |
383 | }; | |
384 | ||
385 | /* I2C common */ | |
386 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
387 | .rev_offs = 0x0, | |
388 | .sysc_offs = 0x10, | |
389 | .syss_offs = 0x90, | |
390 | .sysc_flags = SYSC_HAS_SIDLEMODE | | |
391 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
392 | SYSC_HAS_AUTOIDLE, | |
393 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
394 | .sysc_fields = &omap_hwmod_sysc_type1, | |
395 | }; | |
396 | ||
397 | static struct omap_hwmod_class i2c_class = { | |
398 | .name = "i2c", | |
399 | .sysc = &i2c_sysc, | |
400 | }; | |
401 | ||
402 | static struct omap_hwmod dm81xx_i2c1_hwmod = { | |
403 | .name = "i2c1", | |
404 | .clkdm_name = "alwon_l3s_clkdm", | |
405 | .main_clk = "sysclk10_ck", | |
406 | .prcm = { | |
407 | .omap4 = { | |
7e1b11d1 | 408 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, |
4d38bd12 TL |
409 | .modulemode = MODULEMODE_SWCTRL, |
410 | }, | |
411 | }, | |
412 | .class = &i2c_class, | |
413 | }; | |
414 | ||
7e1b11d1 TL |
415 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { |
416 | .master = &dm81xx_l4_ls_hwmod, | |
4d38bd12 TL |
417 | .slave = &dm81xx_i2c1_hwmod, |
418 | .clk = "sysclk6_ck", | |
419 | .user = OCP_USER_MPU, | |
420 | }; | |
421 | ||
7e1b11d1 | 422 | static struct omap_hwmod dm81xx_i2c2_hwmod = { |
4d38bd12 TL |
423 | .name = "i2c2", |
424 | .clkdm_name = "alwon_l3s_clkdm", | |
425 | .main_clk = "sysclk10_ck", | |
426 | .prcm = { | |
427 | .omap4 = { | |
7e1b11d1 | 428 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, |
4d38bd12 TL |
429 | .modulemode = MODULEMODE_SWCTRL, |
430 | }, | |
431 | }, | |
432 | .class = &i2c_class, | |
433 | }; | |
434 | ||
435 | static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { | |
436 | .rev_offs = 0x0000, | |
437 | .sysc_offs = 0x0010, | |
438 | .syss_offs = 0x0014, | |
439 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
440 | SYSC_HAS_SOFTRESET | | |
441 | SYSS_HAS_RESET_STATUS, | |
442 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
443 | .sysc_fields = &omap_hwmod_sysc_type1, | |
444 | }; | |
445 | ||
7e1b11d1 TL |
446 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { |
447 | .master = &dm81xx_l4_ls_hwmod, | |
448 | .slave = &dm81xx_i2c2_hwmod, | |
4d38bd12 TL |
449 | .clk = "sysclk6_ck", |
450 | .user = OCP_USER_MPU, | |
451 | }; | |
452 | ||
453 | static struct omap_hwmod_class dm81xx_elm_hwmod_class = { | |
454 | .name = "elm", | |
455 | .sysc = &dm81xx_elm_sysc, | |
456 | }; | |
457 | ||
458 | static struct omap_hwmod dm81xx_elm_hwmod = { | |
459 | .name = "elm", | |
460 | .clkdm_name = "alwon_l3s_clkdm", | |
461 | .class = &dm81xx_elm_hwmod_class, | |
462 | .main_clk = "sysclk6_ck", | |
463 | }; | |
464 | ||
465 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { | |
7e1b11d1 | 466 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 | 467 | .slave = &dm81xx_elm_hwmod, |
4f5395f0 | 468 | .clk = "sysclk6_ck", |
4d38bd12 TL |
469 | .user = OCP_USER_MPU, |
470 | }; | |
471 | ||
472 | static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { | |
473 | .rev_offs = 0x0000, | |
474 | .sysc_offs = 0x0010, | |
475 | .syss_offs = 0x0114, | |
476 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
477 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
478 | SYSS_HAS_RESET_STATUS, | |
479 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
480 | SIDLE_SMART_WKUP, | |
481 | .sysc_fields = &omap_hwmod_sysc_type1, | |
482 | }; | |
483 | ||
484 | static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { | |
485 | .name = "gpio", | |
486 | .sysc = &dm81xx_gpio_sysc, | |
487 | .rev = 2, | |
488 | }; | |
489 | ||
490 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
491 | .bank_width = 32, | |
492 | .dbck_flag = true, | |
493 | }; | |
494 | ||
495 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
496 | { .role = "dbclk", .clk = "sysclk18_ck" }, | |
497 | }; | |
498 | ||
499 | static struct omap_hwmod dm81xx_gpio1_hwmod = { | |
500 | .name = "gpio1", | |
501 | .clkdm_name = "alwon_l3s_clkdm", | |
502 | .class = &dm81xx_gpio_hwmod_class, | |
503 | .main_clk = "sysclk6_ck", | |
504 | .prcm = { | |
505 | .omap4 = { | |
7e1b11d1 | 506 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, |
4d38bd12 TL |
507 | .modulemode = MODULEMODE_SWCTRL, |
508 | }, | |
509 | }, | |
510 | .opt_clks = gpio1_opt_clks, | |
511 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
512 | .dev_attr = &gpio_dev_attr, | |
513 | }; | |
514 | ||
515 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { | |
7e1b11d1 | 516 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 | 517 | .slave = &dm81xx_gpio1_hwmod, |
4f5395f0 | 518 | .clk = "sysclk6_ck", |
4d38bd12 TL |
519 | .user = OCP_USER_MPU, |
520 | }; | |
521 | ||
522 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
523 | { .role = "dbclk", .clk = "sysclk18_ck" }, | |
524 | }; | |
525 | ||
526 | static struct omap_hwmod dm81xx_gpio2_hwmod = { | |
527 | .name = "gpio2", | |
528 | .clkdm_name = "alwon_l3s_clkdm", | |
529 | .class = &dm81xx_gpio_hwmod_class, | |
530 | .main_clk = "sysclk6_ck", | |
531 | .prcm = { | |
532 | .omap4 = { | |
7e1b11d1 | 533 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
4d38bd12 TL |
534 | .modulemode = MODULEMODE_SWCTRL, |
535 | }, | |
536 | }, | |
537 | .opt_clks = gpio2_opt_clks, | |
538 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
539 | .dev_attr = &gpio_dev_attr, | |
540 | }; | |
541 | ||
542 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { | |
7e1b11d1 | 543 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 | 544 | .slave = &dm81xx_gpio2_hwmod, |
4f5395f0 | 545 | .clk = "sysclk6_ck", |
4d38bd12 TL |
546 | .user = OCP_USER_MPU, |
547 | }; | |
548 | ||
549 | static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { | |
550 | .rev_offs = 0x0, | |
551 | .sysc_offs = 0x10, | |
552 | .syss_offs = 0x14, | |
553 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
554 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
555 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
556 | .sysc_fields = &omap_hwmod_sysc_type1, | |
557 | }; | |
558 | ||
559 | static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { | |
560 | .name = "gpmc", | |
561 | .sysc = &dm81xx_gpmc_sysc, | |
562 | }; | |
563 | ||
564 | static struct omap_hwmod dm81xx_gpmc_hwmod = { | |
565 | .name = "gpmc", | |
566 | .clkdm_name = "alwon_l3s_clkdm", | |
567 | .class = &dm81xx_gpmc_hwmod_class, | |
568 | .main_clk = "sysclk6_ck", | |
63aa945b TL |
569 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
570 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
4d38bd12 TL |
571 | .prcm = { |
572 | .omap4 = { | |
7e1b11d1 | 573 | .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, |
4d38bd12 TL |
574 | .modulemode = MODULEMODE_SWCTRL, |
575 | }, | |
576 | }, | |
577 | }; | |
578 | ||
f734a9b3 | 579 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { |
7e1b11d1 | 580 | .master = &dm81xx_alwon_l3_slow_hwmod, |
4d38bd12 TL |
581 | .slave = &dm81xx_gpmc_hwmod, |
582 | .user = OCP_USER_MPU, | |
583 | }; | |
584 | ||
ebf24414 | 585 | /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */ |
4d38bd12 TL |
586 | static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { |
587 | .rev_offs = 0x0, | |
588 | .sysc_offs = 0x10, | |
ebf24414 | 589 | .srst_udelay = 2, |
4d38bd12 TL |
590 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
591 | SYSC_HAS_SOFTRESET, | |
592 | .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, | |
593 | .sysc_fields = &omap_hwmod_sysc_type2, | |
594 | }; | |
595 | ||
596 | static struct omap_hwmod_class dm81xx_usbotg_class = { | |
597 | .name = "usbotg", | |
598 | .sysc = &dm81xx_usbhsotg_sysc, | |
599 | }; | |
600 | ||
f53850b5 TL |
601 | static struct omap_hwmod dm814x_usbss_hwmod = { |
602 | .name = "usb_otg_hs", | |
603 | .clkdm_name = "default_l3_slow_clkdm", | |
604 | .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ | |
605 | .prcm = { | |
606 | .omap4 = { | |
607 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, | |
608 | .modulemode = MODULEMODE_SWCTRL, | |
609 | }, | |
610 | }, | |
611 | .class = &dm81xx_usbotg_class, | |
612 | }; | |
613 | ||
614 | static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { | |
615 | .master = &dm81xx_default_l3_slow_hwmod, | |
616 | .slave = &dm814x_usbss_hwmod, | |
617 | .clk = "sysclk6_ck", | |
618 | .user = OCP_USER_MPU, | |
619 | }; | |
620 | ||
621 | static struct omap_hwmod dm816x_usbss_hwmod = { | |
4d38bd12 TL |
622 | .name = "usb_otg_hs", |
623 | .clkdm_name = "default_l3_slow_clkdm", | |
624 | .main_clk = "sysclk6_ck", | |
625 | .prcm = { | |
626 | .omap4 = { | |
f53850b5 | 627 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, |
4d38bd12 TL |
628 | .modulemode = MODULEMODE_SWCTRL, |
629 | }, | |
630 | }, | |
631 | .class = &dm81xx_usbotg_class, | |
632 | }; | |
633 | ||
f53850b5 | 634 | static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { |
7e1b11d1 | 635 | .master = &dm81xx_default_l3_slow_hwmod, |
f53850b5 | 636 | .slave = &dm816x_usbss_hwmod, |
4d38bd12 TL |
637 | .clk = "sysclk6_ck", |
638 | .user = OCP_USER_MPU, | |
639 | }; | |
640 | ||
641 | static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { | |
642 | .rev_offs = 0x0000, | |
643 | .sysc_offs = 0x0010, | |
644 | .syss_offs = 0x0014, | |
645 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, | |
646 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
647 | SIDLE_SMART_WKUP, | |
648 | .sysc_fields = &omap_hwmod_sysc_type2, | |
649 | }; | |
650 | ||
651 | static struct omap_hwmod_class dm816x_timer_hwmod_class = { | |
652 | .name = "timer", | |
653 | .sysc = &dm816x_timer_sysc, | |
654 | }; | |
655 | ||
656 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
657 | .timer_capability = OMAP_TIMER_ALWON, | |
658 | }; | |
659 | ||
0f3ccb24 TL |
660 | static struct omap_hwmod dm814x_timer1_hwmod = { |
661 | .name = "timer1", | |
662 | .clkdm_name = "alwon_l3s_clkdm", | |
cb4db038 | 663 | .main_clk = "timer1_fck", |
0f3ccb24 TL |
664 | .dev_attr = &capability_alwon_dev_attr, |
665 | .class = &dm816x_timer_hwmod_class, | |
666 | .flags = HWMOD_NO_IDLEST, | |
667 | }; | |
668 | ||
669 | static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { | |
670 | .master = &dm81xx_l4_ls_hwmod, | |
671 | .slave = &dm814x_timer1_hwmod, | |
4f5395f0 | 672 | .clk = "sysclk6_ck", |
0f3ccb24 TL |
673 | .user = OCP_USER_MPU, |
674 | }; | |
675 | ||
4d38bd12 TL |
676 | static struct omap_hwmod dm816x_timer1_hwmod = { |
677 | .name = "timer1", | |
678 | .clkdm_name = "alwon_l3s_clkdm", | |
679 | .main_clk = "timer1_fck", | |
680 | .prcm = { | |
681 | .omap4 = { | |
682 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, | |
683 | .modulemode = MODULEMODE_SWCTRL, | |
684 | }, | |
685 | }, | |
686 | .dev_attr = &capability_alwon_dev_attr, | |
687 | .class = &dm816x_timer_hwmod_class, | |
688 | }; | |
689 | ||
690 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { | |
7e1b11d1 | 691 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
692 | .slave = &dm816x_timer1_hwmod, |
693 | .clk = "sysclk6_ck", | |
694 | .user = OCP_USER_MPU, | |
695 | }; | |
696 | ||
0f3ccb24 TL |
697 | static struct omap_hwmod dm814x_timer2_hwmod = { |
698 | .name = "timer2", | |
699 | .clkdm_name = "alwon_l3s_clkdm", | |
cb4db038 | 700 | .main_clk = "timer2_fck", |
0f3ccb24 TL |
701 | .dev_attr = &capability_alwon_dev_attr, |
702 | .class = &dm816x_timer_hwmod_class, | |
703 | .flags = HWMOD_NO_IDLEST, | |
704 | }; | |
705 | ||
706 | static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { | |
707 | .master = &dm81xx_l4_ls_hwmod, | |
708 | .slave = &dm814x_timer2_hwmod, | |
4f5395f0 | 709 | .clk = "sysclk6_ck", |
0f3ccb24 TL |
710 | .user = OCP_USER_MPU, |
711 | }; | |
712 | ||
4d38bd12 TL |
713 | static struct omap_hwmod dm816x_timer2_hwmod = { |
714 | .name = "timer2", | |
715 | .clkdm_name = "alwon_l3s_clkdm", | |
716 | .main_clk = "timer2_fck", | |
717 | .prcm = { | |
718 | .omap4 = { | |
719 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, | |
720 | .modulemode = MODULEMODE_SWCTRL, | |
721 | }, | |
722 | }, | |
723 | .dev_attr = &capability_alwon_dev_attr, | |
724 | .class = &dm816x_timer_hwmod_class, | |
725 | }; | |
726 | ||
727 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { | |
7e1b11d1 | 728 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
729 | .slave = &dm816x_timer2_hwmod, |
730 | .clk = "sysclk6_ck", | |
731 | .user = OCP_USER_MPU, | |
732 | }; | |
733 | ||
734 | static struct omap_hwmod dm816x_timer3_hwmod = { | |
735 | .name = "timer3", | |
736 | .clkdm_name = "alwon_l3s_clkdm", | |
737 | .main_clk = "timer3_fck", | |
738 | .prcm = { | |
739 | .omap4 = { | |
740 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, | |
741 | .modulemode = MODULEMODE_SWCTRL, | |
742 | }, | |
743 | }, | |
744 | .dev_attr = &capability_alwon_dev_attr, | |
745 | .class = &dm816x_timer_hwmod_class, | |
746 | }; | |
747 | ||
748 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { | |
7e1b11d1 | 749 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
750 | .slave = &dm816x_timer3_hwmod, |
751 | .clk = "sysclk6_ck", | |
752 | .user = OCP_USER_MPU, | |
753 | }; | |
754 | ||
755 | static struct omap_hwmod dm816x_timer4_hwmod = { | |
756 | .name = "timer4", | |
757 | .clkdm_name = "alwon_l3s_clkdm", | |
758 | .main_clk = "timer4_fck", | |
759 | .prcm = { | |
760 | .omap4 = { | |
761 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, | |
762 | .modulemode = MODULEMODE_SWCTRL, | |
763 | }, | |
764 | }, | |
765 | .dev_attr = &capability_alwon_dev_attr, | |
766 | .class = &dm816x_timer_hwmod_class, | |
767 | }; | |
768 | ||
769 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { | |
7e1b11d1 | 770 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
771 | .slave = &dm816x_timer4_hwmod, |
772 | .clk = "sysclk6_ck", | |
773 | .user = OCP_USER_MPU, | |
774 | }; | |
775 | ||
776 | static struct omap_hwmod dm816x_timer5_hwmod = { | |
777 | .name = "timer5", | |
778 | .clkdm_name = "alwon_l3s_clkdm", | |
779 | .main_clk = "timer5_fck", | |
780 | .prcm = { | |
781 | .omap4 = { | |
782 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, | |
783 | .modulemode = MODULEMODE_SWCTRL, | |
784 | }, | |
785 | }, | |
786 | .dev_attr = &capability_alwon_dev_attr, | |
787 | .class = &dm816x_timer_hwmod_class, | |
788 | }; | |
789 | ||
790 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { | |
7e1b11d1 | 791 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
792 | .slave = &dm816x_timer5_hwmod, |
793 | .clk = "sysclk6_ck", | |
794 | .user = OCP_USER_MPU, | |
795 | }; | |
796 | ||
797 | static struct omap_hwmod dm816x_timer6_hwmod = { | |
798 | .name = "timer6", | |
799 | .clkdm_name = "alwon_l3s_clkdm", | |
800 | .main_clk = "timer6_fck", | |
801 | .prcm = { | |
802 | .omap4 = { | |
803 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, | |
804 | .modulemode = MODULEMODE_SWCTRL, | |
805 | }, | |
806 | }, | |
807 | .dev_attr = &capability_alwon_dev_attr, | |
808 | .class = &dm816x_timer_hwmod_class, | |
809 | }; | |
810 | ||
811 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { | |
7e1b11d1 | 812 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
813 | .slave = &dm816x_timer6_hwmod, |
814 | .clk = "sysclk6_ck", | |
815 | .user = OCP_USER_MPU, | |
816 | }; | |
817 | ||
818 | static struct omap_hwmod dm816x_timer7_hwmod = { | |
819 | .name = "timer7", | |
820 | .clkdm_name = "alwon_l3s_clkdm", | |
821 | .main_clk = "timer7_fck", | |
822 | .prcm = { | |
823 | .omap4 = { | |
824 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, | |
825 | .modulemode = MODULEMODE_SWCTRL, | |
826 | }, | |
827 | }, | |
828 | .dev_attr = &capability_alwon_dev_attr, | |
829 | .class = &dm816x_timer_hwmod_class, | |
830 | }; | |
831 | ||
832 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { | |
7e1b11d1 | 833 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
834 | .slave = &dm816x_timer7_hwmod, |
835 | .clk = "sysclk6_ck", | |
836 | .user = OCP_USER_MPU, | |
837 | }; | |
838 | ||
0f3ccb24 TL |
839 | /* CPSW on dm814x */ |
840 | static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { | |
841 | .rev_offs = 0x0, | |
842 | .sysc_offs = 0x8, | |
843 | .syss_offs = 0x4, | |
844 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
845 | SYSS_HAS_RESET_STATUS, | |
846 | .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
847 | MSTANDBY_NO, | |
848 | .sysc_fields = &omap_hwmod_sysc_type3, | |
849 | }; | |
850 | ||
851 | static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { | |
852 | .name = "cpgmac0", | |
853 | .sysc = &dm814x_cpgmac_sysc, | |
854 | }; | |
855 | ||
24da741c | 856 | static struct omap_hwmod dm814x_cpgmac0_hwmod = { |
0f3ccb24 TL |
857 | .name = "cpgmac0", |
858 | .class = &dm814x_cpgmac0_hwmod_class, | |
859 | .clkdm_name = "alwon_ethernet_clkdm", | |
860 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
861 | .main_clk = "cpsw_125mhz_gclk", | |
862 | .prcm = { | |
863 | .omap4 = { | |
864 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, | |
865 | .modulemode = MODULEMODE_SWCTRL, | |
866 | }, | |
867 | }, | |
868 | }; | |
869 | ||
870 | static struct omap_hwmod_class dm814x_mdio_hwmod_class = { | |
871 | .name = "davinci_mdio", | |
872 | }; | |
873 | ||
24da741c | 874 | static struct omap_hwmod dm814x_mdio_hwmod = { |
0f3ccb24 TL |
875 | .name = "davinci_mdio", |
876 | .class = &dm814x_mdio_hwmod_class, | |
877 | .clkdm_name = "alwon_ethernet_clkdm", | |
878 | .main_clk = "cpsw_125mhz_gclk", | |
879 | }; | |
880 | ||
881 | static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { | |
882 | .master = &dm81xx_l4_hs_hwmod, | |
883 | .slave = &dm814x_cpgmac0_hwmod, | |
884 | .clk = "cpsw_125mhz_gclk", | |
885 | .user = OCP_USER_MPU, | |
886 | }; | |
887 | ||
24da741c | 888 | static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { |
0f3ccb24 TL |
889 | .master = &dm814x_cpgmac0_hwmod, |
890 | .slave = &dm814x_mdio_hwmod, | |
891 | .user = OCP_USER_MPU, | |
892 | .flags = HWMOD_NO_IDLEST, | |
893 | }; | |
894 | ||
4d38bd12 TL |
895 | /* EMAC Ethernet */ |
896 | static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { | |
897 | .rev_offs = 0x0, | |
898 | .sysc_offs = 0x4, | |
899 | .sysc_flags = SYSC_HAS_SOFTRESET, | |
900 | .sysc_fields = &omap_hwmod_sysc_type2, | |
901 | }; | |
902 | ||
903 | static struct omap_hwmod_class dm816x_emac_hwmod_class = { | |
904 | .name = "emac", | |
905 | .sysc = &dm816x_emac_sysc, | |
906 | }; | |
907 | ||
908 | /* | |
909 | * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate | |
910 | * driver probed before EMAC0, we let MDIO do the clock idling. | |
911 | */ | |
912 | static struct omap_hwmod dm816x_emac0_hwmod = { | |
913 | .name = "emac0", | |
914 | .clkdm_name = "alwon_ethernet_clkdm", | |
915 | .class = &dm816x_emac_hwmod_class, | |
29f5b34c | 916 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
917 | }; |
918 | ||
7e1b11d1 TL |
919 | static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { |
920 | .master = &dm81xx_l4_hs_hwmod, | |
4d38bd12 TL |
921 | .slave = &dm816x_emac0_hwmod, |
922 | .clk = "sysclk5_ck", | |
923 | .user = OCP_USER_MPU, | |
924 | }; | |
925 | ||
7e1b11d1 | 926 | static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { |
4d38bd12 TL |
927 | .name = "davinci_mdio", |
928 | .sysc = &dm816x_emac_sysc, | |
929 | }; | |
930 | ||
24da741c | 931 | static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { |
4d38bd12 | 932 | .name = "davinci_mdio", |
7e1b11d1 | 933 | .class = &dm81xx_mdio_hwmod_class, |
4d38bd12 TL |
934 | .clkdm_name = "alwon_ethernet_clkdm", |
935 | .main_clk = "sysclk24_ck", | |
936 | .flags = HWMOD_NO_IDLEST, | |
937 | /* | |
938 | * REVISIT: This should be moved to the emac0_hwmod | |
939 | * once we have a better way to handle device slaves. | |
940 | */ | |
941 | .prcm = { | |
942 | .omap4 = { | |
7e1b11d1 | 943 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, |
4d38bd12 TL |
944 | .modulemode = MODULEMODE_SWCTRL, |
945 | }, | |
946 | }, | |
947 | }; | |
948 | ||
24da741c | 949 | static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { |
7e1b11d1 TL |
950 | .master = &dm81xx_l4_hs_hwmod, |
951 | .slave = &dm81xx_emac0_mdio_hwmod, | |
4d38bd12 TL |
952 | .user = OCP_USER_MPU, |
953 | }; | |
954 | ||
955 | static struct omap_hwmod dm816x_emac1_hwmod = { | |
956 | .name = "emac1", | |
957 | .clkdm_name = "alwon_ethernet_clkdm", | |
958 | .main_clk = "sysclk24_ck", | |
959 | .flags = HWMOD_NO_IDLEST, | |
960 | .prcm = { | |
961 | .omap4 = { | |
962 | .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, | |
963 | .modulemode = MODULEMODE_SWCTRL, | |
964 | }, | |
965 | }, | |
966 | .class = &dm816x_emac_hwmod_class, | |
967 | }; | |
968 | ||
969 | static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { | |
7e1b11d1 | 970 | .master = &dm81xx_l4_hs_hwmod, |
4d38bd12 TL |
971 | .slave = &dm816x_emac1_hwmod, |
972 | .clk = "sysclk5_ck", | |
973 | .user = OCP_USER_MPU, | |
974 | }; | |
975 | ||
c757fda8 | 976 | static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { |
4d38bd12 TL |
977 | .rev_offs = 0x0, |
978 | .sysc_offs = 0x110, | |
979 | .syss_offs = 0x114, | |
980 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
981 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
982 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
983 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
984 | .sysc_fields = &omap_hwmod_sysc_type1, | |
985 | }; | |
986 | ||
c757fda8 | 987 | static struct omap_hwmod_class dm81xx_mmc_class = { |
4d38bd12 | 988 | .name = "mmc", |
c757fda8 | 989 | .sysc = &dm81xx_mmc_sysc, |
4d38bd12 TL |
990 | }; |
991 | ||
c757fda8 | 992 | static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { |
4d38bd12 TL |
993 | { .role = "dbck", .clk = "sysclk18_ck", }, |
994 | }; | |
995 | ||
c757fda8 TL |
996 | static struct omap_hsmmc_dev_attr mmc_dev_attr = { |
997 | }; | |
998 | ||
999 | static struct omap_hwmod dm814x_mmc1_hwmod = { | |
1000 | .name = "mmc1", | |
1001 | .clkdm_name = "alwon_l3s_clkdm", | |
1002 | .opt_clks = dm81xx_mmc_opt_clks, | |
1003 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
1004 | .main_clk = "sysclk8_ck", | |
1005 | .prcm = { | |
1006 | .omap4 = { | |
1007 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, | |
1008 | .modulemode = MODULEMODE_SWCTRL, | |
1009 | }, | |
1010 | }, | |
1011 | .dev_attr = &mmc_dev_attr, | |
1012 | .class = &dm81xx_mmc_class, | |
1013 | }; | |
1014 | ||
1015 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { | |
1016 | .master = &dm81xx_l4_ls_hwmod, | |
1017 | .slave = &dm814x_mmc1_hwmod, | |
1018 | .clk = "sysclk6_ck", | |
1019 | .user = OCP_USER_MPU, | |
1020 | .flags = OMAP_FIREWALL_L4 | |
1021 | }; | |
1022 | ||
1023 | static struct omap_hwmod dm814x_mmc2_hwmod = { | |
1024 | .name = "mmc2", | |
1025 | .clkdm_name = "alwon_l3s_clkdm", | |
1026 | .opt_clks = dm81xx_mmc_opt_clks, | |
1027 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
1028 | .main_clk = "sysclk8_ck", | |
1029 | .prcm = { | |
1030 | .omap4 = { | |
1031 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, | |
1032 | .modulemode = MODULEMODE_SWCTRL, | |
1033 | }, | |
1034 | }, | |
1035 | .dev_attr = &mmc_dev_attr, | |
1036 | .class = &dm81xx_mmc_class, | |
1037 | }; | |
1038 | ||
1039 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { | |
1040 | .master = &dm81xx_l4_ls_hwmod, | |
1041 | .slave = &dm814x_mmc2_hwmod, | |
1042 | .clk = "sysclk6_ck", | |
1043 | .user = OCP_USER_MPU, | |
1044 | .flags = OMAP_FIREWALL_L4 | |
1045 | }; | |
1046 | ||
1047 | static struct omap_hwmod dm814x_mmc3_hwmod = { | |
1048 | .name = "mmc3", | |
1049 | .clkdm_name = "alwon_l3_med_clkdm", | |
1050 | .opt_clks = dm81xx_mmc_opt_clks, | |
1051 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
1052 | .main_clk = "sysclk8_ck", | |
1053 | .prcm = { | |
1054 | .omap4 = { | |
1055 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, | |
1056 | .modulemode = MODULEMODE_SWCTRL, | |
1057 | }, | |
1058 | }, | |
1059 | .dev_attr = &mmc_dev_attr, | |
1060 | .class = &dm81xx_mmc_class, | |
1061 | }; | |
1062 | ||
1063 | static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { | |
1064 | .master = &dm81xx_alwon_l3_med_hwmod, | |
1065 | .slave = &dm814x_mmc3_hwmod, | |
1066 | .clk = "sysclk4_ck", | |
1067 | .user = OCP_USER_MPU, | |
4d38bd12 TL |
1068 | }; |
1069 | ||
1070 | static struct omap_hwmod dm816x_mmc1_hwmod = { | |
1071 | .name = "mmc1", | |
1072 | .clkdm_name = "alwon_l3s_clkdm", | |
c757fda8 TL |
1073 | .opt_clks = dm81xx_mmc_opt_clks, |
1074 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
4d38bd12 TL |
1075 | .main_clk = "sysclk10_ck", |
1076 | .prcm = { | |
1077 | .omap4 = { | |
1078 | .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, | |
1079 | .modulemode = MODULEMODE_SWCTRL, | |
1080 | }, | |
1081 | }, | |
c757fda8 TL |
1082 | .dev_attr = &mmc_dev_attr, |
1083 | .class = &dm81xx_mmc_class, | |
4d38bd12 TL |
1084 | }; |
1085 | ||
1086 | static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { | |
7e1b11d1 | 1087 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
1088 | .slave = &dm816x_mmc1_hwmod, |
1089 | .clk = "sysclk6_ck", | |
1090 | .user = OCP_USER_MPU, | |
1091 | .flags = OMAP_FIREWALL_L4 | |
1092 | }; | |
1093 | ||
1094 | static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { | |
1095 | .rev_offs = 0x0, | |
1096 | .sysc_offs = 0x110, | |
1097 | .syss_offs = 0x114, | |
1098 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1099 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1100 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
1101 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1102 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1103 | }; | |
1104 | ||
1105 | static struct omap_hwmod_class dm816x_mcspi_class = { | |
1106 | .name = "mcspi", | |
1107 | .sysc = &dm816x_mcspi_sysc, | |
1108 | .rev = OMAP3_MCSPI_REV, | |
1109 | }; | |
1110 | ||
1111 | static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { | |
1112 | .num_chipselect = 4, | |
1113 | }; | |
1114 | ||
7e1b11d1 | 1115 | static struct omap_hwmod dm81xx_mcspi1_hwmod = { |
4d38bd12 TL |
1116 | .name = "mcspi1", |
1117 | .clkdm_name = "alwon_l3s_clkdm", | |
1118 | .main_clk = "sysclk10_ck", | |
1119 | .prcm = { | |
1120 | .omap4 = { | |
7e1b11d1 | 1121 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
4d38bd12 TL |
1122 | .modulemode = MODULEMODE_SWCTRL, |
1123 | }, | |
1124 | }, | |
1125 | .class = &dm816x_mcspi_class, | |
1126 | .dev_attr = &dm816x_mcspi1_dev_attr, | |
1127 | }; | |
1128 | ||
7e1b11d1 TL |
1129 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { |
1130 | .master = &dm81xx_l4_ls_hwmod, | |
1131 | .slave = &dm81xx_mcspi1_hwmod, | |
4d38bd12 TL |
1132 | .clk = "sysclk6_ck", |
1133 | .user = OCP_USER_MPU, | |
1134 | }; | |
1135 | ||
7e1b11d1 | 1136 | static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { |
4d38bd12 TL |
1137 | .rev_offs = 0x000, |
1138 | .sysc_offs = 0x010, | |
1139 | .syss_offs = 0x014, | |
1140 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1141 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, | |
1142 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1143 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1144 | }; | |
1145 | ||
7e1b11d1 | 1146 | static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { |
4d38bd12 | 1147 | .name = "mailbox", |
7e1b11d1 | 1148 | .sysc = &dm81xx_mailbox_sysc, |
4d38bd12 TL |
1149 | }; |
1150 | ||
7e1b11d1 | 1151 | static struct omap_hwmod dm81xx_mailbox_hwmod = { |
4d38bd12 TL |
1152 | .name = "mailbox", |
1153 | .clkdm_name = "alwon_l3s_clkdm", | |
7e1b11d1 | 1154 | .class = &dm81xx_mailbox_hwmod_class, |
4d38bd12 TL |
1155 | .main_clk = "sysclk6_ck", |
1156 | .prcm = { | |
1157 | .omap4 = { | |
7e1b11d1 | 1158 | .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, |
4d38bd12 TL |
1159 | .modulemode = MODULEMODE_SWCTRL, |
1160 | }, | |
1161 | }, | |
1162 | }; | |
1163 | ||
7e1b11d1 TL |
1164 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { |
1165 | .master = &dm81xx_l4_ls_hwmod, | |
1166 | .slave = &dm81xx_mailbox_hwmod, | |
4f5395f0 | 1167 | .clk = "sysclk6_ck", |
4d38bd12 TL |
1168 | .user = OCP_USER_MPU, |
1169 | }; | |
1170 | ||
1539569b NA |
1171 | static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { |
1172 | .rev_offs = 0x000, | |
1173 | .sysc_offs = 0x010, | |
1174 | .syss_offs = 0x014, | |
1175 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1176 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, | |
1177 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1178 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1179 | }; | |
1180 | ||
1181 | static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { | |
1182 | .name = "spinbox", | |
1183 | .sysc = &dm81xx_spinbox_sysc, | |
1184 | }; | |
1185 | ||
1186 | static struct omap_hwmod dm81xx_spinbox_hwmod = { | |
1187 | .name = "spinbox", | |
1188 | .clkdm_name = "alwon_l3s_clkdm", | |
1189 | .class = &dm81xx_spinbox_hwmod_class, | |
1190 | .main_clk = "sysclk6_ck", | |
1191 | .prcm = { | |
1192 | .omap4 = { | |
1193 | .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, | |
1194 | .modulemode = MODULEMODE_SWCTRL, | |
1195 | }, | |
1196 | }, | |
1197 | }; | |
1198 | ||
1199 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { | |
1200 | .master = &dm81xx_l4_ls_hwmod, | |
1201 | .slave = &dm81xx_spinbox_hwmod, | |
4f5395f0 | 1202 | .clk = "sysclk6_ck", |
1539569b NA |
1203 | .user = OCP_USER_MPU, |
1204 | }; | |
1205 | ||
7e1b11d1 | 1206 | static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { |
4d38bd12 TL |
1207 | .name = "tpcc", |
1208 | }; | |
1209 | ||
24da741c | 1210 | static struct omap_hwmod dm81xx_tpcc_hwmod = { |
4d38bd12 | 1211 | .name = "tpcc", |
7e1b11d1 | 1212 | .class = &dm81xx_tpcc_hwmod_class, |
4d38bd12 TL |
1213 | .clkdm_name = "alwon_l3s_clkdm", |
1214 | .main_clk = "sysclk4_ck", | |
1215 | .prcm = { | |
1216 | .omap4 = { | |
7e1b11d1 | 1217 | .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, |
4d38bd12 TL |
1218 | .modulemode = MODULEMODE_SWCTRL, |
1219 | }, | |
1220 | }, | |
1221 | }; | |
1222 | ||
24da741c | 1223 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { |
7e1b11d1 TL |
1224 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1225 | .slave = &dm81xx_tpcc_hwmod, | |
4d38bd12 TL |
1226 | .clk = "sysclk4_ck", |
1227 | .user = OCP_USER_MPU, | |
1228 | }; | |
1229 | ||
7e1b11d1 | 1230 | static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { |
4d38bd12 TL |
1231 | { |
1232 | .pa_start = 0x49800000, | |
1233 | .pa_end = 0x49800000 + SZ_8K - 1, | |
1234 | .flags = ADDR_TYPE_RT, | |
1235 | }, | |
1236 | { }, | |
1237 | }; | |
1238 | ||
7e1b11d1 | 1239 | static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { |
4d38bd12 TL |
1240 | .name = "tptc0", |
1241 | }; | |
1242 | ||
24da741c | 1243 | static struct omap_hwmod dm81xx_tptc0_hwmod = { |
4d38bd12 | 1244 | .name = "tptc0", |
7e1b11d1 | 1245 | .class = &dm81xx_tptc0_hwmod_class, |
4d38bd12 TL |
1246 | .clkdm_name = "alwon_l3s_clkdm", |
1247 | .main_clk = "sysclk4_ck", | |
1248 | .prcm = { | |
1249 | .omap4 = { | |
7e1b11d1 | 1250 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, |
4d38bd12 TL |
1251 | .modulemode = MODULEMODE_SWCTRL, |
1252 | }, | |
1253 | }, | |
1254 | }; | |
1255 | ||
24da741c | 1256 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { |
7e1b11d1 TL |
1257 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1258 | .slave = &dm81xx_tptc0_hwmod, | |
4d38bd12 | 1259 | .clk = "sysclk4_ck", |
7e1b11d1 | 1260 | .addr = dm81xx_tptc0_addr_space, |
4d38bd12 TL |
1261 | .user = OCP_USER_MPU, |
1262 | }; | |
1263 | ||
24da741c | 1264 | static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { |
7e1b11d1 TL |
1265 | .master = &dm81xx_tptc0_hwmod, |
1266 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1267 | .clk = "sysclk4_ck", |
7e1b11d1 | 1268 | .addr = dm81xx_tptc0_addr_space, |
4d38bd12 TL |
1269 | .user = OCP_USER_MPU, |
1270 | }; | |
1271 | ||
7e1b11d1 | 1272 | static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { |
4d38bd12 TL |
1273 | { |
1274 | .pa_start = 0x49900000, | |
1275 | .pa_end = 0x49900000 + SZ_8K - 1, | |
1276 | .flags = ADDR_TYPE_RT, | |
1277 | }, | |
1278 | { }, | |
1279 | }; | |
1280 | ||
7e1b11d1 | 1281 | static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { |
4d38bd12 TL |
1282 | .name = "tptc1", |
1283 | }; | |
1284 | ||
24da741c | 1285 | static struct omap_hwmod dm81xx_tptc1_hwmod = { |
4d38bd12 | 1286 | .name = "tptc1", |
7e1b11d1 | 1287 | .class = &dm81xx_tptc1_hwmod_class, |
4d38bd12 TL |
1288 | .clkdm_name = "alwon_l3s_clkdm", |
1289 | .main_clk = "sysclk4_ck", | |
1290 | .prcm = { | |
1291 | .omap4 = { | |
7e1b11d1 | 1292 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, |
4d38bd12 TL |
1293 | .modulemode = MODULEMODE_SWCTRL, |
1294 | }, | |
1295 | }, | |
1296 | }; | |
1297 | ||
24da741c | 1298 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { |
7e1b11d1 TL |
1299 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1300 | .slave = &dm81xx_tptc1_hwmod, | |
4d38bd12 | 1301 | .clk = "sysclk4_ck", |
7e1b11d1 | 1302 | .addr = dm81xx_tptc1_addr_space, |
4d38bd12 TL |
1303 | .user = OCP_USER_MPU, |
1304 | }; | |
1305 | ||
24da741c | 1306 | static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { |
7e1b11d1 TL |
1307 | .master = &dm81xx_tptc1_hwmod, |
1308 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1309 | .clk = "sysclk4_ck", |
7e1b11d1 | 1310 | .addr = dm81xx_tptc1_addr_space, |
4d38bd12 TL |
1311 | .user = OCP_USER_MPU, |
1312 | }; | |
1313 | ||
7e1b11d1 | 1314 | static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { |
4d38bd12 TL |
1315 | { |
1316 | .pa_start = 0x49a00000, | |
1317 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
1318 | .flags = ADDR_TYPE_RT, | |
1319 | }, | |
1320 | { }, | |
1321 | }; | |
1322 | ||
7e1b11d1 | 1323 | static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { |
4d38bd12 TL |
1324 | .name = "tptc2", |
1325 | }; | |
1326 | ||
24da741c | 1327 | static struct omap_hwmod dm81xx_tptc2_hwmod = { |
4d38bd12 | 1328 | .name = "tptc2", |
7e1b11d1 | 1329 | .class = &dm81xx_tptc2_hwmod_class, |
4d38bd12 TL |
1330 | .clkdm_name = "alwon_l3s_clkdm", |
1331 | .main_clk = "sysclk4_ck", | |
1332 | .prcm = { | |
1333 | .omap4 = { | |
7e1b11d1 | 1334 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, |
4d38bd12 TL |
1335 | .modulemode = MODULEMODE_SWCTRL, |
1336 | }, | |
1337 | }, | |
1338 | }; | |
1339 | ||
24da741c | 1340 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { |
7e1b11d1 TL |
1341 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1342 | .slave = &dm81xx_tptc2_hwmod, | |
4d38bd12 | 1343 | .clk = "sysclk4_ck", |
7e1b11d1 | 1344 | .addr = dm81xx_tptc2_addr_space, |
4d38bd12 TL |
1345 | .user = OCP_USER_MPU, |
1346 | }; | |
1347 | ||
24da741c | 1348 | static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { |
7e1b11d1 TL |
1349 | .master = &dm81xx_tptc2_hwmod, |
1350 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1351 | .clk = "sysclk4_ck", |
7e1b11d1 | 1352 | .addr = dm81xx_tptc2_addr_space, |
4d38bd12 TL |
1353 | .user = OCP_USER_MPU, |
1354 | }; | |
1355 | ||
7e1b11d1 | 1356 | static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { |
4d38bd12 TL |
1357 | { |
1358 | .pa_start = 0x49b00000, | |
1359 | .pa_end = 0x49b00000 + SZ_8K - 1, | |
1360 | .flags = ADDR_TYPE_RT, | |
1361 | }, | |
1362 | { }, | |
1363 | }; | |
1364 | ||
7e1b11d1 | 1365 | static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { |
4d38bd12 TL |
1366 | .name = "tptc3", |
1367 | }; | |
1368 | ||
24da741c | 1369 | static struct omap_hwmod dm81xx_tptc3_hwmod = { |
4d38bd12 | 1370 | .name = "tptc3", |
7e1b11d1 | 1371 | .class = &dm81xx_tptc3_hwmod_class, |
4d38bd12 TL |
1372 | .clkdm_name = "alwon_l3s_clkdm", |
1373 | .main_clk = "sysclk4_ck", | |
1374 | .prcm = { | |
1375 | .omap4 = { | |
7e1b11d1 | 1376 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, |
4d38bd12 TL |
1377 | .modulemode = MODULEMODE_SWCTRL, |
1378 | }, | |
1379 | }, | |
1380 | }; | |
1381 | ||
24da741c | 1382 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { |
7e1b11d1 TL |
1383 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1384 | .slave = &dm81xx_tptc3_hwmod, | |
4d38bd12 | 1385 | .clk = "sysclk4_ck", |
7e1b11d1 | 1386 | .addr = dm81xx_tptc3_addr_space, |
4d38bd12 TL |
1387 | .user = OCP_USER_MPU, |
1388 | }; | |
1389 | ||
24da741c | 1390 | static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { |
7e1b11d1 TL |
1391 | .master = &dm81xx_tptc3_hwmod, |
1392 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1393 | .clk = "sysclk4_ck", |
7e1b11d1 | 1394 | .addr = dm81xx_tptc3_addr_space, |
4d38bd12 TL |
1395 | .user = OCP_USER_MPU, |
1396 | }; | |
1397 | ||
0f3ccb24 TL |
1398 | /* |
1399 | * REVISIT: Test and enable the following once clocks work: | |
0f3ccb24 | 1400 | * dm81xx_l4_ls__mailbox |
0f3ccb24 TL |
1401 | * |
1402 | * Also note that some devices share a single clkctrl_offs.. | |
1403 | * For example, i2c1 and 3 share one, and i2c2 and 4 share one. | |
1404 | */ | |
1405 | static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { | |
1406 | &dm814x_mpu__alwon_l3_slow, | |
1407 | &dm814x_mpu__alwon_l3_med, | |
1408 | &dm81xx_alwon_l3_slow__l4_ls, | |
1409 | &dm81xx_alwon_l3_slow__l4_hs, | |
1410 | &dm81xx_l4_ls__uart1, | |
1411 | &dm81xx_l4_ls__uart2, | |
1412 | &dm81xx_l4_ls__uart3, | |
1413 | &dm81xx_l4_ls__wd_timer1, | |
1414 | &dm81xx_l4_ls__i2c1, | |
1415 | &dm81xx_l4_ls__i2c2, | |
3022b29d TL |
1416 | &dm81xx_l4_ls__gpio1, |
1417 | &dm81xx_l4_ls__gpio2, | |
0f3ccb24 TL |
1418 | &dm81xx_l4_ls__elm, |
1419 | &dm81xx_l4_ls__mcspi1, | |
c757fda8 TL |
1420 | &dm814x_l4_ls__mmc1, |
1421 | &dm814x_l4_ls__mmc2, | |
c5803246 | 1422 | &ti81xx_l4_ls__rtc, |
0f3ccb24 TL |
1423 | &dm81xx_alwon_l3_fast__tpcc, |
1424 | &dm81xx_alwon_l3_fast__tptc0, | |
1425 | &dm81xx_alwon_l3_fast__tptc1, | |
1426 | &dm81xx_alwon_l3_fast__tptc2, | |
1427 | &dm81xx_alwon_l3_fast__tptc3, | |
1428 | &dm81xx_tptc0__alwon_l3_fast, | |
1429 | &dm81xx_tptc1__alwon_l3_fast, | |
1430 | &dm81xx_tptc2__alwon_l3_fast, | |
1431 | &dm81xx_tptc3__alwon_l3_fast, | |
1432 | &dm814x_l4_ls__timer1, | |
1433 | &dm814x_l4_ls__timer2, | |
1434 | &dm814x_l4_hs__cpgmac0, | |
1435 | &dm814x_cpgmac0__mdio, | |
f53850b5 TL |
1436 | &dm81xx_alwon_l3_slow__gpmc, |
1437 | &dm814x_default_l3_slow__usbss, | |
c757fda8 | 1438 | &dm814x_alwon_l3_med__mmc3, |
0f3ccb24 TL |
1439 | NULL, |
1440 | }; | |
1441 | ||
1442 | int __init dm814x_hwmod_init(void) | |
1443 | { | |
1444 | omap_hwmod_init(); | |
1445 | return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); | |
1446 | } | |
1447 | ||
4d38bd12 TL |
1448 | static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { |
1449 | &dm816x_mpu__alwon_l3_slow, | |
1450 | &dm816x_mpu__alwon_l3_med, | |
7e1b11d1 TL |
1451 | &dm81xx_alwon_l3_slow__l4_ls, |
1452 | &dm81xx_alwon_l3_slow__l4_hs, | |
1453 | &dm81xx_l4_ls__uart1, | |
1454 | &dm81xx_l4_ls__uart2, | |
1455 | &dm81xx_l4_ls__uart3, | |
1456 | &dm81xx_l4_ls__wd_timer1, | |
1457 | &dm81xx_l4_ls__i2c1, | |
1458 | &dm81xx_l4_ls__i2c2, | |
4d38bd12 TL |
1459 | &dm81xx_l4_ls__gpio1, |
1460 | &dm81xx_l4_ls__gpio2, | |
1461 | &dm81xx_l4_ls__elm, | |
c5803246 | 1462 | &ti81xx_l4_ls__rtc, |
4d38bd12 TL |
1463 | &dm816x_l4_ls__mmc1, |
1464 | &dm816x_l4_ls__timer1, | |
1465 | &dm816x_l4_ls__timer2, | |
1466 | &dm816x_l4_ls__timer3, | |
1467 | &dm816x_l4_ls__timer4, | |
1468 | &dm816x_l4_ls__timer5, | |
1469 | &dm816x_l4_ls__timer6, | |
1470 | &dm816x_l4_ls__timer7, | |
7e1b11d1 TL |
1471 | &dm81xx_l4_ls__mcspi1, |
1472 | &dm81xx_l4_ls__mailbox, | |
1539569b | 1473 | &dm81xx_l4_ls__spinbox, |
7e1b11d1 TL |
1474 | &dm81xx_l4_hs__emac0, |
1475 | &dm81xx_emac0__mdio, | |
4d38bd12 | 1476 | &dm816x_l4_hs__emac1, |
7e1b11d1 TL |
1477 | &dm81xx_alwon_l3_fast__tpcc, |
1478 | &dm81xx_alwon_l3_fast__tptc0, | |
1479 | &dm81xx_alwon_l3_fast__tptc1, | |
1480 | &dm81xx_alwon_l3_fast__tptc2, | |
1481 | &dm81xx_alwon_l3_fast__tptc3, | |
1482 | &dm81xx_tptc0__alwon_l3_fast, | |
1483 | &dm81xx_tptc1__alwon_l3_fast, | |
1484 | &dm81xx_tptc2__alwon_l3_fast, | |
1485 | &dm81xx_tptc3__alwon_l3_fast, | |
4d38bd12 | 1486 | &dm81xx_alwon_l3_slow__gpmc, |
f53850b5 | 1487 | &dm816x_default_l3_slow__usbss, |
4d38bd12 TL |
1488 | NULL, |
1489 | }; | |
1490 | ||
0f3ccb24 | 1491 | int __init dm816x_hwmod_init(void) |
4d38bd12 TL |
1492 | { |
1493 | omap_hwmod_init(); | |
1494 | return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); | |
1495 | } |