projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision
[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
905a74d9 27#include <plat/mcspi.h>
cb7e9ded 28#include <plat/mcbsp.h>
6ab8946f 29#include <plat/mmc.h>
55d2cb08
BC		 30
31#include "omap_hwmod_common_data.h"
32
d198b514
PW		 33#include "cm1_44xx.h"
34#include "cm2_44xx.h"
35#include "prm44xx.h"
55d2cb08 36#include "prm-regbits-44xx.h"
ff2516fb 37#include "wd_timer.h"
55d2cb08
BC		 38
39/* Base offset for all OMAP4 interrupts external to MPUSS */
40#define OMAP44XX_IRQ_GIC_START 32
41
42/* Base offset for all OMAP4 dma requests */
43#define OMAP44XX_DMA_REQ_START 1
44
45/* Backward references (IPs with Bus Master capability) */
407a6888 46static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 47static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 48static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 49static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 50static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 51static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 52static struct omap_hwmod omap44xx_hsi_hwmod;
53static struct omap_hwmod omap44xx_ipu_hwmod;
54static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 55static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 56static struct omap_hwmod omap44xx_l3_instr_hwmod;
57static struct omap_hwmod omap44xx_l3_main_1_hwmod;
58static struct omap_hwmod omap44xx_l3_main_2_hwmod;
59static struct omap_hwmod omap44xx_l3_main_3_hwmod;
60static struct omap_hwmod omap44xx_l4_abe_hwmod;
61static struct omap_hwmod omap44xx_l4_cfg_hwmod;
62static struct omap_hwmod omap44xx_l4_per_hwmod;
63static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 64static struct omap_hwmod omap44xx_mmc1_hwmod;
65static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 66static struct omap_hwmod omap44xx_mpu_hwmod;
67static struct omap_hwmod omap44xx_mpu_private_hwmod;
5844c4ea 68static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
55d2cb08
BC		 69
70/*
71 * Interconnects omap_hwmod structures
72 * hwmods that compose the global OMAP interconnect
73 */
74
75/*
76 * 'dmm' class
77 * instance(s): dmm
78 */
79static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 80 .name = "dmm",
55d2cb08
BC		 81};
82
7e69ed97
BC		 83/* dmm */
84static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86 { .irq = -1 }
87};
88
55d2cb08
BC		 89/* l3_main_1 -> dmm */
90static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
91 .master = &omap44xx_l3_main_1_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
93 .clk = "l3_div_ck",
659fa822
BC		 94 .user = OCP_USER_SDMA,
95};
96
97static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
98 {
99 .pa_start = 0x4e000000,
100 .pa_end = 0x4e0007ff,
101 .flags = ADDR_TYPE_RT
102 },
78183f3f 103 { }
55d2cb08
BC		 104};
105
106/* mpu -> dmm */
107static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
108 .master = &omap44xx_mpu_hwmod,
109 .slave = &omap44xx_dmm_hwmod,
110 .clk = "l3_div_ck",
659fa822 111 .addr = omap44xx_dmm_addrs,
659fa822 112 .user = OCP_USER_MPU,
55d2cb08
BC		 113};
114
115/* dmm slave ports */
116static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
117 &omap44xx_l3_main_1__dmm,
118 &omap44xx_mpu__dmm,
119};
120
55d2cb08
BC		 121static struct omap_hwmod omap44xx_dmm_hwmod = {
122 .name = "dmm",
123 .class = &omap44xx_dmm_hwmod_class,
7e69ed97 124 .mpu_irqs = omap44xx_dmm_irqs,
55d2cb08
BC		 125 .slaves = omap44xx_dmm_slaves,
126 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
55d2cb08
BC		 127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
128};
129
130/*
131 * 'emif_fw' class
132 * instance(s): emif_fw
133 */
134static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 135 .name = "emif_fw",
55d2cb08
BC		 136};
137
7e69ed97 138/* emif_fw */
55d2cb08
BC		 139/* dmm -> emif_fw */
140static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
141 .master = &omap44xx_dmm_hwmod,
142 .slave = &omap44xx_emif_fw_hwmod,
143 .clk = "l3_div_ck",
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145};
146
659fa822
BC		 147static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
148 {
149 .pa_start = 0x4a20c000,
150 .pa_end = 0x4a20c0ff,
151 .flags = ADDR_TYPE_RT
152 },
78183f3f 153 { }
659fa822
BC		 154};
155
55d2cb08
BC		 156/* l4_cfg -> emif_fw */
157static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
158 .master = &omap44xx_l4_cfg_hwmod,
159 .slave = &omap44xx_emif_fw_hwmod,
160 .clk = "l4_div_ck",
659fa822 161 .addr = omap44xx_emif_fw_addrs,
659fa822 162 .user = OCP_USER_MPU,
55d2cb08
BC		 163};
164
165/* emif_fw slave ports */
166static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
167 &omap44xx_dmm__emif_fw,
168 &omap44xx_l4_cfg__emif_fw,
169};
170
171static struct omap_hwmod omap44xx_emif_fw_hwmod = {
172 .name = "emif_fw",
173 .class = &omap44xx_emif_fw_hwmod_class,
174 .slaves = omap44xx_emif_fw_slaves,
175 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
177};
178
179/*
180 * 'l3' class
181 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
182 */
183static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 184 .name = "l3",
55d2cb08
BC		 185};
186
7e69ed97 187/* l3_instr */
8f25bdc5
BC		 188/* iva -> l3_instr */
189static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
190 .master = &omap44xx_iva_hwmod,
191 .slave = &omap44xx_l3_instr_hwmod,
192 .clk = "l3_div_ck",
193 .user = OCP_USER_MPU | OCP_USER_SDMA,
194};
195
55d2cb08
BC		 196/* l3_main_3 -> l3_instr */
197static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
198 .master = &omap44xx_l3_main_3_hwmod,
199 .slave = &omap44xx_l3_instr_hwmod,
200 .clk = "l3_div_ck",
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202};
203
204/* l3_instr slave ports */
205static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 206 &omap44xx_iva__l3_instr,
55d2cb08
BC		 207 &omap44xx_l3_main_3__l3_instr,
208};
209
210static struct omap_hwmod omap44xx_l3_instr_hwmod = {
211 .name = "l3_instr",
212 .class = &omap44xx_l3_hwmod_class,
213 .slaves = omap44xx_l3_instr_slaves,
214 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216};
217
7e69ed97 218/* l3_main_1 */
9b4021be
BC		 219static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
220 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
221 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
222 { .irq = -1 }
223};
224
8f25bdc5
BC		 225/* dsp -> l3_main_1 */
226static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
227 .master = &omap44xx_dsp_hwmod,
228 .slave = &omap44xx_l3_main_1_hwmod,
229 .clk = "l3_div_ck",
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
d63bd74f
BC		 233/* dss -> l3_main_1 */
234static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
235 .master = &omap44xx_dss_hwmod,
236 .slave = &omap44xx_l3_main_1_hwmod,
237 .clk = "l3_div_ck",
238 .user = OCP_USER_MPU | OCP_USER_SDMA,
239};
240
55d2cb08
BC		 241/* l3_main_2 -> l3_main_1 */
242static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
243 .master = &omap44xx_l3_main_2_hwmod,
244 .slave = &omap44xx_l3_main_1_hwmod,
245 .clk = "l3_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247};
248
249/* l4_cfg -> l3_main_1 */
250static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
251 .master = &omap44xx_l4_cfg_hwmod,
252 .slave = &omap44xx_l3_main_1_hwmod,
253 .clk = "l4_div_ck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255};
256
407a6888
BC		 257/* mmc1 -> l3_main_1 */
258static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
259 .master = &omap44xx_mmc1_hwmod,
260 .slave = &omap44xx_l3_main_1_hwmod,
261 .clk = "l3_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
265/* mmc2 -> l3_main_1 */
266static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
267 .master = &omap44xx_mmc2_hwmod,
268 .slave = &omap44xx_l3_main_1_hwmod,
269 .clk = "l3_div_ck",
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
271};
272
c4645234 273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
9b4021be 277 .flags = ADDR_TYPE_RT
c4645234 278 },
78183f3f 279 { }
c4645234 280};
281
55d2cb08
BC		 282/* mpu -> l3_main_1 */
283static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
284 .master = &omap44xx_mpu_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
286 .clk = "l3_div_ck",
c4645234 287 .addr = omap44xx_l3_main_1_addrs,
9b4021be 288 .user = OCP_USER_MPU,
55d2cb08
BC		 289};
290
291/* l3_main_1 slave ports */
292static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 293 &omap44xx_dsp__l3_main_1,
d63bd74f 294 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 295 &omap44xx_l3_main_2__l3_main_1,
296 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 297 &omap44xx_mmc1__l3_main_1,
298 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 299 &omap44xx_mpu__l3_main_1,
300};
301
302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
303 .name = "l3_main_1",
304 .class = &omap44xx_l3_hwmod_class,
7e69ed97 305 .mpu_irqs = omap44xx_l3_main_1_irqs,
55d2cb08
BC		 306 .slaves = omap44xx_l3_main_1_slaves,
307 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
308 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
309};
310
7e69ed97 311/* l3_main_2 */
d7cf5f33
BC		 312/* dma_system -> l3_main_2 */
313static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
314 .master = &omap44xx_dma_system_hwmod,
315 .slave = &omap44xx_l3_main_2_hwmod,
316 .clk = "l3_div_ck",
317 .user = OCP_USER_MPU | OCP_USER_SDMA,
318};
319
407a6888
BC		 320/* hsi -> l3_main_2 */
321static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
322 .master = &omap44xx_hsi_hwmod,
323 .slave = &omap44xx_l3_main_2_hwmod,
324 .clk = "l3_div_ck",
325 .user = OCP_USER_MPU | OCP_USER_SDMA,
326};
327
328/* ipu -> l3_main_2 */
329static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
330 .master = &omap44xx_ipu_hwmod,
331 .slave = &omap44xx_l3_main_2_hwmod,
332 .clk = "l3_div_ck",
333 .user = OCP_USER_MPU | OCP_USER_SDMA,
334};
335
336/* iss -> l3_main_2 */
337static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
338 .master = &omap44xx_iss_hwmod,
339 .slave = &omap44xx_l3_main_2_hwmod,
340 .clk = "l3_div_ck",
341 .user = OCP_USER_MPU | OCP_USER_SDMA,
342};
343
8f25bdc5
BC		 344/* iva -> l3_main_2 */
345static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
346 .master = &omap44xx_iva_hwmod,
347 .slave = &omap44xx_l3_main_2_hwmod,
348 .clk = "l3_div_ck",
349 .user = OCP_USER_MPU | OCP_USER_SDMA,
350};
351
c4645234 352static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
353 {
354 .pa_start = 0x44800000,
355 .pa_end = 0x44801fff,
9b4021be 356 .flags = ADDR_TYPE_RT
c4645234 357 },
78183f3f 358 { }
c4645234 359};
360
55d2cb08
BC		 361/* l3_main_1 -> l3_main_2 */
362static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
363 .master = &omap44xx_l3_main_1_hwmod,
364 .slave = &omap44xx_l3_main_2_hwmod,
365 .clk = "l3_div_ck",
c4645234 366 .addr = omap44xx_l3_main_2_addrs,
9b4021be 367 .user = OCP_USER_MPU,
55d2cb08
BC		 368};
369
370/* l4_cfg -> l3_main_2 */
371static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
372 .master = &omap44xx_l4_cfg_hwmod,
373 .slave = &omap44xx_l3_main_2_hwmod,
374 .clk = "l4_div_ck",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
5844c4ea
BC		 378/* usb_otg_hs -> l3_main_2 */
379static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
380 .master = &omap44xx_usb_otg_hs_hwmod,
381 .slave = &omap44xx_l3_main_2_hwmod,
382 .clk = "l3_div_ck",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384};
385
55d2cb08
BC		 386/* l3_main_2 slave ports */
387static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 388 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 389 &omap44xx_hsi__l3_main_2,
390 &omap44xx_ipu__l3_main_2,
391 &omap44xx_iss__l3_main_2,
8f25bdc5 392 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 393 &omap44xx_l3_main_1__l3_main_2,
394 &omap44xx_l4_cfg__l3_main_2,
5844c4ea 395 &omap44xx_usb_otg_hs__l3_main_2,
55d2cb08
BC		 396};
397
398static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
399 .name = "l3_main_2",
400 .class = &omap44xx_l3_hwmod_class,
401 .slaves = omap44xx_l3_main_2_slaves,
402 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
403 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
404};
405
7e69ed97 406/* l3_main_3 */
c4645234 407static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
408 {
409 .pa_start = 0x45000000,
410 .pa_end = 0x45000fff,
9b4021be 411 .flags = ADDR_TYPE_RT
c4645234 412 },
78183f3f 413 { }
c4645234 414};
415
55d2cb08
BC		 416/* l3_main_1 -> l3_main_3 */
417static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
418 .master = &omap44xx_l3_main_1_hwmod,
419 .slave = &omap44xx_l3_main_3_hwmod,
420 .clk = "l3_div_ck",
c4645234 421 .addr = omap44xx_l3_main_3_addrs,
9b4021be 422 .user = OCP_USER_MPU,
55d2cb08
BC		 423};
424
425/* l3_main_2 -> l3_main_3 */
426static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
427 .master = &omap44xx_l3_main_2_hwmod,
428 .slave = &omap44xx_l3_main_3_hwmod,
429 .clk = "l3_div_ck",
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
433/* l4_cfg -> l3_main_3 */
434static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
435 .master = &omap44xx_l4_cfg_hwmod,
436 .slave = &omap44xx_l3_main_3_hwmod,
437 .clk = "l4_div_ck",
438 .user = OCP_USER_MPU | OCP_USER_SDMA,
439};
440
441/* l3_main_3 slave ports */
442static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
443 &omap44xx_l3_main_1__l3_main_3,
444 &omap44xx_l3_main_2__l3_main_3,
445 &omap44xx_l4_cfg__l3_main_3,
446};
447
448static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
449 .name = "l3_main_3",
450 .class = &omap44xx_l3_hwmod_class,
451 .slaves = omap44xx_l3_main_3_slaves,
452 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
454};
455
456/*
457 * 'l4' class
458 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
459 */
460static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 461 .name = "l4",
55d2cb08
BC		 462};
463
7e69ed97 464/* l4_abe */
407a6888
BC		 465/* aess -> l4_abe */
466static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
467 .master = &omap44xx_aess_hwmod,
468 .slave = &omap44xx_l4_abe_hwmod,
469 .clk = "ocp_abe_iclk",
470 .user = OCP_USER_MPU | OCP_USER_SDMA,
471};
472
8f25bdc5
BC		 473/* dsp -> l4_abe */
474static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
475 .master = &omap44xx_dsp_hwmod,
476 .slave = &omap44xx_l4_abe_hwmod,
477 .clk = "ocp_abe_iclk",
478 .user = OCP_USER_MPU | OCP_USER_SDMA,
479};
480
55d2cb08
BC		 481/* l3_main_1 -> l4_abe */
482static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
483 .master = &omap44xx_l3_main_1_hwmod,
484 .slave = &omap44xx_l4_abe_hwmod,
485 .clk = "l3_div_ck",
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* mpu -> l4_abe */
490static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
491 .master = &omap44xx_mpu_hwmod,
492 .slave = &omap44xx_l4_abe_hwmod,
493 .clk = "ocp_abe_iclk",
494 .user = OCP_USER_MPU | OCP_USER_SDMA,
495};
496
497/* l4_abe slave ports */
498static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 499 &omap44xx_aess__l4_abe,
8f25bdc5 500 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 501 &omap44xx_l3_main_1__l4_abe,
502 &omap44xx_mpu__l4_abe,
503};
504
505static struct omap_hwmod omap44xx_l4_abe_hwmod = {
506 .name = "l4_abe",
507 .class = &omap44xx_l4_hwmod_class,
508 .slaves = omap44xx_l4_abe_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
511};
512
7e69ed97 513/* l4_cfg */
55d2cb08
BC		 514/* l3_main_1 -> l4_cfg */
515static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
516 .master = &omap44xx_l3_main_1_hwmod,
517 .slave = &omap44xx_l4_cfg_hwmod,
518 .clk = "l3_div_ck",
519 .user = OCP_USER_MPU | OCP_USER_SDMA,
520};
521
522/* l4_cfg slave ports */
523static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
524 &omap44xx_l3_main_1__l4_cfg,
525};
526
527static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
528 .name = "l4_cfg",
529 .class = &omap44xx_l4_hwmod_class,
530 .slaves = omap44xx_l4_cfg_slaves,
531 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
533};
534
7e69ed97 535/* l4_per */
55d2cb08
BC		 536/* l3_main_2 -> l4_per */
537static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
538 .master = &omap44xx_l3_main_2_hwmod,
539 .slave = &omap44xx_l4_per_hwmod,
540 .clk = "l3_div_ck",
541 .user = OCP_USER_MPU | OCP_USER_SDMA,
542};
543
544/* l4_per slave ports */
545static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
546 &omap44xx_l3_main_2__l4_per,
547};
548
549static struct omap_hwmod omap44xx_l4_per_hwmod = {
550 .name = "l4_per",
551 .class = &omap44xx_l4_hwmod_class,
552 .slaves = omap44xx_l4_per_slaves,
553 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
555};
556
7e69ed97 557/* l4_wkup */
55d2cb08
BC		 558/* l4_cfg -> l4_wkup */
559static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
560 .master = &omap44xx_l4_cfg_hwmod,
561 .slave = &omap44xx_l4_wkup_hwmod,
562 .clk = "l4_div_ck",
563 .user = OCP_USER_MPU | OCP_USER_SDMA,
564};
565
566/* l4_wkup slave ports */
567static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
568 &omap44xx_l4_cfg__l4_wkup,
569};
570
571static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
572 .name = "l4_wkup",
573 .class = &omap44xx_l4_hwmod_class,
574 .slaves = omap44xx_l4_wkup_slaves,
575 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577};
578
f776471f 579/*
3b54baad
BC		 580 * 'mpu_bus' class
581 * instance(s): mpu_private
f776471f 582 */
3b54baad 583static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 584 .name = "mpu_bus",
3b54baad 585};
f776471f 586
7e69ed97 587/* mpu_private */
3b54baad
BC		 588/* mpu -> mpu_private */
589static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
590 .master = &omap44xx_mpu_hwmod,
591 .slave = &omap44xx_mpu_private_hwmod,
592 .clk = "l3_div_ck",
593 .user = OCP_USER_MPU | OCP_USER_SDMA,
594};
595
596/* mpu_private slave ports */
597static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
598 &omap44xx_mpu__mpu_private,
599};
600
601static struct omap_hwmod omap44xx_mpu_private_hwmod = {
602 .name = "mpu_private",
603 .class = &omap44xx_mpu_bus_hwmod_class,
604 .slaves = omap44xx_mpu_private_slaves,
605 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
606 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
607};
608
609/*
610 * Modules omap_hwmod structures
611 *
612 * The following IPs are excluded for the moment because:
613 * - They do not need an explicit SW control using omap_hwmod API.
614 * - They still need to be validated with the driver
615 * properly adapted to omap_hwmod / omap_device
616 *
3b54baad
BC		 617 * c2c
618 * c2c_target_fw
619 * cm_core
620 * cm_core_aon
3b54baad
BC		 621 * ctrl_module_core
622 * ctrl_module_pad_core
623 * ctrl_module_pad_wkup
624 * ctrl_module_wkup
625 * debugss
3b54baad
BC		 626 * efuse_ctrl_cust
627 * efuse_ctrl_std
628 * elm
629 * emif1
630 * emif2
631 * fdif
632 * gpmc
633 * gpu
634 * hdq1w
00fe610b
BC		 635 * mcasp
636 * mpu_c0
637 * mpu_c1
3b54baad
BC		 638 * ocmc_ram
639 * ocp2scp_usb_phy
640 * ocp_wp_noc
3b54baad
BC		 641 * prcm_mpu
642 * prm
643 * scrm
644 * sl2if
645 * slimbus1
646 * slimbus2
3b54baad
BC		 647 * usb_host_fs
648 * usb_host_hs
3b54baad
BC		 649 * usb_phy_cm
650 * usb_tll_hs
651 * usim
652 */
653
407a6888
BC		 654/*
655 * 'aess' class
656 * audio engine sub system
657 */
658
659static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
660 .rev_offs = 0x0000,
661 .sysc_offs = 0x0010,
662 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
663 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
c614ebf6
BC		 664 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
665 MSTANDBY_SMART_WKUP),
407a6888
BC		 666 .sysc_fields = &omap_hwmod_sysc_type2,
667};
668
669static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
670 .name = "aess",
671 .sysc = &omap44xx_aess_sysc,
672};
673
674/* aess */
675static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
676 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
212738a4 677 { .irq = -1 }
407a6888
BC		 678};
679
680static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
681 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
682 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
683 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
684 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
685 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
686 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
687 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
688 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
bc614958 689 { .dma_req = -1 }
407a6888
BC		 690};
691
692/* aess master ports */
693static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
694 &omap44xx_aess__l4_abe,
695};
696
697static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
698 {
699 .pa_start = 0x401f1000,
700 .pa_end = 0x401f13ff,
701 .flags = ADDR_TYPE_RT
702 },
78183f3f 703 { }
407a6888
BC		 704};
705
706/* l4_abe -> aess */
707static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
708 .master = &omap44xx_l4_abe_hwmod,
709 .slave = &omap44xx_aess_hwmod,
710 .clk = "ocp_abe_iclk",
711 .addr = omap44xx_aess_addrs,
407a6888
BC		 712 .user = OCP_USER_MPU,
713};
714
715static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
716 {
717 .pa_start = 0x490f1000,
718 .pa_end = 0x490f13ff,
719 .flags = ADDR_TYPE_RT
720 },
78183f3f 721 { }
407a6888
BC		 722};
723
724/* l4_abe -> aess (dma) */
725static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
726 .master = &omap44xx_l4_abe_hwmod,
727 .slave = &omap44xx_aess_hwmod,
728 .clk = "ocp_abe_iclk",
729 .addr = omap44xx_aess_dma_addrs,
407a6888
BC		 730 .user = OCP_USER_SDMA,
731};
732
733/* aess slave ports */
734static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
735 &omap44xx_l4_abe__aess,
736 &omap44xx_l4_abe__aess_dma,
737};
738
739static struct omap_hwmod omap44xx_aess_hwmod = {
740 .name = "aess",
741 .class = &omap44xx_aess_hwmod_class,
742 .mpu_irqs = omap44xx_aess_irqs,
407a6888 743 .sdma_reqs = omap44xx_aess_sdma_reqs,
407a6888 744 .main_clk = "aess_fck",
00fe610b 745 .prcm = {
407a6888
BC		 746 .omap4 = {
747 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
748 },
749 },
750 .slaves = omap44xx_aess_slaves,
751 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
752 .masters = omap44xx_aess_masters,
753 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
755};
756
757/*
758 * 'bandgap' class
759 * bangap reference for ldo regulators
760 */
761
762static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
763 .name = "bandgap",
764};
765
766/* bandgap */
767static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
768 { .role = "fclk", .clk = "bandgap_fclk" },
769};
770
771static struct omap_hwmod omap44xx_bandgap_hwmod = {
772 .name = "bandgap",
773 .class = &omap44xx_bandgap_hwmod_class,
00fe610b 774 .prcm = {
407a6888
BC		 775 .omap4 = {
776 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
777 },
778 },
779 .opt_clks = bandgap_opt_clks,
780 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
781 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
782};
783
784/*
785 * 'counter' class
786 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
787 */
788
789static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
790 .rev_offs = 0x0000,
791 .sysc_offs = 0x0004,
792 .sysc_flags = SYSC_HAS_SIDLEMODE,
793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
794 SIDLE_SMART_WKUP),
795 .sysc_fields = &omap_hwmod_sysc_type1,
796};
797
798static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
799 .name = "counter",
800 .sysc = &omap44xx_counter_sysc,
801};
802
803/* counter_32k */
804static struct omap_hwmod omap44xx_counter_32k_hwmod;
805static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
806 {
807 .pa_start = 0x4a304000,
808 .pa_end = 0x4a30401f,
809 .flags = ADDR_TYPE_RT
810 },
78183f3f 811 { }
407a6888
BC		 812};
813
814/* l4_wkup -> counter_32k */
815static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
816 .master = &omap44xx_l4_wkup_hwmod,
817 .slave = &omap44xx_counter_32k_hwmod,
818 .clk = "l4_wkup_clk_mux_ck",
819 .addr = omap44xx_counter_32k_addrs,
407a6888
BC		 820 .user = OCP_USER_MPU | OCP_USER_SDMA,
821};
822
823/* counter_32k slave ports */
824static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
825 &omap44xx_l4_wkup__counter_32k,
826};
827
828static struct omap_hwmod omap44xx_counter_32k_hwmod = {
829 .name = "counter_32k",
830 .class = &omap44xx_counter_hwmod_class,
831 .flags = HWMOD_SWSUP_SIDLE,
832 .main_clk = "sys_32k_ck",
00fe610b 833 .prcm = {
407a6888
BC		 834 .omap4 = {
835 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
836 },
837 },
838 .slaves = omap44xx_counter_32k_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
840 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
841};
842
d7cf5f33
BC		 843/*
844 * 'dma' class
845 * dma controller for data exchange between memory to memory (i.e. internal or
846 * external memory) and gp peripherals to memory or memory to gp peripherals
847 */
848
849static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
850 .rev_offs = 0x0000,
851 .sysc_offs = 0x002c,
852 .syss_offs = 0x0028,
853 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
854 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
855 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
856 SYSS_HAS_RESET_STATUS),
857 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
858 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
859 .sysc_fields = &omap_hwmod_sysc_type1,
860};
861
862static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
863 .name = "dma",
864 .sysc = &omap44xx_dma_sysc,
865};
866
867/* dma dev_attr */
868static struct omap_dma_dev_attr dma_dev_attr = {
869 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
870 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
871 .lch_count = 32,
872};
873
874/* dma_system */
875static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
876 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
877 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
878 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
879 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
212738a4 880 { .irq = -1 }
d7cf5f33
BC		 881};
882
883/* dma_system master ports */
884static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
885 &omap44xx_dma_system__l3_main_2,
886};
887
888static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
889 {
890 .pa_start = 0x4a056000,
1286eeb2 891 .pa_end = 0x4a056fff,
d7cf5f33
BC		 892 .flags = ADDR_TYPE_RT
893 },
78183f3f 894 { }
d7cf5f33
BC		 895};
896
897/* l4_cfg -> dma_system */
898static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
899 .master = &omap44xx_l4_cfg_hwmod,
900 .slave = &omap44xx_dma_system_hwmod,
901 .clk = "l4_div_ck",
902 .addr = omap44xx_dma_system_addrs,
d7cf5f33
BC		 903 .user = OCP_USER_MPU | OCP_USER_SDMA,
904};
905
906/* dma_system slave ports */
907static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
908 &omap44xx_l4_cfg__dma_system,
909};
910
911static struct omap_hwmod omap44xx_dma_system_hwmod = {
912 .name = "dma_system",
913 .class = &omap44xx_dma_hwmod_class,
914 .mpu_irqs = omap44xx_dma_system_irqs,
d7cf5f33
BC		 915 .main_clk = "l3_div_ck",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
919 },
920 },
921 .dev_attr = &dma_dev_attr,
922 .slaves = omap44xx_dma_system_slaves,
923 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
924 .masters = omap44xx_dma_system_masters,
925 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
926 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
927};
928
8ca476da
BC		 929/*
930 * 'dmic' class
931 * digital microphone controller
932 */
933
934static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
935 .rev_offs = 0x0000,
936 .sysc_offs = 0x0010,
937 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
938 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
939 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
940 SIDLE_SMART_WKUP),
941 .sysc_fields = &omap_hwmod_sysc_type2,
942};
943
944static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
945 .name = "dmic",
946 .sysc = &omap44xx_dmic_sysc,
947};
948
949/* dmic */
950static struct omap_hwmod omap44xx_dmic_hwmod;
951static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
952 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
212738a4 953 { .irq = -1 }
8ca476da
BC		 954};
955
956static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
957 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
bc614958 958 { .dma_req = -1 }
8ca476da
BC		 959};
960
961static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
962 {
963 .pa_start = 0x4012e000,
964 .pa_end = 0x4012e07f,
965 .flags = ADDR_TYPE_RT
966 },
78183f3f 967 { }
8ca476da
BC		 968};
969
970/* l4_abe -> dmic */
971static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
972 .master = &omap44xx_l4_abe_hwmod,
973 .slave = &omap44xx_dmic_hwmod,
974 .clk = "ocp_abe_iclk",
975 .addr = omap44xx_dmic_addrs,
8ca476da
BC		 976 .user = OCP_USER_MPU,
977};
978
979static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
980 {
981 .pa_start = 0x4902e000,
982 .pa_end = 0x4902e07f,
983 .flags = ADDR_TYPE_RT
984 },
78183f3f 985 { }
8ca476da
BC		 986};
987
988/* l4_abe -> dmic (dma) */
989static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
990 .master = &omap44xx_l4_abe_hwmod,
991 .slave = &omap44xx_dmic_hwmod,
992 .clk = "ocp_abe_iclk",
993 .addr = omap44xx_dmic_dma_addrs,
8ca476da
BC		 994 .user = OCP_USER_SDMA,
995};
996
997/* dmic slave ports */
998static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
999 &omap44xx_l4_abe__dmic,
1000 &omap44xx_l4_abe__dmic_dma,
1001};
1002
1003static struct omap_hwmod omap44xx_dmic_hwmod = {
1004 .name = "dmic",
1005 .class = &omap44xx_dmic_hwmod_class,
1006 .mpu_irqs = omap44xx_dmic_irqs,
8ca476da 1007 .sdma_reqs = omap44xx_dmic_sdma_reqs,
8ca476da 1008 .main_clk = "dmic_fck",
00fe610b 1009 .prcm = {
8ca476da
BC		 1010 .omap4 = {
1011 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1012 },
1013 },
1014 .slaves = omap44xx_dmic_slaves,
1015 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1017};
1018
8f25bdc5
BC		 1019/*
1020 * 'dsp' class
1021 * dsp sub-system
1022 */
1023
1024static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 1025 .name = "dsp",
8f25bdc5
BC		 1026};
1027
1028/* dsp */
1029static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1030 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
212738a4 1031 { .irq = -1 }
8f25bdc5
BC		 1032};
1033
1034static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1035 { .name = "mmu_cache", .rst_shift = 1 },
1036};
1037
1038static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1039 { .name = "dsp", .rst_shift = 0 },
1040};
1041
1042/* dsp -> iva */
1043static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1044 .master = &omap44xx_dsp_hwmod,
1045 .slave = &omap44xx_iva_hwmod,
1046 .clk = "dpll_iva_m5x2_ck",
1047};
1048
1049/* dsp master ports */
1050static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1051 &omap44xx_dsp__l3_main_1,
1052 &omap44xx_dsp__l4_abe,
1053 &omap44xx_dsp__iva,
1054};
1055
1056/* l4_cfg -> dsp */
1057static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1058 .master = &omap44xx_l4_cfg_hwmod,
1059 .slave = &omap44xx_dsp_hwmod,
1060 .clk = "l4_div_ck",
1061 .user = OCP_USER_MPU | OCP_USER_SDMA,
1062};
1063
1064/* dsp slave ports */
1065static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1066 &omap44xx_l4_cfg__dsp,
1067};
1068
1069/* Pseudo hwmod for reset control purpose only */
1070static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1071 .name = "dsp_c0",
1072 .class = &omap44xx_dsp_hwmod_class,
1073 .flags = HWMOD_INIT_NO_RESET,
1074 .rst_lines = omap44xx_dsp_c0_resets,
1075 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1076 .prcm = {
1077 .omap4 = {
1078 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1079 },
1080 },
1081 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1082};
1083
1084static struct omap_hwmod omap44xx_dsp_hwmod = {
1085 .name = "dsp",
1086 .class = &omap44xx_dsp_hwmod_class,
1087 .mpu_irqs = omap44xx_dsp_irqs,
8f25bdc5
BC		 1088 .rst_lines = omap44xx_dsp_resets,
1089 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1090 .main_clk = "dsp_fck",
1091 .prcm = {
1092 .omap4 = {
1093 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1094 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1095 },
1096 },
1097 .slaves = omap44xx_dsp_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1099 .masters = omap44xx_dsp_masters,
1100 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1102};
1103
d63bd74f
BC		 1104/*
1105 * 'dss' class
1106 * display sub-system
1107 */
1108
1109static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1110 .rev_offs = 0x0000,
1111 .syss_offs = 0x0014,
1112 .sysc_flags = SYSS_HAS_RESET_STATUS,
1113};
1114
1115static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1116 .name = "dss",
1117 .sysc = &omap44xx_dss_sysc,
1118};
1119
1120/* dss */
1121/* dss master ports */
1122static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1123 &omap44xx_dss__l3_main_1,
1124};
1125
1126static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1127 {
1128 .pa_start = 0x58000000,
1129 .pa_end = 0x5800007f,
1130 .flags = ADDR_TYPE_RT
1131 },
78183f3f 1132 { }
d63bd74f
BC		 1133};
1134
1135/* l3_main_2 -> dss */
1136static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1137 .master = &omap44xx_l3_main_2_hwmod,
1138 .slave = &omap44xx_dss_hwmod,
da7cdfac 1139 .clk = "dss_fck",
d63bd74f 1140 .addr = omap44xx_dss_dma_addrs,
d63bd74f
BC		 1141 .user = OCP_USER_SDMA,
1142};
1143
1144static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1145 {
1146 .pa_start = 0x48040000,
1147 .pa_end = 0x4804007f,
1148 .flags = ADDR_TYPE_RT
1149 },
78183f3f 1150 { }
d63bd74f
BC		 1151};
1152
1153/* l4_per -> dss */
1154static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1155 .master = &omap44xx_l4_per_hwmod,
1156 .slave = &omap44xx_dss_hwmod,
1157 .clk = "l4_div_ck",
1158 .addr = omap44xx_dss_addrs,
d63bd74f
BC		 1159 .user = OCP_USER_MPU,
1160};
1161
1162/* dss slave ports */
1163static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1164 &omap44xx_l3_main_2__dss,
1165 &omap44xx_l4_per__dss,
1166};
1167
1168static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1169 { .role = "sys_clk", .clk = "dss_sys_clk" },
1170 { .role = "tv_clk", .clk = "dss_tv_clk" },
1171 { .role = "dss_clk", .clk = "dss_dss_clk" },
1172 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1173};
1174
1175static struct omap_hwmod omap44xx_dss_hwmod = {
1176 .name = "dss_core",
1177 .class = &omap44xx_dss_hwmod_class,
da7cdfac 1178 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1179 .prcm = {
1180 .omap4 = {
1181 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1182 },
1183 },
1184 .opt_clks = dss_opt_clks,
1185 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1186 .slaves = omap44xx_dss_slaves,
1187 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1188 .masters = omap44xx_dss_masters,
1189 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191};
1192
1193/*
1194 * 'dispc' class
1195 * display controller
1196 */
1197
1198static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1199 .rev_offs = 0x0000,
1200 .sysc_offs = 0x0010,
1201 .syss_offs = 0x0014,
1202 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1203 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1205 SYSS_HAS_RESET_STATUS),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1208 .sysc_fields = &omap_hwmod_sysc_type1,
1209};
1210
1211static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1212 .name = "dispc",
1213 .sysc = &omap44xx_dispc_sysc,
1214};
1215
1216/* dss_dispc */
1217static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1218static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1219 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
212738a4 1220 { .irq = -1 }
d63bd74f
BC		 1221};
1222
1223static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1224 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
bc614958 1225 { .dma_req = -1 }
d63bd74f
BC		 1226};
1227
1228static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1229 {
1230 .pa_start = 0x58001000,
1231 .pa_end = 0x58001fff,
1232 .flags = ADDR_TYPE_RT
1233 },
78183f3f 1234 { }
d63bd74f
BC		 1235};
1236
1237/* l3_main_2 -> dss_dispc */
1238static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1239 .master = &omap44xx_l3_main_2_hwmod,
1240 .slave = &omap44xx_dss_dispc_hwmod,
da7cdfac 1241 .clk = "dss_fck",
d63bd74f 1242 .addr = omap44xx_dss_dispc_dma_addrs,
d63bd74f
BC		 1243 .user = OCP_USER_SDMA,
1244};
1245
1246static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1247 {
1248 .pa_start = 0x48041000,
1249 .pa_end = 0x48041fff,
1250 .flags = ADDR_TYPE_RT
1251 },
78183f3f 1252 { }
d63bd74f
BC		 1253};
1254
1255/* l4_per -> dss_dispc */
1256static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1257 .master = &omap44xx_l4_per_hwmod,
1258 .slave = &omap44xx_dss_dispc_hwmod,
1259 .clk = "l4_div_ck",
1260 .addr = omap44xx_dss_dispc_addrs,
d63bd74f
BC		 1261 .user = OCP_USER_MPU,
1262};
1263
1264/* dss_dispc slave ports */
1265static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1266 &omap44xx_l3_main_2__dss_dispc,
1267 &omap44xx_l4_per__dss_dispc,
1268};
1269
3a23aafc
TV		 1270static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1271 { .role = "sys_clk", .clk = "dss_sys_clk" },
1272 { .role = "tv_clk", .clk = "dss_tv_clk" },
1273 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1274};
1275
d63bd74f
BC		 1276static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1277 .name = "dss_dispc",
1278 .class = &omap44xx_dispc_hwmod_class,
3a23aafc 1279 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
d63bd74f 1280 .mpu_irqs = omap44xx_dss_dispc_irqs,
d63bd74f 1281 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
da7cdfac 1282 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1283 .prcm = {
1284 .omap4 = {
1285 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1286 },
1287 },
3a23aafc
TV		 1288 .opt_clks = dss_dispc_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
d63bd74f
BC		 1290 .slaves = omap44xx_dss_dispc_slaves,
1291 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1292 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1293};
1294
1295/*
1296 * 'dsi' class
1297 * display serial interface controller
1298 */
1299
1300static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1301 .rev_offs = 0x0000,
1302 .sysc_offs = 0x0010,
1303 .syss_offs = 0x0014,
1304 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1305 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1306 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308 .sysc_fields = &omap_hwmod_sysc_type1,
1309};
1310
1311static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1312 .name = "dsi",
1313 .sysc = &omap44xx_dsi_sysc,
1314};
1315
1316/* dss_dsi1 */
1317static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1318static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1319 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
212738a4 1320 { .irq = -1 }
d63bd74f
BC		 1321};
1322
1323static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1324 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
bc614958 1325 { .dma_req = -1 }
d63bd74f
BC		 1326};
1327
1328static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1329 {
1330 .pa_start = 0x58004000,
1331 .pa_end = 0x580041ff,
1332 .flags = ADDR_TYPE_RT
1333 },
78183f3f 1334 { }
d63bd74f
BC		 1335};
1336
1337/* l3_main_2 -> dss_dsi1 */
1338static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1339 .master = &omap44xx_l3_main_2_hwmod,
1340 .slave = &omap44xx_dss_dsi1_hwmod,
da7cdfac 1341 .clk = "dss_fck",
d63bd74f 1342 .addr = omap44xx_dss_dsi1_dma_addrs,
d63bd74f
BC		 1343 .user = OCP_USER_SDMA,
1344};
1345
1346static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1347 {
1348 .pa_start = 0x48044000,
1349 .pa_end = 0x480441ff,
1350 .flags = ADDR_TYPE_RT
1351 },
78183f3f 1352 { }
d63bd74f
BC		 1353};
1354
1355/* l4_per -> dss_dsi1 */
1356static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1357 .master = &omap44xx_l4_per_hwmod,
1358 .slave = &omap44xx_dss_dsi1_hwmod,
1359 .clk = "l4_div_ck",
1360 .addr = omap44xx_dss_dsi1_addrs,
d63bd74f
BC		 1361 .user = OCP_USER_MPU,
1362};
1363
1364/* dss_dsi1 slave ports */
1365static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1366 &omap44xx_l3_main_2__dss_dsi1,
1367 &omap44xx_l4_per__dss_dsi1,
1368};
1369
3a23aafc
TV		 1370static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1371 { .role = "sys_clk", .clk = "dss_sys_clk" },
1372};
1373
d63bd74f
BC		 1374static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1375 .name = "dss_dsi1",
1376 .class = &omap44xx_dsi_hwmod_class,
1377 .mpu_irqs = omap44xx_dss_dsi1_irqs,
d63bd74f 1378 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
da7cdfac 1379 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1383 },
1384 },
3a23aafc
TV		 1385 .opt_clks = dss_dsi1_opt_clks,
1386 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
d63bd74f
BC		 1387 .slaves = omap44xx_dss_dsi1_slaves,
1388 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1390};
1391
1392/* dss_dsi2 */
1393static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1394static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1395 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
212738a4 1396 { .irq = -1 }
d63bd74f
BC		 1397};
1398
1399static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1400 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
bc614958 1401 { .dma_req = -1 }
d63bd74f
BC		 1402};
1403
1404static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1405 {
1406 .pa_start = 0x58005000,
1407 .pa_end = 0x580051ff,
1408 .flags = ADDR_TYPE_RT
1409 },
78183f3f 1410 { }
d63bd74f
BC		 1411};
1412
1413/* l3_main_2 -> dss_dsi2 */
1414static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1415 .master = &omap44xx_l3_main_2_hwmod,
1416 .slave = &omap44xx_dss_dsi2_hwmod,
da7cdfac 1417 .clk = "dss_fck",
d63bd74f 1418 .addr = omap44xx_dss_dsi2_dma_addrs,
d63bd74f
BC		 1419 .user = OCP_USER_SDMA,
1420};
1421
1422static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1423 {
1424 .pa_start = 0x48045000,
1425 .pa_end = 0x480451ff,
1426 .flags = ADDR_TYPE_RT
1427 },
78183f3f 1428 { }
d63bd74f
BC		 1429};
1430
1431/* l4_per -> dss_dsi2 */
1432static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1433 .master = &omap44xx_l4_per_hwmod,
1434 .slave = &omap44xx_dss_dsi2_hwmod,
1435 .clk = "l4_div_ck",
1436 .addr = omap44xx_dss_dsi2_addrs,
d63bd74f
BC		 1437 .user = OCP_USER_MPU,
1438};
1439
1440/* dss_dsi2 slave ports */
1441static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1442 &omap44xx_l3_main_2__dss_dsi2,
1443 &omap44xx_l4_per__dss_dsi2,
1444};
1445
3a23aafc
TV		 1446static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1447 { .role = "sys_clk", .clk = "dss_sys_clk" },
1448};
1449
d63bd74f
BC		 1450static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1451 .name = "dss_dsi2",
1452 .class = &omap44xx_dsi_hwmod_class,
1453 .mpu_irqs = omap44xx_dss_dsi2_irqs,
d63bd74f 1454 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
da7cdfac 1455 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1456 .prcm = {
1457 .omap4 = {
1458 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1459 },
1460 },
3a23aafc
TV		 1461 .opt_clks = dss_dsi2_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
d63bd74f
BC		 1463 .slaves = omap44xx_dss_dsi2_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1465 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1466};
1467
1468/*
1469 * 'hdmi' class
1470 * hdmi controller
1471 */
1472
1473static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1474 .rev_offs = 0x0000,
1475 .sysc_offs = 0x0010,
1476 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1477 SYSC_HAS_SOFTRESET),
1478 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1479 SIDLE_SMART_WKUP),
1480 .sysc_fields = &omap_hwmod_sysc_type2,
1481};
1482
1483static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1484 .name = "hdmi",
1485 .sysc = &omap44xx_hdmi_sysc,
1486};
1487
1488/* dss_hdmi */
1489static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1490static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1491 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
212738a4 1492 { .irq = -1 }
d63bd74f
BC		 1493};
1494
1495static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1496 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
bc614958 1497 { .dma_req = -1 }
d63bd74f
BC		 1498};
1499
1500static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1501 {
1502 .pa_start = 0x58006000,
1503 .pa_end = 0x58006fff,
1504 .flags = ADDR_TYPE_RT
1505 },
78183f3f 1506 { }
d63bd74f
BC		 1507};
1508
1509/* l3_main_2 -> dss_hdmi */
1510static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1511 .master = &omap44xx_l3_main_2_hwmod,
1512 .slave = &omap44xx_dss_hdmi_hwmod,
da7cdfac 1513 .clk = "dss_fck",
d63bd74f 1514 .addr = omap44xx_dss_hdmi_dma_addrs,
d63bd74f
BC		 1515 .user = OCP_USER_SDMA,
1516};
1517
1518static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1519 {
1520 .pa_start = 0x48046000,
1521 .pa_end = 0x48046fff,
1522 .flags = ADDR_TYPE_RT
1523 },
78183f3f 1524 { }
d63bd74f
BC		 1525};
1526
1527/* l4_per -> dss_hdmi */
1528static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1529 .master = &omap44xx_l4_per_hwmod,
1530 .slave = &omap44xx_dss_hdmi_hwmod,
1531 .clk = "l4_div_ck",
1532 .addr = omap44xx_dss_hdmi_addrs,
d63bd74f
BC		 1533 .user = OCP_USER_MPU,
1534};
1535
1536/* dss_hdmi slave ports */
1537static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1538 &omap44xx_l3_main_2__dss_hdmi,
1539 &omap44xx_l4_per__dss_hdmi,
1540};
1541
3a23aafc
TV		 1542static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1543 { .role = "sys_clk", .clk = "dss_sys_clk" },
1544};
1545
d63bd74f
BC		 1546static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1547 .name = "dss_hdmi",
1548 .class = &omap44xx_hdmi_hwmod_class,
1549 .mpu_irqs = omap44xx_dss_hdmi_irqs,
d63bd74f 1550 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
da7cdfac 1551 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1552 .prcm = {
1553 .omap4 = {
1554 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1555 },
1556 },
3a23aafc
TV		 1557 .opt_clks = dss_hdmi_opt_clks,
1558 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
d63bd74f
BC		 1559 .slaves = omap44xx_dss_hdmi_slaves,
1560 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1562};
1563
1564/*
1565 * 'rfbi' class
1566 * remote frame buffer interface
1567 */
1568
1569static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1570 .rev_offs = 0x0000,
1571 .sysc_offs = 0x0010,
1572 .syss_offs = 0x0014,
1573 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1574 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1575 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1576 .sysc_fields = &omap_hwmod_sysc_type1,
1577};
1578
1579static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1580 .name = "rfbi",
1581 .sysc = &omap44xx_rfbi_sysc,
1582};
1583
1584/* dss_rfbi */
1585static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1586static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1587 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
bc614958 1588 { .dma_req = -1 }
d63bd74f
BC		 1589};
1590
1591static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1592 {
1593 .pa_start = 0x58002000,
1594 .pa_end = 0x580020ff,
1595 .flags = ADDR_TYPE_RT
1596 },
78183f3f 1597 { }
d63bd74f
BC		 1598};
1599
1600/* l3_main_2 -> dss_rfbi */
1601static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1602 .master = &omap44xx_l3_main_2_hwmod,
1603 .slave = &omap44xx_dss_rfbi_hwmod,
da7cdfac 1604 .clk = "dss_fck",
d63bd74f 1605 .addr = omap44xx_dss_rfbi_dma_addrs,
d63bd74f
BC		 1606 .user = OCP_USER_SDMA,
1607};
1608
1609static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1610 {
1611 .pa_start = 0x48042000,
1612 .pa_end = 0x480420ff,
1613 .flags = ADDR_TYPE_RT
1614 },
78183f3f 1615 { }
d63bd74f
BC		 1616};
1617
1618/* l4_per -> dss_rfbi */
1619static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1620 .master = &omap44xx_l4_per_hwmod,
1621 .slave = &omap44xx_dss_rfbi_hwmod,
1622 .clk = "l4_div_ck",
1623 .addr = omap44xx_dss_rfbi_addrs,
d63bd74f
BC		 1624 .user = OCP_USER_MPU,
1625};
1626
1627/* dss_rfbi slave ports */
1628static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1629 &omap44xx_l3_main_2__dss_rfbi,
1630 &omap44xx_l4_per__dss_rfbi,
1631};
1632
3a23aafc
TV		 1633static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1634 { .role = "ick", .clk = "dss_fck" },
1635};
1636
d63bd74f
BC		 1637static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1638 .name = "dss_rfbi",
1639 .class = &omap44xx_rfbi_hwmod_class,
1640 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
da7cdfac 1641 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1645 },
1646 },
3a23aafc
TV		 1647 .opt_clks = dss_rfbi_opt_clks,
1648 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
d63bd74f
BC		 1649 .slaves = omap44xx_dss_rfbi_slaves,
1650 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1651 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1652};
1653
1654/*
1655 * 'venc' class
1656 * video encoder
1657 */
1658
1659static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1660 .name = "venc",
1661};
1662
1663/* dss_venc */
1664static struct omap_hwmod omap44xx_dss_venc_hwmod;
1665static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1666 {
1667 .pa_start = 0x58003000,
1668 .pa_end = 0x580030ff,
1669 .flags = ADDR_TYPE_RT
1670 },
78183f3f 1671 { }
d63bd74f
BC		 1672};
1673
1674/* l3_main_2 -> dss_venc */
1675static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1676 .master = &omap44xx_l3_main_2_hwmod,
1677 .slave = &omap44xx_dss_venc_hwmod,
da7cdfac 1678 .clk = "dss_fck",
d63bd74f 1679 .addr = omap44xx_dss_venc_dma_addrs,
d63bd74f
BC		 1680 .user = OCP_USER_SDMA,
1681};
1682
1683static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1684 {
1685 .pa_start = 0x48043000,
1686 .pa_end = 0x480430ff,
1687 .flags = ADDR_TYPE_RT
1688 },
78183f3f 1689 { }
d63bd74f
BC		 1690};
1691
1692/* l4_per -> dss_venc */
1693static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1694 .master = &omap44xx_l4_per_hwmod,
1695 .slave = &omap44xx_dss_venc_hwmod,
1696 .clk = "l4_div_ck",
1697 .addr = omap44xx_dss_venc_addrs,
d63bd74f
BC		 1698 .user = OCP_USER_MPU,
1699};
1700
1701/* dss_venc slave ports */
1702static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1703 &omap44xx_l3_main_2__dss_venc,
1704 &omap44xx_l4_per__dss_venc,
1705};
1706
1707static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1708 .name = "dss_venc",
1709 .class = &omap44xx_venc_hwmod_class,
da7cdfac 1710 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1711 .prcm = {
1712 .omap4 = {
1713 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1714 },
1715 },
1716 .slaves = omap44xx_dss_venc_slaves,
1717 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1718 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1719};
1720
3b54baad
BC		 1721/*
1722 * 'gpio' class
1723 * general purpose io module
1724 */
1725
1726static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1727 .rev_offs = 0x0000,
f776471f 1728 .sysc_offs = 0x0010,
3b54baad 1729 .syss_offs = 0x0114,
0cfe8751
BC		 1730 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1731 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1732 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1734 SIDLE_SMART_WKUP),
f776471f
BC		 1735 .sysc_fields = &omap_hwmod_sysc_type1,
1736};
1737
3b54baad 1738static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1739 .name = "gpio",
1740 .sysc = &omap44xx_gpio_sysc,
1741 .rev = 2,
f776471f
BC		 1742};
1743
3b54baad
BC		 1744/* gpio dev_attr */
1745static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1746 .bank_width = 32,
1747 .dbck_flag = true,
f776471f
BC		 1748};
1749
3b54baad
BC		 1750/* gpio1 */
1751static struct omap_hwmod omap44xx_gpio1_hwmod;
1752static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1753 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
212738a4 1754 { .irq = -1 }
f776471f
BC		 1755};
1756
3b54baad 1757static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1758 {
3b54baad
BC		 1759 .pa_start = 0x4a310000,
1760 .pa_end = 0x4a3101ff,
f776471f
BC		 1761 .flags = ADDR_TYPE_RT
1762 },
78183f3f 1763 { }
f776471f
BC		 1764};
1765
3b54baad
BC		 1766/* l4_wkup -> gpio1 */
1767static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1768 .master = &omap44xx_l4_wkup_hwmod,
1769 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1770 .clk = "l4_wkup_clk_mux_ck",
3b54baad 1771 .addr = omap44xx_gpio1_addrs,
f776471f
BC		 1772 .user = OCP_USER_MPU | OCP_USER_SDMA,
1773};
1774
3b54baad
BC		 1775/* gpio1 slave ports */
1776static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1777 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1778};
1779
3b54baad 1780static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1781 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1782};
1783
1784static struct omap_hwmod omap44xx_gpio1_hwmod = {
1785 .name = "gpio1",
1786 .class = &omap44xx_gpio_hwmod_class,
1787 .mpu_irqs = omap44xx_gpio1_irqs,
3b54baad 1788 .main_clk = "gpio1_ick",
f776471f
BC		 1789 .prcm = {
1790 .omap4 = {
3b54baad 1791 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1792 },
1793 },
3b54baad
BC		 1794 .opt_clks = gpio1_opt_clks,
1795 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1796 .dev_attr = &gpio_dev_attr,
1797 .slaves = omap44xx_gpio1_slaves,
1798 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1799 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1800};
1801
3b54baad
BC		 1802/* gpio2 */
1803static struct omap_hwmod omap44xx_gpio2_hwmod;
1804static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1805 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
212738a4 1806 { .irq = -1 }
f776471f
BC		 1807};
1808
3b54baad 1809static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1810 {
3b54baad
BC		 1811 .pa_start = 0x48055000,
1812 .pa_end = 0x480551ff,
f776471f
BC		 1813 .flags = ADDR_TYPE_RT
1814 },
78183f3f 1815 { }
f776471f
BC		 1816};
1817
3b54baad
BC		 1818/* l4_per -> gpio2 */
1819static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1820 .master = &omap44xx_l4_per_hwmod,
3b54baad 1821 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1822 .clk = "l4_div_ck",
3b54baad 1823 .addr = omap44xx_gpio2_addrs,
f776471f
BC		 1824 .user = OCP_USER_MPU | OCP_USER_SDMA,
1825};
1826
3b54baad
BC		 1827/* gpio2 slave ports */
1828static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1829 &omap44xx_l4_per__gpio2,
f776471f
BC		 1830};
1831
3b54baad 1832static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1833 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1834};
1835
1836static struct omap_hwmod omap44xx_gpio2_hwmod = {
1837 .name = "gpio2",
1838 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1839 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1840 .mpu_irqs = omap44xx_gpio2_irqs,
3b54baad 1841 .main_clk = "gpio2_ick",
f776471f
BC		 1842 .prcm = {
1843 .omap4 = {
3b54baad 1844 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1845 },
1846 },
3b54baad
BC		 1847 .opt_clks = gpio2_opt_clks,
1848 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1849 .dev_attr = &gpio_dev_attr,
1850 .slaves = omap44xx_gpio2_slaves,
1851 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1852 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1853};
1854
3b54baad
BC		 1855/* gpio3 */
1856static struct omap_hwmod omap44xx_gpio3_hwmod;
1857static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1858 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
212738a4 1859 { .irq = -1 }
f776471f
BC		 1860};
1861
3b54baad 1862static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1863 {
3b54baad
BC		 1864 .pa_start = 0x48057000,
1865 .pa_end = 0x480571ff,
f776471f
BC		 1866 .flags = ADDR_TYPE_RT
1867 },
78183f3f 1868 { }
f776471f
BC		 1869};
1870
3b54baad
BC		 1871/* l4_per -> gpio3 */
1872static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1873 .master = &omap44xx_l4_per_hwmod,
3b54baad 1874 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1875 .clk = "l4_div_ck",
3b54baad 1876 .addr = omap44xx_gpio3_addrs,
f776471f
BC		 1877 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878};
1879
3b54baad
BC		 1880/* gpio3 slave ports */
1881static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1882 &omap44xx_l4_per__gpio3,
f776471f
BC		 1883};
1884
3b54baad 1885static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1886 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1887};
1888
1889static struct omap_hwmod omap44xx_gpio3_hwmod = {
1890 .name = "gpio3",
1891 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1892 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1893 .mpu_irqs = omap44xx_gpio3_irqs,
3b54baad 1894 .main_clk = "gpio3_ick",
f776471f
BC		 1895 .prcm = {
1896 .omap4 = {
3b54baad 1897 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1898 },
1899 },
3b54baad
BC		 1900 .opt_clks = gpio3_opt_clks,
1901 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1902 .dev_attr = &gpio_dev_attr,
1903 .slaves = omap44xx_gpio3_slaves,
1904 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1905 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1906};
1907
3b54baad
BC		 1908/* gpio4 */
1909static struct omap_hwmod omap44xx_gpio4_hwmod;
1910static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1911 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
212738a4 1912 { .irq = -1 }
f776471f
BC		 1913};
1914
3b54baad 1915static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1916 {
3b54baad
BC		 1917 .pa_start = 0x48059000,
1918 .pa_end = 0x480591ff,
f776471f
BC		 1919 .flags = ADDR_TYPE_RT
1920 },
78183f3f 1921 { }
f776471f
BC		 1922};
1923
3b54baad
BC		 1924/* l4_per -> gpio4 */
1925static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1926 .master = &omap44xx_l4_per_hwmod,
3b54baad 1927 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1928 .clk = "l4_div_ck",
3b54baad 1929 .addr = omap44xx_gpio4_addrs,
f776471f
BC		 1930 .user = OCP_USER_MPU | OCP_USER_SDMA,
1931};
1932
3b54baad
BC		 1933/* gpio4 slave ports */
1934static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1935 &omap44xx_l4_per__gpio4,
f776471f
BC		 1936};
1937
3b54baad 1938static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1939 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1940};
1941
1942static struct omap_hwmod omap44xx_gpio4_hwmod = {
1943 .name = "gpio4",
1944 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1946 .mpu_irqs = omap44xx_gpio4_irqs,
3b54baad 1947 .main_clk = "gpio4_ick",
f776471f
BC		 1948 .prcm = {
1949 .omap4 = {
3b54baad 1950 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1951 },
1952 },
3b54baad
BC		 1953 .opt_clks = gpio4_opt_clks,
1954 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1955 .dev_attr = &gpio_dev_attr,
1956 .slaves = omap44xx_gpio4_slaves,
1957 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1958 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1959};
1960
3b54baad
BC		 1961/* gpio5 */
1962static struct omap_hwmod omap44xx_gpio5_hwmod;
1963static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1964 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
212738a4 1965 { .irq = -1 }
55d2cb08
BC		 1966};
1967
3b54baad
BC		 1968static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1969 {
1970 .pa_start = 0x4805b000,
1971 .pa_end = 0x4805b1ff,
1972 .flags = ADDR_TYPE_RT
1973 },
78183f3f 1974 { }
55d2cb08
BC		 1975};
1976
3b54baad
BC		 1977/* l4_per -> gpio5 */
1978static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1979 .master = &omap44xx_l4_per_hwmod,
1980 .slave = &omap44xx_gpio5_hwmod,
b399bca8 1981 .clk = "l4_div_ck",
3b54baad 1982 .addr = omap44xx_gpio5_addrs,
3b54baad 1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 1984};
1985
3b54baad
BC		 1986/* gpio5 slave ports */
1987static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1988 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1989};
1990
3b54baad 1991static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1992 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1993};
1994
3b54baad
BC		 1995static struct omap_hwmod omap44xx_gpio5_hwmod = {
1996 .name = "gpio5",
1997 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1998 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1999 .mpu_irqs = omap44xx_gpio5_irqs,
3b54baad 2000 .main_clk = "gpio5_ick",
55d2cb08
BC		 2001 .prcm = {
2002 .omap4 = {
3b54baad 2003 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 2004 },
2005 },
3b54baad
BC		 2006 .opt_clks = gpio5_opt_clks,
2007 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2008 .dev_attr = &gpio_dev_attr,
2009 .slaves = omap44xx_gpio5_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 2011 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2012};
2013
3b54baad
BC		 2014/* gpio6 */
2015static struct omap_hwmod omap44xx_gpio6_hwmod;
2016static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2017 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
212738a4 2018 { .irq = -1 }
92b18d1c
BC		 2019};
2020
3b54baad 2021static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 2022 {
3b54baad
BC		 2023 .pa_start = 0x4805d000,
2024 .pa_end = 0x4805d1ff,
92b18d1c
BC		 2025 .flags = ADDR_TYPE_RT
2026 },
78183f3f 2027 { }
92b18d1c
BC		 2028};
2029
3b54baad
BC		 2030/* l4_per -> gpio6 */
2031static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2032 .master = &omap44xx_l4_per_hwmod,
2033 .slave = &omap44xx_gpio6_hwmod,
b399bca8 2034 .clk = "l4_div_ck",
3b54baad 2035 .addr = omap44xx_gpio6_addrs,
3b54baad 2036 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 2037};
2038
3b54baad
BC		 2039/* gpio6 slave ports */
2040static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2041 &omap44xx_l4_per__gpio6,
db12ba53
BC		 2042};
2043
3b54baad 2044static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 2045 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 2046};
2047
3b54baad
BC		 2048static struct omap_hwmod omap44xx_gpio6_hwmod = {
2049 .name = "gpio6",
2050 .class = &omap44xx_gpio_hwmod_class,
b399bca8 2051 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2052 .mpu_irqs = omap44xx_gpio6_irqs,
3b54baad
BC		 2053 .main_clk = "gpio6_ick",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2057 },
db12ba53 2058 },
3b54baad
BC		 2059 .opt_clks = gpio6_opt_clks,
2060 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2061 .dev_attr = &gpio_dev_attr,
2062 .slaves = omap44xx_gpio6_slaves,
2063 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2064 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 2065};
2066
407a6888
BC		 2067/*
2068 * 'hsi' class
2069 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2070 * serial if)
2071 */
2072
2073static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2074 .rev_offs = 0x0000,
2075 .sysc_offs = 0x0010,
2076 .syss_offs = 0x0014,
2077 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2078 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2079 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2080 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2081 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2082 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2083 .sysc_fields = &omap_hwmod_sysc_type1,
2084};
2085
2086static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2087 .name = "hsi",
2088 .sysc = &omap44xx_hsi_sysc,
2089};
2090
2091/* hsi */
2092static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2093 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2094 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2095 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
212738a4 2096 { .irq = -1 }
407a6888
BC		 2097};
2098
2099/* hsi master ports */
2100static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2101 &omap44xx_hsi__l3_main_2,
2102};
2103
2104static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2105 {
2106 .pa_start = 0x4a058000,
2107 .pa_end = 0x4a05bfff,
2108 .flags = ADDR_TYPE_RT
2109 },
78183f3f 2110 { }
407a6888
BC		 2111};
2112
2113/* l4_cfg -> hsi */
2114static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2115 .master = &omap44xx_l4_cfg_hwmod,
2116 .slave = &omap44xx_hsi_hwmod,
2117 .clk = "l4_div_ck",
2118 .addr = omap44xx_hsi_addrs,
407a6888
BC		 2119 .user = OCP_USER_MPU | OCP_USER_SDMA,
2120};
2121
2122/* hsi slave ports */
2123static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2124 &omap44xx_l4_cfg__hsi,
2125};
2126
2127static struct omap_hwmod omap44xx_hsi_hwmod = {
2128 .name = "hsi",
2129 .class = &omap44xx_hsi_hwmod_class,
2130 .mpu_irqs = omap44xx_hsi_irqs,
407a6888 2131 .main_clk = "hsi_fck",
00fe610b 2132 .prcm = {
407a6888
BC		 2133 .omap4 = {
2134 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2135 },
2136 },
2137 .slaves = omap44xx_hsi_slaves,
2138 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2139 .masters = omap44xx_hsi_masters,
2140 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2141 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2142};
2143
3b54baad
BC		 2144/*
2145 * 'i2c' class
2146 * multimaster high-speed i2c controller
2147 */
db12ba53 2148
3b54baad
BC		 2149static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2150 .sysc_offs = 0x0010,
2151 .syss_offs = 0x0090,
2152 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2154 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2156 SIDLE_SMART_WKUP),
3b54baad 2157 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2158};
2159
3b54baad 2160static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2161 .name = "i2c",
2162 .sysc = &omap44xx_i2c_sysc,
db791a75 2163 .rev = OMAP_I2C_IP_VERSION_2,
db12ba53
BC		 2164};
2165
3b54baad
BC		 2166/* i2c1 */
2167static struct omap_hwmod omap44xx_i2c1_hwmod;
2168static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2169 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
212738a4 2170 { .irq = -1 }
db12ba53
BC		 2171};
2172
3b54baad
BC		 2173static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2174 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2175 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
bc614958 2176 { .dma_req = -1 }
db12ba53
BC		 2177};
2178
3b54baad 2179static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2180 {
3b54baad
BC		 2181 .pa_start = 0x48070000,
2182 .pa_end = 0x480700ff,
db12ba53
BC		 2183 .flags = ADDR_TYPE_RT
2184 },
78183f3f 2185 { }
db12ba53
BC		 2186};
2187
3b54baad
BC		 2188/* l4_per -> i2c1 */
2189static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2190 .master = &omap44xx_l4_per_hwmod,
2191 .slave = &omap44xx_i2c1_hwmod,
2192 .clk = "l4_div_ck",
2193 .addr = omap44xx_i2c1_addrs,
92b18d1c
BC		 2194 .user = OCP_USER_MPU | OCP_USER_SDMA,
2195};
2196
3b54baad
BC		 2197/* i2c1 slave ports */
2198static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2199 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2200};
2201
3b54baad
BC		 2202static struct omap_hwmod omap44xx_i2c1_hwmod = {
2203 .name = "i2c1",
2204 .class = &omap44xx_i2c_hwmod_class,
3e600522 2205 .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
3b54baad 2206 .mpu_irqs = omap44xx_i2c1_irqs,
3b54baad 2207 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
3b54baad 2208 .main_clk = "i2c1_fck",
92b18d1c
BC		 2209 .prcm = {
2210 .omap4 = {
3b54baad 2211 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 2212 },
2213 },
3b54baad
BC		 2214 .slaves = omap44xx_i2c1_slaves,
2215 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 2216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2217};
2218
3b54baad
BC		 2219/* i2c2 */
2220static struct omap_hwmod omap44xx_i2c2_hwmod;
2221static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2222 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
212738a4 2223 { .irq = -1 }
92b18d1c
BC		 2224};
2225
3b54baad
BC		 2226static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2227 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2228 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
bc614958 2229 { .dma_req = -1 }
3b54baad
BC		 2230};
2231
2232static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2233 {
3b54baad
BC		 2234 .pa_start = 0x48072000,
2235 .pa_end = 0x480720ff,
92b18d1c
BC		 2236 .flags = ADDR_TYPE_RT
2237 },
78183f3f 2238 { }
92b18d1c
BC		 2239};
2240
3b54baad
BC		 2241/* l4_per -> i2c2 */
2242static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2243 .master = &omap44xx_l4_per_hwmod,
3b54baad 2244 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2245 .clk = "l4_div_ck",
3b54baad 2246 .addr = omap44xx_i2c2_addrs,
db12ba53
BC		 2247 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248};
2249
3b54baad
BC		 2250/* i2c2 slave ports */
2251static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2252 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2253};
2254
3b54baad
BC		 2255static struct omap_hwmod omap44xx_i2c2_hwmod = {
2256 .name = "i2c2",
2257 .class = &omap44xx_i2c_hwmod_class,
3e600522 2258 .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
3b54baad 2259 .mpu_irqs = omap44xx_i2c2_irqs,
3b54baad 2260 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
3b54baad 2261 .main_clk = "i2c2_fck",
db12ba53
BC		 2262 .prcm = {
2263 .omap4 = {
3b54baad 2264 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 2265 },
2266 },
3b54baad
BC		 2267 .slaves = omap44xx_i2c2_slaves,
2268 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 2269 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2270};
2271
3b54baad
BC		 2272/* i2c3 */
2273static struct omap_hwmod omap44xx_i2c3_hwmod;
2274static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2275 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
212738a4 2276 { .irq = -1 }
db12ba53
BC		 2277};
2278
3b54baad
BC		 2279static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2280 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2281 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
bc614958 2282 { .dma_req = -1 }
92b18d1c
BC		 2283};
2284
3b54baad 2285static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2286 {
3b54baad
BC		 2287 .pa_start = 0x48060000,
2288 .pa_end = 0x480600ff,
92b18d1c
BC		 2289 .flags = ADDR_TYPE_RT
2290 },
78183f3f 2291 { }
92b18d1c
BC		 2292};
2293
3b54baad
BC		 2294/* l4_per -> i2c3 */
2295static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2296 .master = &omap44xx_l4_per_hwmod,
3b54baad 2297 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2298 .clk = "l4_div_ck",
3b54baad 2299 .addr = omap44xx_i2c3_addrs,
db12ba53
BC		 2300 .user = OCP_USER_MPU | OCP_USER_SDMA,
2301};
2302
3b54baad
BC		 2303/* i2c3 slave ports */
2304static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2305 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2306};
2307
3b54baad
BC		 2308static struct omap_hwmod omap44xx_i2c3_hwmod = {
2309 .name = "i2c3",
2310 .class = &omap44xx_i2c_hwmod_class,
3e600522 2311 .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
3b54baad 2312 .mpu_irqs = omap44xx_i2c3_irqs,
3b54baad 2313 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
3b54baad 2314 .main_clk = "i2c3_fck",
db12ba53
BC		 2315 .prcm = {
2316 .omap4 = {
3b54baad 2317 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 2318 },
2319 },
3b54baad
BC		 2320 .slaves = omap44xx_i2c3_slaves,
2321 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 2322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2323};
2324
3b54baad
BC		 2325/* i2c4 */
2326static struct omap_hwmod omap44xx_i2c4_hwmod;
2327static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2328 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
212738a4 2329 { .irq = -1 }
db12ba53
BC		 2330};
2331
3b54baad
BC		 2332static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2333 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2334 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
bc614958 2335 { .dma_req = -1 }
db12ba53
BC		 2336};
2337
3b54baad 2338static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2339 {
3b54baad
BC		 2340 .pa_start = 0x48350000,
2341 .pa_end = 0x483500ff,
db12ba53
BC		 2342 .flags = ADDR_TYPE_RT
2343 },
78183f3f 2344 { }
db12ba53
BC		 2345};
2346
3b54baad
BC		 2347/* l4_per -> i2c4 */
2348static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2349 .master = &omap44xx_l4_per_hwmod,
2350 .slave = &omap44xx_i2c4_hwmod,
2351 .clk = "l4_div_ck",
2352 .addr = omap44xx_i2c4_addrs,
3b54baad 2353 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2354};
2355
3b54baad
BC		 2356/* i2c4 slave ports */
2357static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2358 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2359};
2360
3b54baad
BC		 2361static struct omap_hwmod omap44xx_i2c4_hwmod = {
2362 .name = "i2c4",
2363 .class = &omap44xx_i2c_hwmod_class,
3e600522 2364 .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
3b54baad 2365 .mpu_irqs = omap44xx_i2c4_irqs,
3b54baad 2366 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
3b54baad 2367 .main_clk = "i2c4_fck",
92b18d1c
BC		 2368 .prcm = {
2369 .omap4 = {
3b54baad 2370 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 2371 },
2372 },
3b54baad
BC		 2373 .slaves = omap44xx_i2c4_slaves,
2374 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 2375 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2376};
2377
407a6888
BC		 2378/*
2379 * 'ipu' class
2380 * imaging processor unit
2381 */
2382
2383static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2384 .name = "ipu",
2385};
2386
2387/* ipu */
2388static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2389 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
212738a4 2390 { .irq = -1 }
407a6888
BC		 2391};
2392
2393static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2394 { .name = "cpu0", .rst_shift = 0 },
2395};
2396
2397static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2398 { .name = "cpu1", .rst_shift = 1 },
2399};
2400
2401static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2402 { .name = "mmu_cache", .rst_shift = 2 },
2403};
2404
2405/* ipu master ports */
2406static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2407 &omap44xx_ipu__l3_main_2,
2408};
2409
2410/* l3_main_2 -> ipu */
2411static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2412 .master = &omap44xx_l3_main_2_hwmod,
2413 .slave = &omap44xx_ipu_hwmod,
2414 .clk = "l3_div_ck",
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416};
2417
2418/* ipu slave ports */
2419static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2420 &omap44xx_l3_main_2__ipu,
2421};
2422
2423/* Pseudo hwmod for reset control purpose only */
2424static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2425 .name = "ipu_c0",
2426 .class = &omap44xx_ipu_hwmod_class,
2427 .flags = HWMOD_INIT_NO_RESET,
2428 .rst_lines = omap44xx_ipu_c0_resets,
2429 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
00fe610b 2430 .prcm = {
407a6888
BC		 2431 .omap4 = {
2432 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2433 },
2434 },
2435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2436};
2437
2438/* Pseudo hwmod for reset control purpose only */
2439static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2440 .name = "ipu_c1",
2441 .class = &omap44xx_ipu_hwmod_class,
2442 .flags = HWMOD_INIT_NO_RESET,
2443 .rst_lines = omap44xx_ipu_c1_resets,
2444 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
00fe610b 2445 .prcm = {
407a6888
BC		 2446 .omap4 = {
2447 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2448 },
2449 },
2450 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2451};
2452
2453static struct omap_hwmod omap44xx_ipu_hwmod = {
2454 .name = "ipu",
2455 .class = &omap44xx_ipu_hwmod_class,
2456 .mpu_irqs = omap44xx_ipu_irqs,
407a6888
BC		 2457 .rst_lines = omap44xx_ipu_resets,
2458 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2459 .main_clk = "ipu_fck",
00fe610b 2460 .prcm = {
407a6888
BC		 2461 .omap4 = {
2462 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2463 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2464 },
2465 },
2466 .slaves = omap44xx_ipu_slaves,
2467 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2468 .masters = omap44xx_ipu_masters,
2469 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2470 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2471};
2472
2473/*
2474 * 'iss' class
2475 * external images sensor pixel data processor
2476 */
2477
2478static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2479 .rev_offs = 0x0000,
2480 .sysc_offs = 0x0010,
2481 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2482 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2483 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2484 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2485 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2486 .sysc_fields = &omap_hwmod_sysc_type2,
2487};
2488
2489static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2490 .name = "iss",
2491 .sysc = &omap44xx_iss_sysc,
2492};
2493
2494/* iss */
2495static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2496 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
212738a4 2497 { .irq = -1 }
407a6888
BC		 2498};
2499
2500static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2501 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2502 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2503 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2504 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
bc614958 2505 { .dma_req = -1 }
407a6888
BC		 2506};
2507
2508/* iss master ports */
2509static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2510 &omap44xx_iss__l3_main_2,
2511};
2512
2513static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2514 {
2515 .pa_start = 0x52000000,
2516 .pa_end = 0x520000ff,
2517 .flags = ADDR_TYPE_RT
2518 },
78183f3f 2519 { }
407a6888
BC		 2520};
2521
2522/* l3_main_2 -> iss */
2523static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2524 .master = &omap44xx_l3_main_2_hwmod,
2525 .slave = &omap44xx_iss_hwmod,
2526 .clk = "l3_div_ck",
2527 .addr = omap44xx_iss_addrs,
407a6888
BC		 2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529};
2530
2531/* iss slave ports */
2532static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2533 &omap44xx_l3_main_2__iss,
2534};
2535
2536static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2537 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2538};
2539
2540static struct omap_hwmod omap44xx_iss_hwmod = {
2541 .name = "iss",
2542 .class = &omap44xx_iss_hwmod_class,
2543 .mpu_irqs = omap44xx_iss_irqs,
407a6888 2544 .sdma_reqs = omap44xx_iss_sdma_reqs,
407a6888 2545 .main_clk = "iss_fck",
00fe610b 2546 .prcm = {
407a6888
BC		 2547 .omap4 = {
2548 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2549 },
2550 },
2551 .opt_clks = iss_opt_clks,
2552 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2553 .slaves = omap44xx_iss_slaves,
2554 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2555 .masters = omap44xx_iss_masters,
2556 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2557 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2558};
2559
8f25bdc5
BC		 2560/*
2561 * 'iva' class
2562 * multi-standard video encoder/decoder hardware accelerator
2563 */
2564
2565static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2566 .name = "iva",
8f25bdc5
BC		 2567};
2568
2569/* iva */
2570static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2571 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2572 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2573 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
212738a4 2574 { .irq = -1 }
8f25bdc5
BC		 2575};
2576
2577static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2578 { .name = "logic", .rst_shift = 2 },
2579};
2580
2581static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2582 { .name = "seq0", .rst_shift = 0 },
2583};
2584
2585static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2586 { .name = "seq1", .rst_shift = 1 },
2587};
2588
2589/* iva master ports */
2590static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2591 &omap44xx_iva__l3_main_2,
2592 &omap44xx_iva__l3_instr,
2593};
2594
2595static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2596 {
2597 .pa_start = 0x5a000000,
2598 .pa_end = 0x5a07ffff,
2599 .flags = ADDR_TYPE_RT
2600 },
78183f3f 2601 { }
8f25bdc5
BC		 2602};
2603
2604/* l3_main_2 -> iva */
2605static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2606 .master = &omap44xx_l3_main_2_hwmod,
2607 .slave = &omap44xx_iva_hwmod,
2608 .clk = "l3_div_ck",
2609 .addr = omap44xx_iva_addrs,
8f25bdc5
BC		 2610 .user = OCP_USER_MPU,
2611};
2612
2613/* iva slave ports */
2614static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2615 &omap44xx_dsp__iva,
2616 &omap44xx_l3_main_2__iva,
2617};
2618
2619/* Pseudo hwmod for reset control purpose only */
2620static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2621 .name = "iva_seq0",
2622 .class = &omap44xx_iva_hwmod_class,
2623 .flags = HWMOD_INIT_NO_RESET,
2624 .rst_lines = omap44xx_iva_seq0_resets,
2625 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2626 .prcm = {
2627 .omap4 = {
2628 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2629 },
2630 },
2631 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2632};
2633
2634/* Pseudo hwmod for reset control purpose only */
2635static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2636 .name = "iva_seq1",
2637 .class = &omap44xx_iva_hwmod_class,
2638 .flags = HWMOD_INIT_NO_RESET,
2639 .rst_lines = omap44xx_iva_seq1_resets,
2640 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2641 .prcm = {
2642 .omap4 = {
2643 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2644 },
2645 },
2646 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2647};
2648
2649static struct omap_hwmod omap44xx_iva_hwmod = {
2650 .name = "iva",
2651 .class = &omap44xx_iva_hwmod_class,
2652 .mpu_irqs = omap44xx_iva_irqs,
8f25bdc5
BC		 2653 .rst_lines = omap44xx_iva_resets,
2654 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2655 .main_clk = "iva_fck",
2656 .prcm = {
2657 .omap4 = {
2658 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2659 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2660 },
2661 },
2662 .slaves = omap44xx_iva_slaves,
2663 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2664 .masters = omap44xx_iva_masters,
2665 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2666 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2667};
2668
407a6888
BC		 2669/*
2670 * 'kbd' class
2671 * keyboard controller
2672 */
2673
2674static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2675 .rev_offs = 0x0000,
2676 .sysc_offs = 0x0010,
2677 .syss_offs = 0x0014,
2678 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2679 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2680 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2681 SYSS_HAS_RESET_STATUS),
2682 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2683 .sysc_fields = &omap_hwmod_sysc_type1,
2684};
2685
2686static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2687 .name = "kbd",
2688 .sysc = &omap44xx_kbd_sysc,
2689};
2690
2691/* kbd */
2692static struct omap_hwmod omap44xx_kbd_hwmod;
2693static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2694 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
212738a4 2695 { .irq = -1 }
407a6888
BC		 2696};
2697
2698static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2699 {
2700 .pa_start = 0x4a31c000,
2701 .pa_end = 0x4a31c07f,
2702 .flags = ADDR_TYPE_RT
2703 },
78183f3f 2704 { }
407a6888
BC		 2705};
2706
2707/* l4_wkup -> kbd */
2708static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2709 .master = &omap44xx_l4_wkup_hwmod,
2710 .slave = &omap44xx_kbd_hwmod,
2711 .clk = "l4_wkup_clk_mux_ck",
2712 .addr = omap44xx_kbd_addrs,
407a6888
BC		 2713 .user = OCP_USER_MPU | OCP_USER_SDMA,
2714};
2715
2716/* kbd slave ports */
2717static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2718 &omap44xx_l4_wkup__kbd,
2719};
2720
2721static struct omap_hwmod omap44xx_kbd_hwmod = {
2722 .name = "kbd",
2723 .class = &omap44xx_kbd_hwmod_class,
2724 .mpu_irqs = omap44xx_kbd_irqs,
407a6888 2725 .main_clk = "kbd_fck",
00fe610b 2726 .prcm = {
407a6888
BC		 2727 .omap4 = {
2728 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2729 },
2730 },
2731 .slaves = omap44xx_kbd_slaves,
2732 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2733 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2734};
2735
ec5df927
BC		 2736/*
2737 * 'mailbox' class
2738 * mailbox module allowing communication between the on-chip processors using a
2739 * queued mailbox-interrupt mechanism.
2740 */
2741
2742static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2743 .rev_offs = 0x0000,
2744 .sysc_offs = 0x0010,
2745 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2746 SYSC_HAS_SOFTRESET),
2747 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2748 .sysc_fields = &omap_hwmod_sysc_type2,
2749};
2750
2751static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2752 .name = "mailbox",
2753 .sysc = &omap44xx_mailbox_sysc,
2754};
2755
2756/* mailbox */
2757static struct omap_hwmod omap44xx_mailbox_hwmod;
2758static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2759 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
212738a4 2760 { .irq = -1 }
ec5df927
BC		 2761};
2762
2763static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2764 {
2765 .pa_start = 0x4a0f4000,
2766 .pa_end = 0x4a0f41ff,
2767 .flags = ADDR_TYPE_RT
2768 },
78183f3f 2769 { }
ec5df927
BC		 2770};
2771
2772/* l4_cfg -> mailbox */
2773static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2774 .master = &omap44xx_l4_cfg_hwmod,
2775 .slave = &omap44xx_mailbox_hwmod,
2776 .clk = "l4_div_ck",
2777 .addr = omap44xx_mailbox_addrs,
ec5df927
BC		 2778 .user = OCP_USER_MPU | OCP_USER_SDMA,
2779};
2780
2781/* mailbox slave ports */
2782static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2783 &omap44xx_l4_cfg__mailbox,
2784};
2785
2786static struct omap_hwmod omap44xx_mailbox_hwmod = {
2787 .name = "mailbox",
2788 .class = &omap44xx_mailbox_hwmod_class,
2789 .mpu_irqs = omap44xx_mailbox_irqs,
00fe610b 2790 .prcm = {
ec5df927
BC		 2791 .omap4 = {
2792 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2793 },
2794 },
2795 .slaves = omap44xx_mailbox_slaves,
2796 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2797 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2798};
2799
4ddff493
BC		 2800/*
2801 * 'mcbsp' class
2802 * multi channel buffered serial port controller
2803 */
2804
2805static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2806 .sysc_offs = 0x008c,
2807 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2808 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2809 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2810 .sysc_fields = &omap_hwmod_sysc_type1,
2811};
2812
2813static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2814 .name = "mcbsp",
2815 .sysc = &omap44xx_mcbsp_sysc,
cb7e9ded 2816 .rev = MCBSP_CONFIG_TYPE4,
4ddff493
BC		 2817};
2818
2819/* mcbsp1 */
2820static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2821static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2822 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
212738a4 2823 { .irq = -1 }
4ddff493
BC		 2824};
2825
2826static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2827 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2828 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
bc614958 2829 { .dma_req = -1 }
4ddff493
BC		 2830};
2831
2832static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2833 {
cb7e9ded 2834 .name = "mpu",
4ddff493
BC		 2835 .pa_start = 0x40122000,
2836 .pa_end = 0x401220ff,
2837 .flags = ADDR_TYPE_RT
2838 },
78183f3f 2839 { }
4ddff493
BC		 2840};
2841
2842/* l4_abe -> mcbsp1 */
2843static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2844 .master = &omap44xx_l4_abe_hwmod,
2845 .slave = &omap44xx_mcbsp1_hwmod,
2846 .clk = "ocp_abe_iclk",
2847 .addr = omap44xx_mcbsp1_addrs,
4ddff493
BC		 2848 .user = OCP_USER_MPU,
2849};
2850
2851static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2852 {
cb7e9ded 2853 .name = "dma",
4ddff493
BC		 2854 .pa_start = 0x49022000,
2855 .pa_end = 0x490220ff,
2856 .flags = ADDR_TYPE_RT
2857 },
78183f3f 2858 { }
4ddff493
BC		 2859};
2860
2861/* l4_abe -> mcbsp1 (dma) */
2862static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2863 .master = &omap44xx_l4_abe_hwmod,
2864 .slave = &omap44xx_mcbsp1_hwmod,
2865 .clk = "ocp_abe_iclk",
2866 .addr = omap44xx_mcbsp1_dma_addrs,
4ddff493
BC		 2867 .user = OCP_USER_SDMA,
2868};
2869
2870/* mcbsp1 slave ports */
2871static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2872 &omap44xx_l4_abe__mcbsp1,
2873 &omap44xx_l4_abe__mcbsp1_dma,
2874};
2875
2876static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2877 .name = "mcbsp1",
2878 .class = &omap44xx_mcbsp_hwmod_class,
2879 .mpu_irqs = omap44xx_mcbsp1_irqs,
4ddff493 2880 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
4ddff493
BC		 2881 .main_clk = "mcbsp1_fck",
2882 .prcm = {
2883 .omap4 = {
2884 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2885 },
2886 },
2887 .slaves = omap44xx_mcbsp1_slaves,
2888 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2889 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2890};
2891
2892/* mcbsp2 */
2893static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2894static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2895 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
212738a4 2896 { .irq = -1 }
4ddff493
BC		 2897};
2898
2899static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2900 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2901 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
bc614958 2902 { .dma_req = -1 }
4ddff493
BC		 2903};
2904
2905static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2906 {
cb7e9ded 2907 .name = "mpu",
4ddff493
BC		 2908 .pa_start = 0x40124000,
2909 .pa_end = 0x401240ff,
2910 .flags = ADDR_TYPE_RT
2911 },
78183f3f 2912 { }
4ddff493
BC		 2913};
2914
2915/* l4_abe -> mcbsp2 */
2916static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2917 .master = &omap44xx_l4_abe_hwmod,
2918 .slave = &omap44xx_mcbsp2_hwmod,
2919 .clk = "ocp_abe_iclk",
2920 .addr = omap44xx_mcbsp2_addrs,
4ddff493
BC		 2921 .user = OCP_USER_MPU,
2922};
2923
2924static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2925 {
cb7e9ded 2926 .name = "dma",
4ddff493
BC		 2927 .pa_start = 0x49024000,
2928 .pa_end = 0x490240ff,
2929 .flags = ADDR_TYPE_RT
2930 },
78183f3f 2931 { }
4ddff493
BC		 2932};
2933
2934/* l4_abe -> mcbsp2 (dma) */
2935static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2936 .master = &omap44xx_l4_abe_hwmod,
2937 .slave = &omap44xx_mcbsp2_hwmod,
2938 .clk = "ocp_abe_iclk",
2939 .addr = omap44xx_mcbsp2_dma_addrs,
4ddff493
BC		 2940 .user = OCP_USER_SDMA,
2941};
2942
2943/* mcbsp2 slave ports */
2944static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2945 &omap44xx_l4_abe__mcbsp2,
2946 &omap44xx_l4_abe__mcbsp2_dma,
2947};
2948
2949static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2950 .name = "mcbsp2",
2951 .class = &omap44xx_mcbsp_hwmod_class,
2952 .mpu_irqs = omap44xx_mcbsp2_irqs,
4ddff493 2953 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
4ddff493
BC		 2954 .main_clk = "mcbsp2_fck",
2955 .prcm = {
2956 .omap4 = {
2957 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2958 },
2959 },
2960 .slaves = omap44xx_mcbsp2_slaves,
2961 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2962 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2963};
2964
2965/* mcbsp3 */
2966static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2967static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2968 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
212738a4 2969 { .irq = -1 }
4ddff493
BC		 2970};
2971
2972static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2973 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2974 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
bc614958 2975 { .dma_req = -1 }
4ddff493
BC		 2976};
2977
2978static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2979 {
cb7e9ded 2980 .name = "mpu",
4ddff493
BC		 2981 .pa_start = 0x40126000,
2982 .pa_end = 0x401260ff,
2983 .flags = ADDR_TYPE_RT
2984 },
78183f3f 2985 { }
4ddff493
BC		 2986};
2987
2988/* l4_abe -> mcbsp3 */
2989static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2990 .master = &omap44xx_l4_abe_hwmod,
2991 .slave = &omap44xx_mcbsp3_hwmod,
2992 .clk = "ocp_abe_iclk",
2993 .addr = omap44xx_mcbsp3_addrs,
4ddff493
BC		 2994 .user = OCP_USER_MPU,
2995};
2996
2997static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2998 {
cb7e9ded 2999 .name = "dma",
4ddff493
BC		 3000 .pa_start = 0x49026000,
3001 .pa_end = 0x490260ff,
3002 .flags = ADDR_TYPE_RT
3003 },
78183f3f 3004 { }
4ddff493
BC		 3005};
3006
3007/* l4_abe -> mcbsp3 (dma) */
3008static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3009 .master = &omap44xx_l4_abe_hwmod,
3010 .slave = &omap44xx_mcbsp3_hwmod,
3011 .clk = "ocp_abe_iclk",
3012 .addr = omap44xx_mcbsp3_dma_addrs,
4ddff493
BC		 3013 .user = OCP_USER_SDMA,
3014};
3015
3016/* mcbsp3 slave ports */
3017static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3018 &omap44xx_l4_abe__mcbsp3,
3019 &omap44xx_l4_abe__mcbsp3_dma,
3020};
3021
3022static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3023 .name = "mcbsp3",
3024 .class = &omap44xx_mcbsp_hwmod_class,
3025 .mpu_irqs = omap44xx_mcbsp3_irqs,
4ddff493 3026 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
4ddff493
BC		 3027 .main_clk = "mcbsp3_fck",
3028 .prcm = {
3029 .omap4 = {
3030 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3031 },
3032 },
3033 .slaves = omap44xx_mcbsp3_slaves,
3034 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3035 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3036};
3037
3038/* mcbsp4 */
3039static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3040static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3041 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
212738a4 3042 { .irq = -1 }
4ddff493
BC		 3043};
3044
3045static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3046 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3047 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
bc614958 3048 { .dma_req = -1 }
4ddff493
BC		 3049};
3050
3051static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3052 {
3053 .pa_start = 0x48096000,
3054 .pa_end = 0x480960ff,
3055 .flags = ADDR_TYPE_RT
3056 },
78183f3f 3057 { }
4ddff493
BC		 3058};
3059
3060/* l4_per -> mcbsp4 */
3061static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3062 .master = &omap44xx_l4_per_hwmod,
3063 .slave = &omap44xx_mcbsp4_hwmod,
3064 .clk = "l4_div_ck",
3065 .addr = omap44xx_mcbsp4_addrs,
4ddff493
BC		 3066 .user = OCP_USER_MPU | OCP_USER_SDMA,
3067};
3068
3069/* mcbsp4 slave ports */
3070static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3071 &omap44xx_l4_per__mcbsp4,
3072};
3073
3074static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3075 .name = "mcbsp4",
3076 .class = &omap44xx_mcbsp_hwmod_class,
3077 .mpu_irqs = omap44xx_mcbsp4_irqs,
4ddff493 3078 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
4ddff493
BC		 3079 .main_clk = "mcbsp4_fck",
3080 .prcm = {
3081 .omap4 = {
3082 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3083 },
3084 },
3085 .slaves = omap44xx_mcbsp4_slaves,
3086 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3087 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3088};
3089
407a6888
BC		 3090/*
3091 * 'mcpdm' class
3092 * multi channel pdm controller (proprietary interface with phoenix power
3093 * ic)
3094 */
3095
3096static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3097 .rev_offs = 0x0000,
3098 .sysc_offs = 0x0010,
3099 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3100 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3101 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3102 SIDLE_SMART_WKUP),
3103 .sysc_fields = &omap_hwmod_sysc_type2,
3104};
3105
3106static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3107 .name = "mcpdm",
3108 .sysc = &omap44xx_mcpdm_sysc,
3109};
3110
3111/* mcpdm */
3112static struct omap_hwmod omap44xx_mcpdm_hwmod;
3113static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3114 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
212738a4 3115 { .irq = -1 }
407a6888
BC		 3116};
3117
3118static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3119 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3120 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
bc614958 3121 { .dma_req = -1 }
407a6888
BC		 3122};
3123
3124static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3125 {
3126 .pa_start = 0x40132000,
3127 .pa_end = 0x4013207f,
3128 .flags = ADDR_TYPE_RT
3129 },
78183f3f 3130 { }
407a6888
BC		 3131};
3132
3133/* l4_abe -> mcpdm */
3134static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3135 .master = &omap44xx_l4_abe_hwmod,
3136 .slave = &omap44xx_mcpdm_hwmod,
3137 .clk = "ocp_abe_iclk",
3138 .addr = omap44xx_mcpdm_addrs,
407a6888
BC		 3139 .user = OCP_USER_MPU,
3140};
3141
3142static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3143 {
3144 .pa_start = 0x49032000,
3145 .pa_end = 0x4903207f,
3146 .flags = ADDR_TYPE_RT
3147 },
78183f3f 3148 { }
407a6888
BC		 3149};
3150
3151/* l4_abe -> mcpdm (dma) */
3152static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3153 .master = &omap44xx_l4_abe_hwmod,
3154 .slave = &omap44xx_mcpdm_hwmod,
3155 .clk = "ocp_abe_iclk",
3156 .addr = omap44xx_mcpdm_dma_addrs,
407a6888
BC		 3157 .user = OCP_USER_SDMA,
3158};
3159
3160/* mcpdm slave ports */
3161static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3162 &omap44xx_l4_abe__mcpdm,
3163 &omap44xx_l4_abe__mcpdm_dma,
3164};
3165
3166static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3167 .name = "mcpdm",
3168 .class = &omap44xx_mcpdm_hwmod_class,
3169 .mpu_irqs = omap44xx_mcpdm_irqs,
407a6888 3170 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
407a6888 3171 .main_clk = "mcpdm_fck",
00fe610b 3172 .prcm = {
407a6888
BC		 3173 .omap4 = {
3174 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3175 },
3176 },
3177 .slaves = omap44xx_mcpdm_slaves,
3178 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3179 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3180};
3181
9bcbd7f0
BC		 3182/*
3183 * 'mcspi' class
3184 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3185 * bus
3186 */
3187
3188static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3189 .rev_offs = 0x0000,
3190 .sysc_offs = 0x0010,
3191 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3192 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3194 SIDLE_SMART_WKUP),
3195 .sysc_fields = &omap_hwmod_sysc_type2,
3196};
3197
3198static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3199 .name = "mcspi",
3200 .sysc = &omap44xx_mcspi_sysc,
905a74d9 3201 .rev = OMAP4_MCSPI_REV,
9bcbd7f0
BC		 3202};
3203
3204/* mcspi1 */
3205static struct omap_hwmod omap44xx_mcspi1_hwmod;
3206static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3207 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
212738a4 3208 { .irq = -1 }
9bcbd7f0
BC		 3209};
3210
3211static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3212 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3213 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3214 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3215 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3216 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3217 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3218 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3219 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
bc614958 3220 { .dma_req = -1 }
9bcbd7f0
BC		 3221};
3222
3223static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3224 {
3225 .pa_start = 0x48098000,
3226 .pa_end = 0x480981ff,
3227 .flags = ADDR_TYPE_RT
3228 },
78183f3f 3229 { }
9bcbd7f0
BC		 3230};
3231
3232/* l4_per -> mcspi1 */
3233static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3234 .master = &omap44xx_l4_per_hwmod,
3235 .slave = &omap44xx_mcspi1_hwmod,
3236 .clk = "l4_div_ck",
3237 .addr = omap44xx_mcspi1_addrs,
9bcbd7f0
BC		 3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239};
3240
3241/* mcspi1 slave ports */
3242static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3243 &omap44xx_l4_per__mcspi1,
3244};
3245
905a74d9
BC		 3246/* mcspi1 dev_attr */
3247static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3248 .num_chipselect = 4,
3249};
3250
9bcbd7f0
BC		 3251static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3252 .name = "mcspi1",
3253 .class = &omap44xx_mcspi_hwmod_class,
3254 .mpu_irqs = omap44xx_mcspi1_irqs,
9bcbd7f0 3255 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
9bcbd7f0
BC		 3256 .main_clk = "mcspi1_fck",
3257 .prcm = {
3258 .omap4 = {
3259 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3260 },
3261 },
905a74d9 3262 .dev_attr = &mcspi1_dev_attr,
9bcbd7f0
BC		 3263 .slaves = omap44xx_mcspi1_slaves,
3264 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3266};
3267
3268/* mcspi2 */
3269static struct omap_hwmod omap44xx_mcspi2_hwmod;
3270static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3271 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
212738a4 3272 { .irq = -1 }
9bcbd7f0
BC		 3273};
3274
3275static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3276 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3277 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3278 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3279 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
bc614958 3280 { .dma_req = -1 }
9bcbd7f0
BC		 3281};
3282
3283static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3284 {
3285 .pa_start = 0x4809a000,
3286 .pa_end = 0x4809a1ff,
3287 .flags = ADDR_TYPE_RT
3288 },
78183f3f 3289 { }
9bcbd7f0
BC		 3290};
3291
3292/* l4_per -> mcspi2 */
3293static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3294 .master = &omap44xx_l4_per_hwmod,
3295 .slave = &omap44xx_mcspi2_hwmod,
3296 .clk = "l4_div_ck",
3297 .addr = omap44xx_mcspi2_addrs,
9bcbd7f0
BC		 3298 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299};
3300
3301/* mcspi2 slave ports */
3302static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3303 &omap44xx_l4_per__mcspi2,
3304};
3305
905a74d9
BC		 3306/* mcspi2 dev_attr */
3307static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3308 .num_chipselect = 2,
3309};
3310
9bcbd7f0
BC		 3311static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3312 .name = "mcspi2",
3313 .class = &omap44xx_mcspi_hwmod_class,
3314 .mpu_irqs = omap44xx_mcspi2_irqs,
9bcbd7f0 3315 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
9bcbd7f0
BC		 3316 .main_clk = "mcspi2_fck",
3317 .prcm = {
3318 .omap4 = {
3319 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3320 },
3321 },
905a74d9 3322 .dev_attr = &mcspi2_dev_attr,
9bcbd7f0
BC		 3323 .slaves = omap44xx_mcspi2_slaves,
3324 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3325 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3326};
3327
3328/* mcspi3 */
3329static struct omap_hwmod omap44xx_mcspi3_hwmod;
3330static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3331 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
212738a4 3332 { .irq = -1 }
9bcbd7f0
BC		 3333};
3334
3335static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3336 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3337 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3338 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3339 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
bc614958 3340 { .dma_req = -1 }
9bcbd7f0
BC		 3341};
3342
3343static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3344 {
3345 .pa_start = 0x480b8000,
3346 .pa_end = 0x480b81ff,
3347 .flags = ADDR_TYPE_RT
3348 },
78183f3f 3349 { }
9bcbd7f0
BC		 3350};
3351
3352/* l4_per -> mcspi3 */
3353static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3354 .master = &omap44xx_l4_per_hwmod,
3355 .slave = &omap44xx_mcspi3_hwmod,
3356 .clk = "l4_div_ck",
3357 .addr = omap44xx_mcspi3_addrs,
9bcbd7f0
BC		 3358 .user = OCP_USER_MPU | OCP_USER_SDMA,
3359};
3360
3361/* mcspi3 slave ports */
3362static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3363 &omap44xx_l4_per__mcspi3,
3364};
3365
905a74d9
BC		 3366/* mcspi3 dev_attr */
3367static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3368 .num_chipselect = 2,
3369};
3370
9bcbd7f0
BC		 3371static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3372 .name = "mcspi3",
3373 .class = &omap44xx_mcspi_hwmod_class,
3374 .mpu_irqs = omap44xx_mcspi3_irqs,
9bcbd7f0 3375 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
9bcbd7f0
BC		 3376 .main_clk = "mcspi3_fck",
3377 .prcm = {
3378 .omap4 = {
3379 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3380 },
3381 },
905a74d9 3382 .dev_attr = &mcspi3_dev_attr,
9bcbd7f0
BC		 3383 .slaves = omap44xx_mcspi3_slaves,
3384 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3385 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3386};
3387
3388/* mcspi4 */
3389static struct omap_hwmod omap44xx_mcspi4_hwmod;
3390static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3391 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
212738a4 3392 { .irq = -1 }
9bcbd7f0
BC		 3393};
3394
3395static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3396 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3397 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
bc614958 3398 { .dma_req = -1 }
9bcbd7f0
BC		 3399};
3400
3401static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3402 {
3403 .pa_start = 0x480ba000,
3404 .pa_end = 0x480ba1ff,
3405 .flags = ADDR_TYPE_RT
3406 },
78183f3f 3407 { }
9bcbd7f0
BC		 3408};
3409
3410/* l4_per -> mcspi4 */
3411static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3412 .master = &omap44xx_l4_per_hwmod,
3413 .slave = &omap44xx_mcspi4_hwmod,
3414 .clk = "l4_div_ck",
3415 .addr = omap44xx_mcspi4_addrs,
9bcbd7f0
BC		 3416 .user = OCP_USER_MPU | OCP_USER_SDMA,
3417};
3418
3419/* mcspi4 slave ports */
3420static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3421 &omap44xx_l4_per__mcspi4,
3422};
3423
905a74d9
BC		 3424/* mcspi4 dev_attr */
3425static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3426 .num_chipselect = 1,
3427};
3428
9bcbd7f0
BC		 3429static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3430 .name = "mcspi4",
3431 .class = &omap44xx_mcspi_hwmod_class,
3432 .mpu_irqs = omap44xx_mcspi4_irqs,
9bcbd7f0 3433 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
9bcbd7f0
BC		 3434 .main_clk = "mcspi4_fck",
3435 .prcm = {
3436 .omap4 = {
3437 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3438 },
3439 },
905a74d9 3440 .dev_attr = &mcspi4_dev_attr,
9bcbd7f0
BC		 3441 .slaves = omap44xx_mcspi4_slaves,
3442 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3443 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3444};
3445
407a6888
BC		 3446/*
3447 * 'mmc' class
3448 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3449 */
3450
3451static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3452 .rev_offs = 0x0000,
3453 .sysc_offs = 0x0010,
3454 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3455 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3456 SYSC_HAS_SOFTRESET),
3457 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3458 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 3459 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 3460 .sysc_fields = &omap_hwmod_sysc_type2,
3461};
3462
3463static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3464 .name = "mmc",
3465 .sysc = &omap44xx_mmc_sysc,
3466};
3467
3468/* mmc1 */
3469static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3470 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
212738a4 3471 { .irq = -1 }
407a6888
BC		 3472};
3473
3474static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3475 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3476 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
bc614958 3477 { .dma_req = -1 }
407a6888
BC		 3478};
3479
3480/* mmc1 master ports */
3481static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3482 &omap44xx_mmc1__l3_main_1,
3483};
3484
3485static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3486 {
3487 .pa_start = 0x4809c000,
3488 .pa_end = 0x4809c3ff,
3489 .flags = ADDR_TYPE_RT
3490 },
78183f3f 3491 { }
407a6888
BC		 3492};
3493
3494/* l4_per -> mmc1 */
3495static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3496 .master = &omap44xx_l4_per_hwmod,
3497 .slave = &omap44xx_mmc1_hwmod,
3498 .clk = "l4_div_ck",
3499 .addr = omap44xx_mmc1_addrs,
407a6888
BC		 3500 .user = OCP_USER_MPU | OCP_USER_SDMA,
3501};
3502
3503/* mmc1 slave ports */
3504static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3505 &omap44xx_l4_per__mmc1,
3506};
3507
6ab8946f
KK		 3508/* mmc1 dev_attr */
3509static struct omap_mmc_dev_attr mmc1_dev_attr = {
3510 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3511};
3512
407a6888
BC		 3513static struct omap_hwmod omap44xx_mmc1_hwmod = {
3514 .name = "mmc1",
3515 .class = &omap44xx_mmc_hwmod_class,
3516 .mpu_irqs = omap44xx_mmc1_irqs,
407a6888 3517 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
407a6888 3518 .main_clk = "mmc1_fck",
00fe610b 3519 .prcm = {
407a6888
BC		 3520 .omap4 = {
3521 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3522 },
3523 },
6ab8946f 3524 .dev_attr = &mmc1_dev_attr,
407a6888
BC		 3525 .slaves = omap44xx_mmc1_slaves,
3526 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3527 .masters = omap44xx_mmc1_masters,
3528 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3530};
3531
3532/* mmc2 */
3533static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3534 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
212738a4 3535 { .irq = -1 }
407a6888
BC		 3536};
3537
3538static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3539 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3540 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
bc614958 3541 { .dma_req = -1 }
407a6888
BC		 3542};
3543
3544/* mmc2 master ports */
3545static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3546 &omap44xx_mmc2__l3_main_1,
3547};
3548
3549static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3550 {
3551 .pa_start = 0x480b4000,
3552 .pa_end = 0x480b43ff,
3553 .flags = ADDR_TYPE_RT
3554 },
78183f3f 3555 { }
407a6888
BC		 3556};
3557
3558/* l4_per -> mmc2 */
3559static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3560 .master = &omap44xx_l4_per_hwmod,
3561 .slave = &omap44xx_mmc2_hwmod,
3562 .clk = "l4_div_ck",
3563 .addr = omap44xx_mmc2_addrs,
407a6888
BC		 3564 .user = OCP_USER_MPU | OCP_USER_SDMA,
3565};
3566
3567/* mmc2 slave ports */
3568static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3569 &omap44xx_l4_per__mmc2,
3570};
3571
3572static struct omap_hwmod omap44xx_mmc2_hwmod = {
3573 .name = "mmc2",
3574 .class = &omap44xx_mmc_hwmod_class,
3575 .mpu_irqs = omap44xx_mmc2_irqs,
407a6888 3576 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
407a6888 3577 .main_clk = "mmc2_fck",
00fe610b 3578 .prcm = {
407a6888
BC		 3579 .omap4 = {
3580 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3581 },
3582 },
3583 .slaves = omap44xx_mmc2_slaves,
3584 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3585 .masters = omap44xx_mmc2_masters,
3586 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3587 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3588};
3589
3590/* mmc3 */
3591static struct omap_hwmod omap44xx_mmc3_hwmod;
3592static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3593 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
212738a4 3594 { .irq = -1 }
407a6888
BC		 3595};
3596
3597static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3598 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3599 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
bc614958 3600 { .dma_req = -1 }
407a6888
BC		 3601};
3602
3603static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3604 {
3605 .pa_start = 0x480ad000,
3606 .pa_end = 0x480ad3ff,
3607 .flags = ADDR_TYPE_RT
3608 },
78183f3f 3609 { }
407a6888
BC		 3610};
3611
3612/* l4_per -> mmc3 */
3613static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3614 .master = &omap44xx_l4_per_hwmod,
3615 .slave = &omap44xx_mmc3_hwmod,
3616 .clk = "l4_div_ck",
3617 .addr = omap44xx_mmc3_addrs,
407a6888
BC		 3618 .user = OCP_USER_MPU | OCP_USER_SDMA,
3619};
3620
3621/* mmc3 slave ports */
3622static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3623 &omap44xx_l4_per__mmc3,
3624};
3625
3626static struct omap_hwmod omap44xx_mmc3_hwmod = {
3627 .name = "mmc3",
3628 .class = &omap44xx_mmc_hwmod_class,
3629 .mpu_irqs = omap44xx_mmc3_irqs,
407a6888 3630 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
407a6888 3631 .main_clk = "mmc3_fck",
00fe610b 3632 .prcm = {
407a6888
BC		 3633 .omap4 = {
3634 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3635 },
3636 },
3637 .slaves = omap44xx_mmc3_slaves,
3638 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3639 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3640};
3641
3642/* mmc4 */
3643static struct omap_hwmod omap44xx_mmc4_hwmod;
3644static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3645 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
212738a4 3646 { .irq = -1 }
407a6888
BC		 3647};
3648
3649static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3650 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3651 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
bc614958 3652 { .dma_req = -1 }
407a6888
BC		 3653};
3654
3655static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3656 {
3657 .pa_start = 0x480d1000,
3658 .pa_end = 0x480d13ff,
3659 .flags = ADDR_TYPE_RT
3660 },
78183f3f 3661 { }
407a6888
BC		 3662};
3663
3664/* l4_per -> mmc4 */
3665static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3666 .master = &omap44xx_l4_per_hwmod,
3667 .slave = &omap44xx_mmc4_hwmod,
3668 .clk = "l4_div_ck",
3669 .addr = omap44xx_mmc4_addrs,
407a6888
BC		 3670 .user = OCP_USER_MPU | OCP_USER_SDMA,
3671};
3672
3673/* mmc4 slave ports */
3674static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3675 &omap44xx_l4_per__mmc4,
3676};
3677
3678static struct omap_hwmod omap44xx_mmc4_hwmod = {
3679 .name = "mmc4",
3680 .class = &omap44xx_mmc_hwmod_class,
3681 .mpu_irqs = omap44xx_mmc4_irqs,
212738a4 3682
407a6888 3683 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
407a6888 3684 .main_clk = "mmc4_fck",
00fe610b 3685 .prcm = {
407a6888
BC		 3686 .omap4 = {
3687 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3688 },
3689 },
3690 .slaves = omap44xx_mmc4_slaves,
3691 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3692 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3693};
3694
3695/* mmc5 */
3696static struct omap_hwmod omap44xx_mmc5_hwmod;
3697static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3698 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
212738a4 3699 { .irq = -1 }
407a6888
BC		 3700};
3701
3702static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3703 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3704 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
bc614958 3705 { .dma_req = -1 }
407a6888
BC		 3706};
3707
3708static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3709 {
3710 .pa_start = 0x480d5000,
3711 .pa_end = 0x480d53ff,
3712 .flags = ADDR_TYPE_RT
3713 },
78183f3f 3714 { }
407a6888
BC		 3715};
3716
3717/* l4_per -> mmc5 */
3718static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3719 .master = &omap44xx_l4_per_hwmod,
3720 .slave = &omap44xx_mmc5_hwmod,
3721 .clk = "l4_div_ck",
3722 .addr = omap44xx_mmc5_addrs,
407a6888
BC		 3723 .user = OCP_USER_MPU | OCP_USER_SDMA,
3724};
3725
3726/* mmc5 slave ports */
3727static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3728 &omap44xx_l4_per__mmc5,
3729};
3730
3731static struct omap_hwmod omap44xx_mmc5_hwmod = {
3732 .name = "mmc5",
3733 .class = &omap44xx_mmc_hwmod_class,
3734 .mpu_irqs = omap44xx_mmc5_irqs,
407a6888 3735 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
407a6888 3736 .main_clk = "mmc5_fck",
00fe610b 3737 .prcm = {
407a6888
BC		 3738 .omap4 = {
3739 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3740 },
3741 },
3742 .slaves = omap44xx_mmc5_slaves,
3743 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3744 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3745};
3746
3b54baad
BC		 3747/*
3748 * 'mpu' class
3749 * mpu sub-system
3750 */
3751
3752static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3753 .name = "mpu",
db12ba53
BC		 3754};
3755
3b54baad
BC		 3756/* mpu */
3757static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3758 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3759 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3760 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
212738a4 3761 { .irq = -1 }
db12ba53
BC		 3762};
3763
3b54baad
BC		 3764/* mpu master ports */
3765static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3766 &omap44xx_mpu__l3_main_1,
3767 &omap44xx_mpu__l4_abe,
3768 &omap44xx_mpu__dmm,
3769};
3770
3771static struct omap_hwmod omap44xx_mpu_hwmod = {
3772 .name = "mpu",
3773 .class = &omap44xx_mpu_hwmod_class,
7ecc5373 3774 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 3775 .mpu_irqs = omap44xx_mpu_irqs,
3b54baad 3776 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3777 .prcm = {
3778 .omap4 = {
3b54baad 3779 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 3780 },
3781 },
3b54baad
BC		 3782 .masters = omap44xx_mpu_masters,
3783 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3784 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3785};
3786
1f6a717f
BC		 3787/*
3788 * 'smartreflex' class
3789 * smartreflex module (monitor silicon performance and outputs a measure of
3790 * performance error)
3791 */
3792
3793/* The IP is not compliant to type1 / type2 scheme */
3794static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3795 .sidle_shift = 24,
3796 .enwkup_shift = 26,
3797};
3798
3799static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3800 .sysc_offs = 0x0038,
3801 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3802 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3803 SIDLE_SMART_WKUP),
3804 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3805};
3806
3807static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3808 .name = "smartreflex",
3809 .sysc = &omap44xx_smartreflex_sysc,
3810 .rev = 2,
1f6a717f
BC		 3811};
3812
3813/* smartreflex_core */
3814static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3815static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3816 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
212738a4 3817 { .irq = -1 }
1f6a717f
BC		 3818};
3819
3820static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3821 {
3822 .pa_start = 0x4a0dd000,
3823 .pa_end = 0x4a0dd03f,
3824 .flags = ADDR_TYPE_RT
3825 },
78183f3f 3826 { }
1f6a717f
BC		 3827};
3828
3829/* l4_cfg -> smartreflex_core */
3830static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3831 .master = &omap44xx_l4_cfg_hwmod,
3832 .slave = &omap44xx_smartreflex_core_hwmod,
3833 .clk = "l4_div_ck",
3834 .addr = omap44xx_smartreflex_core_addrs,
1f6a717f
BC		 3835 .user = OCP_USER_MPU | OCP_USER_SDMA,
3836};
3837
3838/* smartreflex_core slave ports */
3839static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3840 &omap44xx_l4_cfg__smartreflex_core,
3841};
3842
3843static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3844 .name = "smartreflex_core",
3845 .class = &omap44xx_smartreflex_hwmod_class,
3846 .mpu_irqs = omap44xx_smartreflex_core_irqs,
212738a4 3847
1f6a717f
BC		 3848 .main_clk = "smartreflex_core_fck",
3849 .vdd_name = "core",
3850 .prcm = {
3851 .omap4 = {
3852 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3853 },
3854 },
3855 .slaves = omap44xx_smartreflex_core_slaves,
3856 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3857 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3858};
3859
3860/* smartreflex_iva */
3861static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3862static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3863 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
212738a4 3864 { .irq = -1 }
1f6a717f
BC		 3865};
3866
3867static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3868 {
3869 .pa_start = 0x4a0db000,
3870 .pa_end = 0x4a0db03f,
3871 .flags = ADDR_TYPE_RT
3872 },
78183f3f 3873 { }
1f6a717f
BC		 3874};
3875
3876/* l4_cfg -> smartreflex_iva */
3877static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3878 .master = &omap44xx_l4_cfg_hwmod,
3879 .slave = &omap44xx_smartreflex_iva_hwmod,
3880 .clk = "l4_div_ck",
3881 .addr = omap44xx_smartreflex_iva_addrs,
1f6a717f
BC		 3882 .user = OCP_USER_MPU | OCP_USER_SDMA,
3883};
3884
3885/* smartreflex_iva slave ports */
3886static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3887 &omap44xx_l4_cfg__smartreflex_iva,
3888};
3889
3890static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3891 .name = "smartreflex_iva",
3892 .class = &omap44xx_smartreflex_hwmod_class,
3893 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1f6a717f
BC		 3894 .main_clk = "smartreflex_iva_fck",
3895 .vdd_name = "iva",
3896 .prcm = {
3897 .omap4 = {
3898 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3899 },
3900 },
3901 .slaves = omap44xx_smartreflex_iva_slaves,
3902 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3903 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3904};
3905
3906/* smartreflex_mpu */
3907static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3908static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3909 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
212738a4 3910 { .irq = -1 }
1f6a717f
BC		 3911};
3912
3913static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3914 {
3915 .pa_start = 0x4a0d9000,
3916 .pa_end = 0x4a0d903f,
3917 .flags = ADDR_TYPE_RT
3918 },
78183f3f 3919 { }
1f6a717f
BC		 3920};
3921
3922/* l4_cfg -> smartreflex_mpu */
3923static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3924 .master = &omap44xx_l4_cfg_hwmod,
3925 .slave = &omap44xx_smartreflex_mpu_hwmod,
3926 .clk = "l4_div_ck",
3927 .addr = omap44xx_smartreflex_mpu_addrs,
1f6a717f
BC		 3928 .user = OCP_USER_MPU | OCP_USER_SDMA,
3929};
3930
3931/* smartreflex_mpu slave ports */
3932static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3933 &omap44xx_l4_cfg__smartreflex_mpu,
3934};
3935
3936static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3937 .name = "smartreflex_mpu",
3938 .class = &omap44xx_smartreflex_hwmod_class,
3939 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1f6a717f
BC		 3940 .main_clk = "smartreflex_mpu_fck",
3941 .vdd_name = "mpu",
3942 .prcm = {
3943 .omap4 = {
3944 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3945 },
3946 },
3947 .slaves = omap44xx_smartreflex_mpu_slaves,
3948 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3949 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3950};
3951
d11c217f
BC		 3952/*
3953 * 'spinlock' class
3954 * spinlock provides hardware assistance for synchronizing the processes
3955 * running on multiple processors
3956 */
3957
3958static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3959 .rev_offs = 0x0000,
3960 .sysc_offs = 0x0010,
3961 .syss_offs = 0x0014,
3962 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3963 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3964 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3965 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3966 SIDLE_SMART_WKUP),
3967 .sysc_fields = &omap_hwmod_sysc_type1,
3968};
3969
3970static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3971 .name = "spinlock",
3972 .sysc = &omap44xx_spinlock_sysc,
3973};
3974
3975/* spinlock */
3976static struct omap_hwmod omap44xx_spinlock_hwmod;
3977static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3978 {
3979 .pa_start = 0x4a0f6000,
3980 .pa_end = 0x4a0f6fff,
3981 .flags = ADDR_TYPE_RT
3982 },
78183f3f 3983 { }
d11c217f
BC		 3984};
3985
3986/* l4_cfg -> spinlock */
3987static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3988 .master = &omap44xx_l4_cfg_hwmod,
3989 .slave = &omap44xx_spinlock_hwmod,
3990 .clk = "l4_div_ck",
3991 .addr = omap44xx_spinlock_addrs,
d11c217f
BC		 3992 .user = OCP_USER_MPU | OCP_USER_SDMA,
3993};
3994
3995/* spinlock slave ports */
3996static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3997 &omap44xx_l4_cfg__spinlock,
3998};
3999
4000static struct omap_hwmod omap44xx_spinlock_hwmod = {
4001 .name = "spinlock",
4002 .class = &omap44xx_spinlock_hwmod_class,
4003 .prcm = {
4004 .omap4 = {
4005 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
4006 },
4007 },
4008 .slaves = omap44xx_spinlock_slaves,
4009 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4010 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4011};
4012
35d1a66a
BC		 4013/*
4014 * 'timer' class
4015 * general purpose timer module with accurate 1ms tick
4016 * This class contains several variants: ['timer_1ms', 'timer']
4017 */
4018
4019static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4020 .rev_offs = 0x0000,
4021 .sysc_offs = 0x0010,
4022 .syss_offs = 0x0014,
4023 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4024 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4025 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4026 SYSS_HAS_RESET_STATUS),
4027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4028 .sysc_fields = &omap_hwmod_sysc_type1,
4029};
4030
4031static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4032 .name = "timer",
4033 .sysc = &omap44xx_timer_1ms_sysc,
4034};
4035
4036static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4037 .rev_offs = 0x0000,
4038 .sysc_offs = 0x0010,
4039 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4040 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4041 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4042 SIDLE_SMART_WKUP),
4043 .sysc_fields = &omap_hwmod_sysc_type2,
4044};
4045
4046static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4047 .name = "timer",
4048 .sysc = &omap44xx_timer_sysc,
4049};
4050
4051/* timer1 */
4052static struct omap_hwmod omap44xx_timer1_hwmod;
4053static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4054 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
212738a4 4055 { .irq = -1 }
35d1a66a
BC		 4056};
4057
4058static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4059 {
4060 .pa_start = 0x4a318000,
4061 .pa_end = 0x4a31807f,
4062 .flags = ADDR_TYPE_RT
4063 },
78183f3f 4064 { }
35d1a66a
BC		 4065};
4066
4067/* l4_wkup -> timer1 */
4068static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4069 .master = &omap44xx_l4_wkup_hwmod,
4070 .slave = &omap44xx_timer1_hwmod,
4071 .clk = "l4_wkup_clk_mux_ck",
4072 .addr = omap44xx_timer1_addrs,
35d1a66a
BC		 4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074};
4075
4076/* timer1 slave ports */
4077static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4078 &omap44xx_l4_wkup__timer1,
4079};
4080
4081static struct omap_hwmod omap44xx_timer1_hwmod = {
4082 .name = "timer1",
4083 .class = &omap44xx_timer_1ms_hwmod_class,
4084 .mpu_irqs = omap44xx_timer1_irqs,
35d1a66a
BC		 4085 .main_clk = "timer1_fck",
4086 .prcm = {
4087 .omap4 = {
4088 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4089 },
4090 },
4091 .slaves = omap44xx_timer1_slaves,
4092 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4093 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4094};
4095
4096/* timer2 */
4097static struct omap_hwmod omap44xx_timer2_hwmod;
4098static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4099 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
212738a4 4100 { .irq = -1 }
35d1a66a
BC		 4101};
4102
4103static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4104 {
4105 .pa_start = 0x48032000,
4106 .pa_end = 0x4803207f,
4107 .flags = ADDR_TYPE_RT
4108 },
78183f3f 4109 { }
35d1a66a
BC		 4110};
4111
4112/* l4_per -> timer2 */
4113static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4114 .master = &omap44xx_l4_per_hwmod,
4115 .slave = &omap44xx_timer2_hwmod,
4116 .clk = "l4_div_ck",
4117 .addr = omap44xx_timer2_addrs,
35d1a66a
BC		 4118 .user = OCP_USER_MPU | OCP_USER_SDMA,
4119};
4120
4121/* timer2 slave ports */
4122static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4123 &omap44xx_l4_per__timer2,
4124};
4125
4126static struct omap_hwmod omap44xx_timer2_hwmod = {
4127 .name = "timer2",
4128 .class = &omap44xx_timer_1ms_hwmod_class,
4129 .mpu_irqs = omap44xx_timer2_irqs,
35d1a66a
BC		 4130 .main_clk = "timer2_fck",
4131 .prcm = {
4132 .omap4 = {
4133 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4134 },
4135 },
4136 .slaves = omap44xx_timer2_slaves,
4137 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4139};
4140
4141/* timer3 */
4142static struct omap_hwmod omap44xx_timer3_hwmod;
4143static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4144 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
212738a4 4145 { .irq = -1 }
35d1a66a
BC		 4146};
4147
4148static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4149 {
4150 .pa_start = 0x48034000,
4151 .pa_end = 0x4803407f,
4152 .flags = ADDR_TYPE_RT
4153 },
78183f3f 4154 { }
35d1a66a
BC		 4155};
4156
4157/* l4_per -> timer3 */
4158static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4159 .master = &omap44xx_l4_per_hwmod,
4160 .slave = &omap44xx_timer3_hwmod,
4161 .clk = "l4_div_ck",
4162 .addr = omap44xx_timer3_addrs,
35d1a66a
BC		 4163 .user = OCP_USER_MPU | OCP_USER_SDMA,
4164};
4165
4166/* timer3 slave ports */
4167static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4168 &omap44xx_l4_per__timer3,
4169};
4170
4171static struct omap_hwmod omap44xx_timer3_hwmod = {
4172 .name = "timer3",
4173 .class = &omap44xx_timer_hwmod_class,
4174 .mpu_irqs = omap44xx_timer3_irqs,
35d1a66a
BC		 4175 .main_clk = "timer3_fck",
4176 .prcm = {
4177 .omap4 = {
4178 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4179 },
4180 },
4181 .slaves = omap44xx_timer3_slaves,
4182 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4184};
4185
4186/* timer4 */
4187static struct omap_hwmod omap44xx_timer4_hwmod;
4188static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4189 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
212738a4 4190 { .irq = -1 }
35d1a66a
BC		 4191};
4192
4193static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4194 {
4195 .pa_start = 0x48036000,
4196 .pa_end = 0x4803607f,
4197 .flags = ADDR_TYPE_RT
4198 },
78183f3f 4199 { }
35d1a66a
BC		 4200};
4201
4202/* l4_per -> timer4 */
4203static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4204 .master = &omap44xx_l4_per_hwmod,
4205 .slave = &omap44xx_timer4_hwmod,
4206 .clk = "l4_div_ck",
4207 .addr = omap44xx_timer4_addrs,
35d1a66a
BC		 4208 .user = OCP_USER_MPU | OCP_USER_SDMA,
4209};
4210
4211/* timer4 slave ports */
4212static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4213 &omap44xx_l4_per__timer4,
4214};
4215
4216static struct omap_hwmod omap44xx_timer4_hwmod = {
4217 .name = "timer4",
4218 .class = &omap44xx_timer_hwmod_class,
4219 .mpu_irqs = omap44xx_timer4_irqs,
35d1a66a
BC		 4220 .main_clk = "timer4_fck",
4221 .prcm = {
4222 .omap4 = {
4223 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4224 },
4225 },
4226 .slaves = omap44xx_timer4_slaves,
4227 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4229};
4230
4231/* timer5 */
4232static struct omap_hwmod omap44xx_timer5_hwmod;
4233static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4234 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
212738a4 4235 { .irq = -1 }
35d1a66a
BC		 4236};
4237
4238static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4239 {
4240 .pa_start = 0x40138000,
4241 .pa_end = 0x4013807f,
4242 .flags = ADDR_TYPE_RT
4243 },
78183f3f 4244 { }
35d1a66a
BC		 4245};
4246
4247/* l4_abe -> timer5 */
4248static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4249 .master = &omap44xx_l4_abe_hwmod,
4250 .slave = &omap44xx_timer5_hwmod,
4251 .clk = "ocp_abe_iclk",
4252 .addr = omap44xx_timer5_addrs,
35d1a66a
BC		 4253 .user = OCP_USER_MPU,
4254};
4255
4256static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4257 {
4258 .pa_start = 0x49038000,
4259 .pa_end = 0x4903807f,
4260 .flags = ADDR_TYPE_RT
4261 },
78183f3f 4262 { }
35d1a66a
BC		 4263};
4264
4265/* l4_abe -> timer5 (dma) */
4266static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4267 .master = &omap44xx_l4_abe_hwmod,
4268 .slave = &omap44xx_timer5_hwmod,
4269 .clk = "ocp_abe_iclk",
4270 .addr = omap44xx_timer5_dma_addrs,
35d1a66a
BC		 4271 .user = OCP_USER_SDMA,
4272};
4273
4274/* timer5 slave ports */
4275static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4276 &omap44xx_l4_abe__timer5,
4277 &omap44xx_l4_abe__timer5_dma,
4278};
4279
4280static struct omap_hwmod omap44xx_timer5_hwmod = {
4281 .name = "timer5",
4282 .class = &omap44xx_timer_hwmod_class,
4283 .mpu_irqs = omap44xx_timer5_irqs,
35d1a66a
BC		 4284 .main_clk = "timer5_fck",
4285 .prcm = {
4286 .omap4 = {
4287 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4288 },
4289 },
4290 .slaves = omap44xx_timer5_slaves,
4291 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4292 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4293};
4294
4295/* timer6 */
4296static struct omap_hwmod omap44xx_timer6_hwmod;
4297static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4298 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
212738a4 4299 { .irq = -1 }
35d1a66a
BC		 4300};
4301
4302static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4303 {
4304 .pa_start = 0x4013a000,
4305 .pa_end = 0x4013a07f,
4306 .flags = ADDR_TYPE_RT
4307 },
78183f3f 4308 { }
35d1a66a
BC		 4309};
4310
4311/* l4_abe -> timer6 */
4312static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4313 .master = &omap44xx_l4_abe_hwmod,
4314 .slave = &omap44xx_timer6_hwmod,
4315 .clk = "ocp_abe_iclk",
4316 .addr = omap44xx_timer6_addrs,
35d1a66a
BC		 4317 .user = OCP_USER_MPU,
4318};
4319
4320static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4321 {
4322 .pa_start = 0x4903a000,
4323 .pa_end = 0x4903a07f,
4324 .flags = ADDR_TYPE_RT
4325 },
78183f3f 4326 { }
35d1a66a
BC		 4327};
4328
4329/* l4_abe -> timer6 (dma) */
4330static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4331 .master = &omap44xx_l4_abe_hwmod,
4332 .slave = &omap44xx_timer6_hwmod,
4333 .clk = "ocp_abe_iclk",
4334 .addr = omap44xx_timer6_dma_addrs,
35d1a66a
BC		 4335 .user = OCP_USER_SDMA,
4336};
4337
4338/* timer6 slave ports */
4339static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4340 &omap44xx_l4_abe__timer6,
4341 &omap44xx_l4_abe__timer6_dma,
4342};
4343
4344static struct omap_hwmod omap44xx_timer6_hwmod = {
4345 .name = "timer6",
4346 .class = &omap44xx_timer_hwmod_class,
4347 .mpu_irqs = omap44xx_timer6_irqs,
212738a4 4348
35d1a66a
BC		 4349 .main_clk = "timer6_fck",
4350 .prcm = {
4351 .omap4 = {
4352 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4353 },
4354 },
4355 .slaves = omap44xx_timer6_slaves,
4356 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4358};
4359
4360/* timer7 */
4361static struct omap_hwmod omap44xx_timer7_hwmod;
4362static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4363 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
212738a4 4364 { .irq = -1 }
35d1a66a
BC		 4365};
4366
4367static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4368 {
4369 .pa_start = 0x4013c000,
4370 .pa_end = 0x4013c07f,
4371 .flags = ADDR_TYPE_RT
4372 },
78183f3f 4373 { }
35d1a66a
BC		 4374};
4375
4376/* l4_abe -> timer7 */
4377static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4378 .master = &omap44xx_l4_abe_hwmod,
4379 .slave = &omap44xx_timer7_hwmod,
4380 .clk = "ocp_abe_iclk",
4381 .addr = omap44xx_timer7_addrs,
35d1a66a
BC		 4382 .user = OCP_USER_MPU,
4383};
4384
4385static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4386 {
4387 .pa_start = 0x4903c000,
4388 .pa_end = 0x4903c07f,
4389 .flags = ADDR_TYPE_RT
4390 },
78183f3f 4391 { }
35d1a66a
BC		 4392};
4393
4394/* l4_abe -> timer7 (dma) */
4395static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4396 .master = &omap44xx_l4_abe_hwmod,
4397 .slave = &omap44xx_timer7_hwmod,
4398 .clk = "ocp_abe_iclk",
4399 .addr = omap44xx_timer7_dma_addrs,
35d1a66a
BC		 4400 .user = OCP_USER_SDMA,
4401};
4402
4403/* timer7 slave ports */
4404static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4405 &omap44xx_l4_abe__timer7,
4406 &omap44xx_l4_abe__timer7_dma,
4407};
4408
4409static struct omap_hwmod omap44xx_timer7_hwmod = {
4410 .name = "timer7",
4411 .class = &omap44xx_timer_hwmod_class,
4412 .mpu_irqs = omap44xx_timer7_irqs,
35d1a66a
BC		 4413 .main_clk = "timer7_fck",
4414 .prcm = {
4415 .omap4 = {
4416 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4417 },
4418 },
4419 .slaves = omap44xx_timer7_slaves,
4420 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4421 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4422};
4423
4424/* timer8 */
4425static struct omap_hwmod omap44xx_timer8_hwmod;
4426static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4427 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
212738a4 4428 { .irq = -1 }
35d1a66a
BC		 4429};
4430
4431static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4432 {
4433 .pa_start = 0x4013e000,
4434 .pa_end = 0x4013e07f,
4435 .flags = ADDR_TYPE_RT
4436 },
78183f3f 4437 { }
35d1a66a
BC		 4438};
4439
4440/* l4_abe -> timer8 */
4441static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4442 .master = &omap44xx_l4_abe_hwmod,
4443 .slave = &omap44xx_timer8_hwmod,
4444 .clk = "ocp_abe_iclk",
4445 .addr = omap44xx_timer8_addrs,
35d1a66a
BC		 4446 .user = OCP_USER_MPU,
4447};
4448
4449static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4450 {
4451 .pa_start = 0x4903e000,
4452 .pa_end = 0x4903e07f,
4453 .flags = ADDR_TYPE_RT
4454 },
78183f3f 4455 { }
35d1a66a
BC		 4456};
4457
4458/* l4_abe -> timer8 (dma) */
4459static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4460 .master = &omap44xx_l4_abe_hwmod,
4461 .slave = &omap44xx_timer8_hwmod,
4462 .clk = "ocp_abe_iclk",
4463 .addr = omap44xx_timer8_dma_addrs,
35d1a66a
BC		 4464 .user = OCP_USER_SDMA,
4465};
4466
4467/* timer8 slave ports */
4468static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4469 &omap44xx_l4_abe__timer8,
4470 &omap44xx_l4_abe__timer8_dma,
4471};
4472
4473static struct omap_hwmod omap44xx_timer8_hwmod = {
4474 .name = "timer8",
4475 .class = &omap44xx_timer_hwmod_class,
4476 .mpu_irqs = omap44xx_timer8_irqs,
35d1a66a
BC		 4477 .main_clk = "timer8_fck",
4478 .prcm = {
4479 .omap4 = {
4480 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4481 },
4482 },
4483 .slaves = omap44xx_timer8_slaves,
4484 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4485 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4486};
4487
4488/* timer9 */
4489static struct omap_hwmod omap44xx_timer9_hwmod;
4490static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4491 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
212738a4 4492 { .irq = -1 }
35d1a66a
BC		 4493};
4494
4495static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4496 {
4497 .pa_start = 0x4803e000,
4498 .pa_end = 0x4803e07f,
4499 .flags = ADDR_TYPE_RT
4500 },
78183f3f 4501 { }
35d1a66a
BC		 4502};
4503
4504/* l4_per -> timer9 */
4505static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4506 .master = &omap44xx_l4_per_hwmod,
4507 .slave = &omap44xx_timer9_hwmod,
4508 .clk = "l4_div_ck",
4509 .addr = omap44xx_timer9_addrs,
35d1a66a
BC		 4510 .user = OCP_USER_MPU | OCP_USER_SDMA,
4511};
4512
4513/* timer9 slave ports */
4514static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4515 &omap44xx_l4_per__timer9,
4516};
4517
4518static struct omap_hwmod omap44xx_timer9_hwmod = {
4519 .name = "timer9",
4520 .class = &omap44xx_timer_hwmod_class,
4521 .mpu_irqs = omap44xx_timer9_irqs,
35d1a66a
BC		 4522 .main_clk = "timer9_fck",
4523 .prcm = {
4524 .omap4 = {
4525 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4526 },
4527 },
4528 .slaves = omap44xx_timer9_slaves,
4529 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4530 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4531};
4532
4533/* timer10 */
4534static struct omap_hwmod omap44xx_timer10_hwmod;
4535static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4536 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
212738a4 4537 { .irq = -1 }
35d1a66a
BC		 4538};
4539
4540static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4541 {
4542 .pa_start = 0x48086000,
4543 .pa_end = 0x4808607f,
4544 .flags = ADDR_TYPE_RT
4545 },
78183f3f 4546 { }
35d1a66a
BC		 4547};
4548
4549/* l4_per -> timer10 */
4550static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4551 .master = &omap44xx_l4_per_hwmod,
4552 .slave = &omap44xx_timer10_hwmod,
4553 .clk = "l4_div_ck",
4554 .addr = omap44xx_timer10_addrs,
35d1a66a
BC		 4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
4556};
4557
4558/* timer10 slave ports */
4559static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4560 &omap44xx_l4_per__timer10,
4561};
4562
4563static struct omap_hwmod omap44xx_timer10_hwmod = {
4564 .name = "timer10",
4565 .class = &omap44xx_timer_1ms_hwmod_class,
4566 .mpu_irqs = omap44xx_timer10_irqs,
35d1a66a
BC		 4567 .main_clk = "timer10_fck",
4568 .prcm = {
4569 .omap4 = {
4570 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4571 },
4572 },
4573 .slaves = omap44xx_timer10_slaves,
4574 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4575 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4576};
4577
4578/* timer11 */
4579static struct omap_hwmod omap44xx_timer11_hwmod;
4580static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4581 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
212738a4 4582 { .irq = -1 }
35d1a66a
BC		 4583};
4584
4585static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4586 {
4587 .pa_start = 0x48088000,
4588 .pa_end = 0x4808807f,
4589 .flags = ADDR_TYPE_RT
4590 },
78183f3f 4591 { }
35d1a66a
BC		 4592};
4593
4594/* l4_per -> timer11 */
4595static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4596 .master = &omap44xx_l4_per_hwmod,
4597 .slave = &omap44xx_timer11_hwmod,
4598 .clk = "l4_div_ck",
4599 .addr = omap44xx_timer11_addrs,
35d1a66a
BC		 4600 .user = OCP_USER_MPU | OCP_USER_SDMA,
4601};
4602
4603/* timer11 slave ports */
4604static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4605 &omap44xx_l4_per__timer11,
4606};
4607
4608static struct omap_hwmod omap44xx_timer11_hwmod = {
4609 .name = "timer11",
4610 .class = &omap44xx_timer_hwmod_class,
4611 .mpu_irqs = omap44xx_timer11_irqs,
35d1a66a
BC		 4612 .main_clk = "timer11_fck",
4613 .prcm = {
4614 .omap4 = {
4615 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4616 },
4617 },
4618 .slaves = omap44xx_timer11_slaves,
4619 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4620 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4621};
4622
9780a9cf 4623/*
3b54baad
BC		 4624 * 'uart' class
4625 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4626 */
4627
3b54baad
BC		 4628static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4629 .rev_offs = 0x0050,
4630 .sysc_offs = 0x0054,
4631 .syss_offs = 0x0058,
4632 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4633 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4634 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4636 SIDLE_SMART_WKUP),
9780a9cf
BC		 4637 .sysc_fields = &omap_hwmod_sysc_type1,
4638};
4639
3b54baad 4640static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4641 .name = "uart",
4642 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4643};
4644
3b54baad
BC		 4645/* uart1 */
4646static struct omap_hwmod omap44xx_uart1_hwmod;
4647static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4648 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
212738a4 4649 { .irq = -1 }
9780a9cf
BC		 4650};
4651
3b54baad
BC		 4652static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4653 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4654 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
bc614958 4655 { .dma_req = -1 }
9780a9cf
BC		 4656};
4657
3b54baad 4658static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4659 {
3b54baad
BC		 4660 .pa_start = 0x4806a000,
4661 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4662 .flags = ADDR_TYPE_RT
4663 },
78183f3f 4664 { }
9780a9cf
BC		 4665};
4666
3b54baad
BC		 4667/* l4_per -> uart1 */
4668static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4669 .master = &omap44xx_l4_per_hwmod,
4670 .slave = &omap44xx_uart1_hwmod,
4671 .clk = "l4_div_ck",
4672 .addr = omap44xx_uart1_addrs,
9780a9cf
BC		 4673 .user = OCP_USER_MPU | OCP_USER_SDMA,
4674};
4675
3b54baad
BC		 4676/* uart1 slave ports */
4677static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4678 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4679};
4680
3b54baad
BC		 4681static struct omap_hwmod omap44xx_uart1_hwmod = {
4682 .name = "uart1",
4683 .class = &omap44xx_uart_hwmod_class,
4684 .mpu_irqs = omap44xx_uart1_irqs,
3b54baad 4685 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3b54baad 4686 .main_clk = "uart1_fck",
9780a9cf
BC		 4687 .prcm = {
4688 .omap4 = {
3b54baad 4689 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 4690 },
4691 },
3b54baad
BC		 4692 .slaves = omap44xx_uart1_slaves,
4693 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4694 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4695};
4696
3b54baad
BC		 4697/* uart2 */
4698static struct omap_hwmod omap44xx_uart2_hwmod;
4699static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4700 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
212738a4 4701 { .irq = -1 }
9780a9cf
BC		 4702};
4703
3b54baad
BC		 4704static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4705 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4706 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
bc614958 4707 { .dma_req = -1 }
3b54baad
BC		 4708};
4709
4710static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4711 {
3b54baad
BC		 4712 .pa_start = 0x4806c000,
4713 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4714 .flags = ADDR_TYPE_RT
4715 },
78183f3f 4716 { }
9780a9cf
BC		 4717};
4718
3b54baad
BC		 4719/* l4_per -> uart2 */
4720static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4721 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4722 .slave = &omap44xx_uart2_hwmod,
4723 .clk = "l4_div_ck",
4724 .addr = omap44xx_uart2_addrs,
9780a9cf
BC		 4725 .user = OCP_USER_MPU | OCP_USER_SDMA,
4726};
4727
3b54baad
BC		 4728/* uart2 slave ports */
4729static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4730 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4731};
4732
3b54baad
BC		 4733static struct omap_hwmod omap44xx_uart2_hwmod = {
4734 .name = "uart2",
4735 .class = &omap44xx_uart_hwmod_class,
4736 .mpu_irqs = omap44xx_uart2_irqs,
3b54baad 4737 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3b54baad 4738 .main_clk = "uart2_fck",
9780a9cf
BC		 4739 .prcm = {
4740 .omap4 = {
3b54baad 4741 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 4742 },
4743 },
3b54baad
BC		 4744 .slaves = omap44xx_uart2_slaves,
4745 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4746 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4747};
4748
3b54baad
BC		 4749/* uart3 */
4750static struct omap_hwmod omap44xx_uart3_hwmod;
4751static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4752 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
212738a4 4753 { .irq = -1 }
9780a9cf
BC		 4754};
4755
3b54baad
BC		 4756static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4757 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4758 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
bc614958 4759 { .dma_req = -1 }
3b54baad
BC		 4760};
4761
4762static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4763 {
3b54baad
BC		 4764 .pa_start = 0x48020000,
4765 .pa_end = 0x480200ff,
9780a9cf
BC		 4766 .flags = ADDR_TYPE_RT
4767 },
78183f3f 4768 { }
9780a9cf
BC		 4769};
4770
3b54baad
BC		 4771/* l4_per -> uart3 */
4772static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4773 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4774 .slave = &omap44xx_uart3_hwmod,
4775 .clk = "l4_div_ck",
4776 .addr = omap44xx_uart3_addrs,
9780a9cf
BC		 4777 .user = OCP_USER_MPU | OCP_USER_SDMA,
4778};
4779
3b54baad
BC		 4780/* uart3 slave ports */
4781static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4782 &omap44xx_l4_per__uart3,
4783};
4784
4785static struct omap_hwmod omap44xx_uart3_hwmod = {
4786 .name = "uart3",
4787 .class = &omap44xx_uart_hwmod_class,
7ecc5373 4788 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 4789 .mpu_irqs = omap44xx_uart3_irqs,
3b54baad 4790 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3b54baad 4791 .main_clk = "uart3_fck",
9780a9cf
BC		 4792 .prcm = {
4793 .omap4 = {
3b54baad 4794 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 4795 },
4796 },
3b54baad
BC		 4797 .slaves = omap44xx_uart3_slaves,
4798 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4799 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4800};
4801
3b54baad
BC		 4802/* uart4 */
4803static struct omap_hwmod omap44xx_uart4_hwmod;
4804static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4805 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
212738a4 4806 { .irq = -1 }
9780a9cf
BC		 4807};
4808
3b54baad
BC		 4809static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4810 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4811 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
bc614958 4812 { .dma_req = -1 }
3b54baad
BC		 4813};
4814
4815static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4816 {
3b54baad
BC		 4817 .pa_start = 0x4806e000,
4818 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4819 .flags = ADDR_TYPE_RT
4820 },
78183f3f 4821 { }
9780a9cf
BC		 4822};
4823
3b54baad
BC		 4824/* l4_per -> uart4 */
4825static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4826 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4827 .slave = &omap44xx_uart4_hwmod,
4828 .clk = "l4_div_ck",
4829 .addr = omap44xx_uart4_addrs,
9780a9cf
BC		 4830 .user = OCP_USER_MPU | OCP_USER_SDMA,
4831};
4832
3b54baad
BC		 4833/* uart4 slave ports */
4834static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4835 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4836};
4837
3b54baad
BC		 4838static struct omap_hwmod omap44xx_uart4_hwmod = {
4839 .name = "uart4",
4840 .class = &omap44xx_uart_hwmod_class,
4841 .mpu_irqs = omap44xx_uart4_irqs,
3b54baad 4842 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3b54baad 4843 .main_clk = "uart4_fck",
9780a9cf
BC		 4844 .prcm = {
4845 .omap4 = {
3b54baad 4846 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 4847 },
4848 },
3b54baad
BC		 4849 .slaves = omap44xx_uart4_slaves,
4850 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4851 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4852};
4853
5844c4ea
BC		 4854/*
4855 * 'usb_otg_hs' class
4856 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4857 */
4858
4859static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4860 .rev_offs = 0x0400,
4861 .sysc_offs = 0x0404,
4862 .syss_offs = 0x0408,
4863 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4864 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4865 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4866 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4867 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4868 MSTANDBY_SMART),
4869 .sysc_fields = &omap_hwmod_sysc_type1,
4870};
4871
4872static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
00fe610b
BC		 4873 .name = "usb_otg_hs",
4874 .sysc = &omap44xx_usb_otg_hs_sysc,
5844c4ea
BC		 4875};
4876
4877/* usb_otg_hs */
4878static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4879 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4880 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
212738a4 4881 { .irq = -1 }
5844c4ea
BC		 4882};
4883
4884/* usb_otg_hs master ports */
4885static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4886 &omap44xx_usb_otg_hs__l3_main_2,
4887};
4888
4889static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4890 {
4891 .pa_start = 0x4a0ab000,
4892 .pa_end = 0x4a0ab003,
4893 .flags = ADDR_TYPE_RT
4894 },
78183f3f 4895 { }
5844c4ea
BC		 4896};
4897
4898/* l4_cfg -> usb_otg_hs */
4899static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4900 .master = &omap44xx_l4_cfg_hwmod,
4901 .slave = &omap44xx_usb_otg_hs_hwmod,
4902 .clk = "l4_div_ck",
4903 .addr = omap44xx_usb_otg_hs_addrs,
5844c4ea
BC		 4904 .user = OCP_USER_MPU | OCP_USER_SDMA,
4905};
4906
4907/* usb_otg_hs slave ports */
4908static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4909 &omap44xx_l4_cfg__usb_otg_hs,
4910};
4911
4912static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4913 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4914};
4915
4916static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4917 .name = "usb_otg_hs",
4918 .class = &omap44xx_usb_otg_hs_hwmod_class,
4919 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4920 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5844c4ea
BC		 4921 .main_clk = "usb_otg_hs_ick",
4922 .prcm = {
4923 .omap4 = {
4924 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4925 },
4926 },
4927 .opt_clks = usb_otg_hs_opt_clks,
00fe610b 4928 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5844c4ea
BC		 4929 .slaves = omap44xx_usb_otg_hs_slaves,
4930 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4931 .masters = omap44xx_usb_otg_hs_masters,
4932 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4933 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4934};
4935
3b54baad
BC		 4936/*
4937 * 'wd_timer' class
4938 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4939 * overflow condition
4940 */
4941
4942static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4943 .rev_offs = 0x0000,
4944 .sysc_offs = 0x0010,
4945 .syss_offs = 0x0014,
4946 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 4947 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4949 SIDLE_SMART_WKUP),
3b54baad 4950 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 4951};
4952
3b54baad
BC		 4953static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4954 .name = "wd_timer",
4955 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 4956 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 4957};
4958
4959/* wd_timer2 */
4960static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4961static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4962 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
212738a4 4963 { .irq = -1 }
3b54baad
BC		 4964};
4965
4966static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 4967 {
3b54baad
BC		 4968 .pa_start = 0x4a314000,
4969 .pa_end = 0x4a31407f,
9780a9cf
BC		 4970 .flags = ADDR_TYPE_RT
4971 },
78183f3f 4972 { }
9780a9cf
BC		 4973};
4974
3b54baad
BC		 4975/* l4_wkup -> wd_timer2 */
4976static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4977 .master = &omap44xx_l4_wkup_hwmod,
4978 .slave = &omap44xx_wd_timer2_hwmod,
4979 .clk = "l4_wkup_clk_mux_ck",
4980 .addr = omap44xx_wd_timer2_addrs,
9780a9cf
BC		 4981 .user = OCP_USER_MPU | OCP_USER_SDMA,
4982};
4983
3b54baad
BC		 4984/* wd_timer2 slave ports */
4985static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4986 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 4987};
4988
3b54baad
BC		 4989static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4990 .name = "wd_timer2",
4991 .class = &omap44xx_wd_timer_hwmod_class,
4992 .mpu_irqs = omap44xx_wd_timer2_irqs,
3b54baad 4993 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 4994 .prcm = {
4995 .omap4 = {
3b54baad 4996 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 4997 },
4998 },
3b54baad
BC		 4999 .slaves = omap44xx_wd_timer2_slaves,
5000 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 5001 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5002};
5003
3b54baad
BC		 5004/* wd_timer3 */
5005static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5006static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5007 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
212738a4 5008 { .irq = -1 }
9780a9cf
BC		 5009};
5010
3b54baad 5011static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 5012 {
3b54baad
BC		 5013 .pa_start = 0x40130000,
5014 .pa_end = 0x4013007f,
9780a9cf
BC		 5015 .flags = ADDR_TYPE_RT
5016 },
78183f3f 5017 { }
9780a9cf
BC		 5018};
5019
3b54baad
BC		 5020/* l4_abe -> wd_timer3 */
5021static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5022 .master = &omap44xx_l4_abe_hwmod,
5023 .slave = &omap44xx_wd_timer3_hwmod,
5024 .clk = "ocp_abe_iclk",
5025 .addr = omap44xx_wd_timer3_addrs,
3b54baad 5026 .user = OCP_USER_MPU,
9780a9cf
BC		 5027};
5028
3b54baad
BC		 5029static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5030 {
5031 .pa_start = 0x49030000,
5032 .pa_end = 0x4903007f,
5033 .flags = ADDR_TYPE_RT
5034 },
78183f3f 5035 { }
9780a9cf
BC		 5036};
5037
3b54baad
BC		 5038/* l4_abe -> wd_timer3 (dma) */
5039static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5040 .master = &omap44xx_l4_abe_hwmod,
5041 .slave = &omap44xx_wd_timer3_hwmod,
5042 .clk = "ocp_abe_iclk",
5043 .addr = omap44xx_wd_timer3_dma_addrs,
3b54baad 5044 .user = OCP_USER_SDMA,
9780a9cf
BC		 5045};
5046
3b54baad
BC		 5047/* wd_timer3 slave ports */
5048static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5049 &omap44xx_l4_abe__wd_timer3,
5050 &omap44xx_l4_abe__wd_timer3_dma,
5051};
5052
5053static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5054 .name = "wd_timer3",
5055 .class = &omap44xx_wd_timer_hwmod_class,
5056 .mpu_irqs = omap44xx_wd_timer3_irqs,
3b54baad 5057 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 5058 .prcm = {
5059 .omap4 = {
3b54baad 5060 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 5061 },
5062 },
3b54baad
BC		 5063 .slaves = omap44xx_wd_timer3_slaves,
5064 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 5065 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5066};
531ce0d5 5067
55d2cb08 5068static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 5069
55d2cb08
BC		 5070 /* dmm class */
5071 &omap44xx_dmm_hwmod,
3b54baad 5072
55d2cb08
BC		 5073 /* emif_fw class */
5074 &omap44xx_emif_fw_hwmod,
3b54baad 5075
55d2cb08
BC		 5076 /* l3 class */
5077 &omap44xx_l3_instr_hwmod,
5078 &omap44xx_l3_main_1_hwmod,
5079 &omap44xx_l3_main_2_hwmod,
5080 &omap44xx_l3_main_3_hwmod,
3b54baad 5081
55d2cb08
BC		 5082 /* l4 class */
5083 &omap44xx_l4_abe_hwmod,
5084 &omap44xx_l4_cfg_hwmod,
5085 &omap44xx_l4_per_hwmod,
5086 &omap44xx_l4_wkup_hwmod,
531ce0d5 5087
55d2cb08
BC		 5088 /* mpu_bus class */
5089 &omap44xx_mpu_private_hwmod,
5090
407a6888
BC		 5091 /* aess class */
5092/* &omap44xx_aess_hwmod, */
5093
5094 /* bandgap class */
5095 &omap44xx_bandgap_hwmod,
5096
5097 /* counter class */
5098/* &omap44xx_counter_32k_hwmod, */
5099
d7cf5f33
BC		 5100 /* dma class */
5101 &omap44xx_dma_system_hwmod,
5102
8ca476da
BC		 5103 /* dmic class */
5104 &omap44xx_dmic_hwmod,
5105
8f25bdc5
BC		 5106 /* dsp class */
5107 &omap44xx_dsp_hwmod,
5108 &omap44xx_dsp_c0_hwmod,
5109
d63bd74f
BC		 5110 /* dss class */
5111 &omap44xx_dss_hwmod,
5112 &omap44xx_dss_dispc_hwmod,
5113 &omap44xx_dss_dsi1_hwmod,
5114 &omap44xx_dss_dsi2_hwmod,
5115 &omap44xx_dss_hdmi_hwmod,
5116 &omap44xx_dss_rfbi_hwmod,
5117 &omap44xx_dss_venc_hwmod,
5118
9780a9cf
BC		 5119 /* gpio class */
5120 &omap44xx_gpio1_hwmod,
5121 &omap44xx_gpio2_hwmod,
5122 &omap44xx_gpio3_hwmod,
5123 &omap44xx_gpio4_hwmod,
5124 &omap44xx_gpio5_hwmod,
5125 &omap44xx_gpio6_hwmod,
5126
407a6888
BC		 5127 /* hsi class */
5128/* &omap44xx_hsi_hwmod, */
5129
3b54baad
BC		 5130 /* i2c class */
5131 &omap44xx_i2c1_hwmod,
5132 &omap44xx_i2c2_hwmod,
5133 &omap44xx_i2c3_hwmod,
5134 &omap44xx_i2c4_hwmod,
5135
407a6888
BC		 5136 /* ipu class */
5137 &omap44xx_ipu_hwmod,
5138 &omap44xx_ipu_c0_hwmod,
5139 &omap44xx_ipu_c1_hwmod,
5140
5141 /* iss class */
5142/* &omap44xx_iss_hwmod, */
5143
8f25bdc5
BC		 5144 /* iva class */
5145 &omap44xx_iva_hwmod,
5146 &omap44xx_iva_seq0_hwmod,
5147 &omap44xx_iva_seq1_hwmod,
5148
407a6888 5149 /* kbd class */
4998b245 5150 &omap44xx_kbd_hwmod,
407a6888 5151
ec5df927
BC		 5152 /* mailbox class */
5153 &omap44xx_mailbox_hwmod,
5154
4ddff493
BC		 5155 /* mcbsp class */
5156 &omap44xx_mcbsp1_hwmod,
5157 &omap44xx_mcbsp2_hwmod,
5158 &omap44xx_mcbsp3_hwmod,
5159 &omap44xx_mcbsp4_hwmod,
5160
407a6888
BC		 5161 /* mcpdm class */
5162/* &omap44xx_mcpdm_hwmod, */
5163
9bcbd7f0
BC		 5164 /* mcspi class */
5165 &omap44xx_mcspi1_hwmod,
5166 &omap44xx_mcspi2_hwmod,
5167 &omap44xx_mcspi3_hwmod,
5168 &omap44xx_mcspi4_hwmod,
5169
407a6888 5170 /* mmc class */
17203bda
AG		 5171 &omap44xx_mmc1_hwmod,
5172 &omap44xx_mmc2_hwmod,
5173 &omap44xx_mmc3_hwmod,
5174 &omap44xx_mmc4_hwmod,
5175 &omap44xx_mmc5_hwmod,
407a6888 5176
55d2cb08
BC		 5177 /* mpu class */
5178 &omap44xx_mpu_hwmod,
db12ba53 5179
1f6a717f
BC		 5180 /* smartreflex class */
5181 &omap44xx_smartreflex_core_hwmod,
5182 &omap44xx_smartreflex_iva_hwmod,
5183 &omap44xx_smartreflex_mpu_hwmod,
5184
d11c217f
BC		 5185 /* spinlock class */
5186 &omap44xx_spinlock_hwmod,
5187
35d1a66a
BC		 5188 /* timer class */
5189 &omap44xx_timer1_hwmod,
5190 &omap44xx_timer2_hwmod,
5191 &omap44xx_timer3_hwmod,
5192 &omap44xx_timer4_hwmod,
5193 &omap44xx_timer5_hwmod,
5194 &omap44xx_timer6_hwmod,
5195 &omap44xx_timer7_hwmod,
5196 &omap44xx_timer8_hwmod,
5197 &omap44xx_timer9_hwmod,
5198 &omap44xx_timer10_hwmod,
5199 &omap44xx_timer11_hwmod,
5200
db12ba53
BC		 5201 /* uart class */
5202 &omap44xx_uart1_hwmod,
5203 &omap44xx_uart2_hwmod,
5204 &omap44xx_uart3_hwmod,
5205 &omap44xx_uart4_hwmod,
3b54baad 5206
5844c4ea
BC		 5207 /* usb_otg_hs class */
5208 &omap44xx_usb_otg_hs_hwmod,
5209
3b54baad
BC		 5210 /* wd_timer class */
5211 &omap44xx_wd_timer2_hwmod,
5212 &omap44xx_wd_timer3_hwmod,
5213
55d2cb08
BC		 5214 NULL,
5215};
5216
5217int __init omap44xx_hwmod_init(void)
5218{
550c8092 5219 return omap_hwmod_register(omap44xx_hwmods);
55d2cb08
BC		 5220}
5221
Linux 6.x block layer and io_uring tree(s)