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OMAP4: hwmod data: Change DSS main_clk scheme
[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
905a74d9 27#include <plat/mcspi.h>
cb7e9ded 28#include <plat/mcbsp.h>
6ab8946f 29#include <plat/mmc.h>
55d2cb08
BC		 30
31#include "omap_hwmod_common_data.h"
32
d198b514
PW		 33#include "cm1_44xx.h"
34#include "cm2_44xx.h"
35#include "prm44xx.h"
55d2cb08 36#include "prm-regbits-44xx.h"
ff2516fb 37#include "wd_timer.h"
55d2cb08
BC		 38
39/* Base offset for all OMAP4 interrupts external to MPUSS */
40#define OMAP44XX_IRQ_GIC_START 32
41
42/* Base offset for all OMAP4 dma requests */
43#define OMAP44XX_DMA_REQ_START 1
44
45/* Backward references (IPs with Bus Master capability) */
407a6888 46static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 47static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 48static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 49static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 50static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 51static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 52static struct omap_hwmod omap44xx_hsi_hwmod;
53static struct omap_hwmod omap44xx_ipu_hwmod;
54static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 55static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 56static struct omap_hwmod omap44xx_l3_instr_hwmod;
57static struct omap_hwmod omap44xx_l3_main_1_hwmod;
58static struct omap_hwmod omap44xx_l3_main_2_hwmod;
59static struct omap_hwmod omap44xx_l3_main_3_hwmod;
60static struct omap_hwmod omap44xx_l4_abe_hwmod;
61static struct omap_hwmod omap44xx_l4_cfg_hwmod;
62static struct omap_hwmod omap44xx_l4_per_hwmod;
63static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 64static struct omap_hwmod omap44xx_mmc1_hwmod;
65static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 66static struct omap_hwmod omap44xx_mpu_hwmod;
67static struct omap_hwmod omap44xx_mpu_private_hwmod;
5844c4ea 68static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
55d2cb08
BC		 69
70/*
71 * Interconnects omap_hwmod structures
72 * hwmods that compose the global OMAP interconnect
73 */
74
75/*
76 * 'dmm' class
77 * instance(s): dmm
78 */
79static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 80 .name = "dmm",
55d2cb08
BC		 81};
82
7e69ed97
BC		 83/* dmm */
84static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86 { .irq = -1 }
87};
88
55d2cb08
BC		 89/* l3_main_1 -> dmm */
90static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
91 .master = &omap44xx_l3_main_1_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
93 .clk = "l3_div_ck",
659fa822
BC		 94 .user = OCP_USER_SDMA,
95};
96
97static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
98 {
99 .pa_start = 0x4e000000,
100 .pa_end = 0x4e0007ff,
101 .flags = ADDR_TYPE_RT
102 },
78183f3f 103 { }
55d2cb08
BC		 104};
105
106/* mpu -> dmm */
107static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
108 .master = &omap44xx_mpu_hwmod,
109 .slave = &omap44xx_dmm_hwmod,
110 .clk = "l3_div_ck",
659fa822 111 .addr = omap44xx_dmm_addrs,
659fa822 112 .user = OCP_USER_MPU,
55d2cb08
BC		 113};
114
115/* dmm slave ports */
116static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
117 &omap44xx_l3_main_1__dmm,
118 &omap44xx_mpu__dmm,
119};
120
55d2cb08
BC		 121static struct omap_hwmod omap44xx_dmm_hwmod = {
122 .name = "dmm",
123 .class = &omap44xx_dmm_hwmod_class,
7e69ed97 124 .mpu_irqs = omap44xx_dmm_irqs,
55d2cb08
BC		 125 .slaves = omap44xx_dmm_slaves,
126 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
55d2cb08
BC		 127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
128};
129
130/*
131 * 'emif_fw' class
132 * instance(s): emif_fw
133 */
134static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 135 .name = "emif_fw",
55d2cb08
BC		 136};
137
7e69ed97 138/* emif_fw */
55d2cb08
BC		 139/* dmm -> emif_fw */
140static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
141 .master = &omap44xx_dmm_hwmod,
142 .slave = &omap44xx_emif_fw_hwmod,
143 .clk = "l3_div_ck",
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145};
146
659fa822
BC		 147static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
148 {
149 .pa_start = 0x4a20c000,
150 .pa_end = 0x4a20c0ff,
151 .flags = ADDR_TYPE_RT
152 },
78183f3f 153 { }
659fa822
BC		 154};
155
55d2cb08
BC		 156/* l4_cfg -> emif_fw */
157static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
158 .master = &omap44xx_l4_cfg_hwmod,
159 .slave = &omap44xx_emif_fw_hwmod,
160 .clk = "l4_div_ck",
659fa822 161 .addr = omap44xx_emif_fw_addrs,
659fa822 162 .user = OCP_USER_MPU,
55d2cb08
BC		 163};
164
165/* emif_fw slave ports */
166static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
167 &omap44xx_dmm__emif_fw,
168 &omap44xx_l4_cfg__emif_fw,
169};
170
171static struct omap_hwmod omap44xx_emif_fw_hwmod = {
172 .name = "emif_fw",
173 .class = &omap44xx_emif_fw_hwmod_class,
174 .slaves = omap44xx_emif_fw_slaves,
175 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
177};
178
179/*
180 * 'l3' class
181 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
182 */
183static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 184 .name = "l3",
55d2cb08
BC		 185};
186
7e69ed97 187/* l3_instr */
8f25bdc5
BC		 188/* iva -> l3_instr */
189static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
190 .master = &omap44xx_iva_hwmod,
191 .slave = &omap44xx_l3_instr_hwmod,
192 .clk = "l3_div_ck",
193 .user = OCP_USER_MPU | OCP_USER_SDMA,
194};
195
55d2cb08
BC		 196/* l3_main_3 -> l3_instr */
197static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
198 .master = &omap44xx_l3_main_3_hwmod,
199 .slave = &omap44xx_l3_instr_hwmod,
200 .clk = "l3_div_ck",
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202};
203
204/* l3_instr slave ports */
205static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 206 &omap44xx_iva__l3_instr,
55d2cb08
BC		 207 &omap44xx_l3_main_3__l3_instr,
208};
209
210static struct omap_hwmod omap44xx_l3_instr_hwmod = {
211 .name = "l3_instr",
212 .class = &omap44xx_l3_hwmod_class,
213 .slaves = omap44xx_l3_instr_slaves,
214 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216};
217
7e69ed97 218/* l3_main_1 */
9b4021be
BC		 219static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
220 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
221 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
222 { .irq = -1 }
223};
224
8f25bdc5
BC		 225/* dsp -> l3_main_1 */
226static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
227 .master = &omap44xx_dsp_hwmod,
228 .slave = &omap44xx_l3_main_1_hwmod,
229 .clk = "l3_div_ck",
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
d63bd74f
BC		 233/* dss -> l3_main_1 */
234static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
235 .master = &omap44xx_dss_hwmod,
236 .slave = &omap44xx_l3_main_1_hwmod,
237 .clk = "l3_div_ck",
238 .user = OCP_USER_MPU | OCP_USER_SDMA,
239};
240
55d2cb08
BC		 241/* l3_main_2 -> l3_main_1 */
242static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
243 .master = &omap44xx_l3_main_2_hwmod,
244 .slave = &omap44xx_l3_main_1_hwmod,
245 .clk = "l3_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247};
248
249/* l4_cfg -> l3_main_1 */
250static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
251 .master = &omap44xx_l4_cfg_hwmod,
252 .slave = &omap44xx_l3_main_1_hwmod,
253 .clk = "l4_div_ck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255};
256
407a6888
BC		 257/* mmc1 -> l3_main_1 */
258static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
259 .master = &omap44xx_mmc1_hwmod,
260 .slave = &omap44xx_l3_main_1_hwmod,
261 .clk = "l3_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
265/* mmc2 -> l3_main_1 */
266static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
267 .master = &omap44xx_mmc2_hwmod,
268 .slave = &omap44xx_l3_main_1_hwmod,
269 .clk = "l3_div_ck",
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
271};
272
c4645234 273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
9b4021be 277 .flags = ADDR_TYPE_RT
c4645234 278 },
78183f3f 279 { }
c4645234 280};
281
55d2cb08
BC		 282/* mpu -> l3_main_1 */
283static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
284 .master = &omap44xx_mpu_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
286 .clk = "l3_div_ck",
c4645234 287 .addr = omap44xx_l3_main_1_addrs,
9b4021be 288 .user = OCP_USER_MPU,
55d2cb08
BC		 289};
290
291/* l3_main_1 slave ports */
292static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 293 &omap44xx_dsp__l3_main_1,
d63bd74f 294 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 295 &omap44xx_l3_main_2__l3_main_1,
296 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 297 &omap44xx_mmc1__l3_main_1,
298 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 299 &omap44xx_mpu__l3_main_1,
300};
301
302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
303 .name = "l3_main_1",
304 .class = &omap44xx_l3_hwmod_class,
7e69ed97 305 .mpu_irqs = omap44xx_l3_main_1_irqs,
55d2cb08
BC		 306 .slaves = omap44xx_l3_main_1_slaves,
307 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
308 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
309};
310
7e69ed97 311/* l3_main_2 */
d7cf5f33
BC		 312/* dma_system -> l3_main_2 */
313static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
314 .master = &omap44xx_dma_system_hwmod,
315 .slave = &omap44xx_l3_main_2_hwmod,
316 .clk = "l3_div_ck",
317 .user = OCP_USER_MPU | OCP_USER_SDMA,
318};
319
407a6888
BC		 320/* hsi -> l3_main_2 */
321static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
322 .master = &omap44xx_hsi_hwmod,
323 .slave = &omap44xx_l3_main_2_hwmod,
324 .clk = "l3_div_ck",
325 .user = OCP_USER_MPU | OCP_USER_SDMA,
326};
327
328/* ipu -> l3_main_2 */
329static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
330 .master = &omap44xx_ipu_hwmod,
331 .slave = &omap44xx_l3_main_2_hwmod,
332 .clk = "l3_div_ck",
333 .user = OCP_USER_MPU | OCP_USER_SDMA,
334};
335
336/* iss -> l3_main_2 */
337static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
338 .master = &omap44xx_iss_hwmod,
339 .slave = &omap44xx_l3_main_2_hwmod,
340 .clk = "l3_div_ck",
341 .user = OCP_USER_MPU | OCP_USER_SDMA,
342};
343
8f25bdc5
BC		 344/* iva -> l3_main_2 */
345static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
346 .master = &omap44xx_iva_hwmod,
347 .slave = &omap44xx_l3_main_2_hwmod,
348 .clk = "l3_div_ck",
349 .user = OCP_USER_MPU | OCP_USER_SDMA,
350};
351
c4645234 352static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
353 {
354 .pa_start = 0x44800000,
355 .pa_end = 0x44801fff,
9b4021be 356 .flags = ADDR_TYPE_RT
c4645234 357 },
78183f3f 358 { }
c4645234 359};
360
55d2cb08
BC		 361/* l3_main_1 -> l3_main_2 */
362static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
363 .master = &omap44xx_l3_main_1_hwmod,
364 .slave = &omap44xx_l3_main_2_hwmod,
365 .clk = "l3_div_ck",
c4645234 366 .addr = omap44xx_l3_main_2_addrs,
9b4021be 367 .user = OCP_USER_MPU,
55d2cb08
BC		 368};
369
370/* l4_cfg -> l3_main_2 */
371static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
372 .master = &omap44xx_l4_cfg_hwmod,
373 .slave = &omap44xx_l3_main_2_hwmod,
374 .clk = "l4_div_ck",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
5844c4ea
BC		 378/* usb_otg_hs -> l3_main_2 */
379static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
380 .master = &omap44xx_usb_otg_hs_hwmod,
381 .slave = &omap44xx_l3_main_2_hwmod,
382 .clk = "l3_div_ck",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384};
385
55d2cb08
BC		 386/* l3_main_2 slave ports */
387static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 388 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 389 &omap44xx_hsi__l3_main_2,
390 &omap44xx_ipu__l3_main_2,
391 &omap44xx_iss__l3_main_2,
8f25bdc5 392 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 393 &omap44xx_l3_main_1__l3_main_2,
394 &omap44xx_l4_cfg__l3_main_2,
5844c4ea 395 &omap44xx_usb_otg_hs__l3_main_2,
55d2cb08
BC		 396};
397
398static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
399 .name = "l3_main_2",
400 .class = &omap44xx_l3_hwmod_class,
401 .slaves = omap44xx_l3_main_2_slaves,
402 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
403 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
404};
405
7e69ed97 406/* l3_main_3 */
c4645234 407static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
408 {
409 .pa_start = 0x45000000,
410 .pa_end = 0x45000fff,
9b4021be 411 .flags = ADDR_TYPE_RT
c4645234 412 },
78183f3f 413 { }
c4645234 414};
415
55d2cb08
BC		 416/* l3_main_1 -> l3_main_3 */
417static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
418 .master = &omap44xx_l3_main_1_hwmod,
419 .slave = &omap44xx_l3_main_3_hwmod,
420 .clk = "l3_div_ck",
c4645234 421 .addr = omap44xx_l3_main_3_addrs,
9b4021be 422 .user = OCP_USER_MPU,
55d2cb08
BC		 423};
424
425/* l3_main_2 -> l3_main_3 */
426static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
427 .master = &omap44xx_l3_main_2_hwmod,
428 .slave = &omap44xx_l3_main_3_hwmod,
429 .clk = "l3_div_ck",
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
433/* l4_cfg -> l3_main_3 */
434static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
435 .master = &omap44xx_l4_cfg_hwmod,
436 .slave = &omap44xx_l3_main_3_hwmod,
437 .clk = "l4_div_ck",
438 .user = OCP_USER_MPU | OCP_USER_SDMA,
439};
440
441/* l3_main_3 slave ports */
442static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
443 &omap44xx_l3_main_1__l3_main_3,
444 &omap44xx_l3_main_2__l3_main_3,
445 &omap44xx_l4_cfg__l3_main_3,
446};
447
448static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
449 .name = "l3_main_3",
450 .class = &omap44xx_l3_hwmod_class,
451 .slaves = omap44xx_l3_main_3_slaves,
452 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
454};
455
456/*
457 * 'l4' class
458 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
459 */
460static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 461 .name = "l4",
55d2cb08
BC		 462};
463
7e69ed97 464/* l4_abe */
407a6888
BC		 465/* aess -> l4_abe */
466static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
467 .master = &omap44xx_aess_hwmod,
468 .slave = &omap44xx_l4_abe_hwmod,
469 .clk = "ocp_abe_iclk",
470 .user = OCP_USER_MPU | OCP_USER_SDMA,
471};
472
8f25bdc5
BC		 473/* dsp -> l4_abe */
474static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
475 .master = &omap44xx_dsp_hwmod,
476 .slave = &omap44xx_l4_abe_hwmod,
477 .clk = "ocp_abe_iclk",
478 .user = OCP_USER_MPU | OCP_USER_SDMA,
479};
480
55d2cb08
BC		 481/* l3_main_1 -> l4_abe */
482static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
483 .master = &omap44xx_l3_main_1_hwmod,
484 .slave = &omap44xx_l4_abe_hwmod,
485 .clk = "l3_div_ck",
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* mpu -> l4_abe */
490static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
491 .master = &omap44xx_mpu_hwmod,
492 .slave = &omap44xx_l4_abe_hwmod,
493 .clk = "ocp_abe_iclk",
494 .user = OCP_USER_MPU | OCP_USER_SDMA,
495};
496
497/* l4_abe slave ports */
498static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 499 &omap44xx_aess__l4_abe,
8f25bdc5 500 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 501 &omap44xx_l3_main_1__l4_abe,
502 &omap44xx_mpu__l4_abe,
503};
504
505static struct omap_hwmod omap44xx_l4_abe_hwmod = {
506 .name = "l4_abe",
507 .class = &omap44xx_l4_hwmod_class,
508 .slaves = omap44xx_l4_abe_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
511};
512
7e69ed97 513/* l4_cfg */
55d2cb08
BC		 514/* l3_main_1 -> l4_cfg */
515static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
516 .master = &omap44xx_l3_main_1_hwmod,
517 .slave = &omap44xx_l4_cfg_hwmod,
518 .clk = "l3_div_ck",
519 .user = OCP_USER_MPU | OCP_USER_SDMA,
520};
521
522/* l4_cfg slave ports */
523static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
524 &omap44xx_l3_main_1__l4_cfg,
525};
526
527static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
528 .name = "l4_cfg",
529 .class = &omap44xx_l4_hwmod_class,
530 .slaves = omap44xx_l4_cfg_slaves,
531 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
533};
534
7e69ed97 535/* l4_per */
55d2cb08
BC		 536/* l3_main_2 -> l4_per */
537static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
538 .master = &omap44xx_l3_main_2_hwmod,
539 .slave = &omap44xx_l4_per_hwmod,
540 .clk = "l3_div_ck",
541 .user = OCP_USER_MPU | OCP_USER_SDMA,
542};
543
544/* l4_per slave ports */
545static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
546 &omap44xx_l3_main_2__l4_per,
547};
548
549static struct omap_hwmod omap44xx_l4_per_hwmod = {
550 .name = "l4_per",
551 .class = &omap44xx_l4_hwmod_class,
552 .slaves = omap44xx_l4_per_slaves,
553 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
555};
556
7e69ed97 557/* l4_wkup */
55d2cb08
BC		 558/* l4_cfg -> l4_wkup */
559static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
560 .master = &omap44xx_l4_cfg_hwmod,
561 .slave = &omap44xx_l4_wkup_hwmod,
562 .clk = "l4_div_ck",
563 .user = OCP_USER_MPU | OCP_USER_SDMA,
564};
565
566/* l4_wkup slave ports */
567static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
568 &omap44xx_l4_cfg__l4_wkup,
569};
570
571static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
572 .name = "l4_wkup",
573 .class = &omap44xx_l4_hwmod_class,
574 .slaves = omap44xx_l4_wkup_slaves,
575 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577};
578
f776471f 579/*
3b54baad
BC		 580 * 'mpu_bus' class
581 * instance(s): mpu_private
f776471f 582 */
3b54baad 583static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 584 .name = "mpu_bus",
3b54baad 585};
f776471f 586
7e69ed97 587/* mpu_private */
3b54baad
BC		 588/* mpu -> mpu_private */
589static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
590 .master = &omap44xx_mpu_hwmod,
591 .slave = &omap44xx_mpu_private_hwmod,
592 .clk = "l3_div_ck",
593 .user = OCP_USER_MPU | OCP_USER_SDMA,
594};
595
596/* mpu_private slave ports */
597static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
598 &omap44xx_mpu__mpu_private,
599};
600
601static struct omap_hwmod omap44xx_mpu_private_hwmod = {
602 .name = "mpu_private",
603 .class = &omap44xx_mpu_bus_hwmod_class,
604 .slaves = omap44xx_mpu_private_slaves,
605 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
606 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
607};
608
609/*
610 * Modules omap_hwmod structures
611 *
612 * The following IPs are excluded for the moment because:
613 * - They do not need an explicit SW control using omap_hwmod API.
614 * - They still need to be validated with the driver
615 * properly adapted to omap_hwmod / omap_device
616 *
3b54baad
BC		 617 * c2c
618 * c2c_target_fw
619 * cm_core
620 * cm_core_aon
3b54baad
BC		 621 * ctrl_module_core
622 * ctrl_module_pad_core
623 * ctrl_module_pad_wkup
624 * ctrl_module_wkup
625 * debugss
3b54baad
BC		 626 * efuse_ctrl_cust
627 * efuse_ctrl_std
628 * elm
629 * emif1
630 * emif2
631 * fdif
632 * gpmc
633 * gpu
634 * hdq1w
00fe610b
BC		 635 * mcasp
636 * mpu_c0
637 * mpu_c1
3b54baad
BC		 638 * ocmc_ram
639 * ocp2scp_usb_phy
640 * ocp_wp_noc
3b54baad
BC		 641 * prcm_mpu
642 * prm
643 * scrm
644 * sl2if
645 * slimbus1
646 * slimbus2
3b54baad
BC		 647 * usb_host_fs
648 * usb_host_hs
3b54baad
BC		 649 * usb_phy_cm
650 * usb_tll_hs
651 * usim
652 */
653
407a6888
BC		 654/*
655 * 'aess' class
656 * audio engine sub system
657 */
658
659static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
660 .rev_offs = 0x0000,
661 .sysc_offs = 0x0010,
662 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
663 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
c614ebf6
BC		 664 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
665 MSTANDBY_SMART_WKUP),
407a6888
BC		 666 .sysc_fields = &omap_hwmod_sysc_type2,
667};
668
669static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
670 .name = "aess",
671 .sysc = &omap44xx_aess_sysc,
672};
673
674/* aess */
675static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
676 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
212738a4 677 { .irq = -1 }
407a6888
BC		 678};
679
680static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
681 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
682 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
683 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
684 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
685 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
686 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
687 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
688 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
bc614958 689 { .dma_req = -1 }
407a6888
BC		 690};
691
692/* aess master ports */
693static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
694 &omap44xx_aess__l4_abe,
695};
696
697static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
698 {
699 .pa_start = 0x401f1000,
700 .pa_end = 0x401f13ff,
701 .flags = ADDR_TYPE_RT
702 },
78183f3f 703 { }
407a6888
BC		 704};
705
706/* l4_abe -> aess */
707static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
708 .master = &omap44xx_l4_abe_hwmod,
709 .slave = &omap44xx_aess_hwmod,
710 .clk = "ocp_abe_iclk",
711 .addr = omap44xx_aess_addrs,
407a6888
BC		 712 .user = OCP_USER_MPU,
713};
714
715static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
716 {
717 .pa_start = 0x490f1000,
718 .pa_end = 0x490f13ff,
719 .flags = ADDR_TYPE_RT
720 },
78183f3f 721 { }
407a6888
BC		 722};
723
724/* l4_abe -> aess (dma) */
725static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
726 .master = &omap44xx_l4_abe_hwmod,
727 .slave = &omap44xx_aess_hwmod,
728 .clk = "ocp_abe_iclk",
729 .addr = omap44xx_aess_dma_addrs,
407a6888
BC		 730 .user = OCP_USER_SDMA,
731};
732
733/* aess slave ports */
734static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
735 &omap44xx_l4_abe__aess,
736 &omap44xx_l4_abe__aess_dma,
737};
738
739static struct omap_hwmod omap44xx_aess_hwmod = {
740 .name = "aess",
741 .class = &omap44xx_aess_hwmod_class,
742 .mpu_irqs = omap44xx_aess_irqs,
407a6888 743 .sdma_reqs = omap44xx_aess_sdma_reqs,
407a6888 744 .main_clk = "aess_fck",
00fe610b 745 .prcm = {
407a6888
BC		 746 .omap4 = {
747 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
748 },
749 },
750 .slaves = omap44xx_aess_slaves,
751 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
752 .masters = omap44xx_aess_masters,
753 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
755};
756
757/*
758 * 'bandgap' class
759 * bangap reference for ldo regulators
760 */
761
762static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
763 .name = "bandgap",
764};
765
766/* bandgap */
767static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
768 { .role = "fclk", .clk = "bandgap_fclk" },
769};
770
771static struct omap_hwmod omap44xx_bandgap_hwmod = {
772 .name = "bandgap",
773 .class = &omap44xx_bandgap_hwmod_class,
00fe610b 774 .prcm = {
407a6888
BC		 775 .omap4 = {
776 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
777 },
778 },
779 .opt_clks = bandgap_opt_clks,
780 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
781 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
782};
783
784/*
785 * 'counter' class
786 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
787 */
788
789static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
790 .rev_offs = 0x0000,
791 .sysc_offs = 0x0004,
792 .sysc_flags = SYSC_HAS_SIDLEMODE,
793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
794 SIDLE_SMART_WKUP),
795 .sysc_fields = &omap_hwmod_sysc_type1,
796};
797
798static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
799 .name = "counter",
800 .sysc = &omap44xx_counter_sysc,
801};
802
803/* counter_32k */
804static struct omap_hwmod omap44xx_counter_32k_hwmod;
805static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
806 {
807 .pa_start = 0x4a304000,
808 .pa_end = 0x4a30401f,
809 .flags = ADDR_TYPE_RT
810 },
78183f3f 811 { }
407a6888
BC		 812};
813
814/* l4_wkup -> counter_32k */
815static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
816 .master = &omap44xx_l4_wkup_hwmod,
817 .slave = &omap44xx_counter_32k_hwmod,
818 .clk = "l4_wkup_clk_mux_ck",
819 .addr = omap44xx_counter_32k_addrs,
407a6888
BC		 820 .user = OCP_USER_MPU | OCP_USER_SDMA,
821};
822
823/* counter_32k slave ports */
824static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
825 &omap44xx_l4_wkup__counter_32k,
826};
827
828static struct omap_hwmod omap44xx_counter_32k_hwmod = {
829 .name = "counter_32k",
830 .class = &omap44xx_counter_hwmod_class,
831 .flags = HWMOD_SWSUP_SIDLE,
832 .main_clk = "sys_32k_ck",
00fe610b 833 .prcm = {
407a6888
BC		 834 .omap4 = {
835 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
836 },
837 },
838 .slaves = omap44xx_counter_32k_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
840 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
841};
842
d7cf5f33
BC		 843/*
844 * 'dma' class
845 * dma controller for data exchange between memory to memory (i.e. internal or
846 * external memory) and gp peripherals to memory or memory to gp peripherals
847 */
848
849static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
850 .rev_offs = 0x0000,
851 .sysc_offs = 0x002c,
852 .syss_offs = 0x0028,
853 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
854 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
855 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
856 SYSS_HAS_RESET_STATUS),
857 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
858 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
859 .sysc_fields = &omap_hwmod_sysc_type1,
860};
861
862static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
863 .name = "dma",
864 .sysc = &omap44xx_dma_sysc,
865};
866
867/* dma dev_attr */
868static struct omap_dma_dev_attr dma_dev_attr = {
869 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
870 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
871 .lch_count = 32,
872};
873
874/* dma_system */
875static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
876 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
877 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
878 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
879 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
212738a4 880 { .irq = -1 }
d7cf5f33
BC		 881};
882
883/* dma_system master ports */
884static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
885 &omap44xx_dma_system__l3_main_2,
886};
887
888static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
889 {
890 .pa_start = 0x4a056000,
1286eeb2 891 .pa_end = 0x4a056fff,
d7cf5f33
BC		 892 .flags = ADDR_TYPE_RT
893 },
78183f3f 894 { }
d7cf5f33
BC		 895};
896
897/* l4_cfg -> dma_system */
898static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
899 .master = &omap44xx_l4_cfg_hwmod,
900 .slave = &omap44xx_dma_system_hwmod,
901 .clk = "l4_div_ck",
902 .addr = omap44xx_dma_system_addrs,
d7cf5f33
BC		 903 .user = OCP_USER_MPU | OCP_USER_SDMA,
904};
905
906/* dma_system slave ports */
907static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
908 &omap44xx_l4_cfg__dma_system,
909};
910
911static struct omap_hwmod omap44xx_dma_system_hwmod = {
912 .name = "dma_system",
913 .class = &omap44xx_dma_hwmod_class,
914 .mpu_irqs = omap44xx_dma_system_irqs,
d7cf5f33
BC		 915 .main_clk = "l3_div_ck",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
919 },
920 },
921 .dev_attr = &dma_dev_attr,
922 .slaves = omap44xx_dma_system_slaves,
923 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
924 .masters = omap44xx_dma_system_masters,
925 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
926 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
927};
928
8ca476da
BC		 929/*
930 * 'dmic' class
931 * digital microphone controller
932 */
933
934static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
935 .rev_offs = 0x0000,
936 .sysc_offs = 0x0010,
937 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
938 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
939 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
940 SIDLE_SMART_WKUP),
941 .sysc_fields = &omap_hwmod_sysc_type2,
942};
943
944static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
945 .name = "dmic",
946 .sysc = &omap44xx_dmic_sysc,
947};
948
949/* dmic */
950static struct omap_hwmod omap44xx_dmic_hwmod;
951static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
952 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
212738a4 953 { .irq = -1 }
8ca476da
BC		 954};
955
956static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
957 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
bc614958 958 { .dma_req = -1 }
8ca476da
BC		 959};
960
961static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
962 {
963 .pa_start = 0x4012e000,
964 .pa_end = 0x4012e07f,
965 .flags = ADDR_TYPE_RT
966 },
78183f3f 967 { }
8ca476da
BC		 968};
969
970/* l4_abe -> dmic */
971static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
972 .master = &omap44xx_l4_abe_hwmod,
973 .slave = &omap44xx_dmic_hwmod,
974 .clk = "ocp_abe_iclk",
975 .addr = omap44xx_dmic_addrs,
8ca476da
BC		 976 .user = OCP_USER_MPU,
977};
978
979static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
980 {
981 .pa_start = 0x4902e000,
982 .pa_end = 0x4902e07f,
983 .flags = ADDR_TYPE_RT
984 },
78183f3f 985 { }
8ca476da
BC		 986};
987
988/* l4_abe -> dmic (dma) */
989static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
990 .master = &omap44xx_l4_abe_hwmod,
991 .slave = &omap44xx_dmic_hwmod,
992 .clk = "ocp_abe_iclk",
993 .addr = omap44xx_dmic_dma_addrs,
8ca476da
BC		 994 .user = OCP_USER_SDMA,
995};
996
997/* dmic slave ports */
998static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
999 &omap44xx_l4_abe__dmic,
1000 &omap44xx_l4_abe__dmic_dma,
1001};
1002
1003static struct omap_hwmod omap44xx_dmic_hwmod = {
1004 .name = "dmic",
1005 .class = &omap44xx_dmic_hwmod_class,
1006 .mpu_irqs = omap44xx_dmic_irqs,
8ca476da 1007 .sdma_reqs = omap44xx_dmic_sdma_reqs,
8ca476da 1008 .main_clk = "dmic_fck",
00fe610b 1009 .prcm = {
8ca476da
BC		 1010 .omap4 = {
1011 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1012 },
1013 },
1014 .slaves = omap44xx_dmic_slaves,
1015 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1017};
1018
8f25bdc5
BC		 1019/*
1020 * 'dsp' class
1021 * dsp sub-system
1022 */
1023
1024static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 1025 .name = "dsp",
8f25bdc5
BC		 1026};
1027
1028/* dsp */
1029static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1030 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
212738a4 1031 { .irq = -1 }
8f25bdc5
BC		 1032};
1033
1034static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1035 { .name = "mmu_cache", .rst_shift = 1 },
1036};
1037
1038static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1039 { .name = "dsp", .rst_shift = 0 },
1040};
1041
1042/* dsp -> iva */
1043static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1044 .master = &omap44xx_dsp_hwmod,
1045 .slave = &omap44xx_iva_hwmod,
1046 .clk = "dpll_iva_m5x2_ck",
1047};
1048
1049/* dsp master ports */
1050static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1051 &omap44xx_dsp__l3_main_1,
1052 &omap44xx_dsp__l4_abe,
1053 &omap44xx_dsp__iva,
1054};
1055
1056/* l4_cfg -> dsp */
1057static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1058 .master = &omap44xx_l4_cfg_hwmod,
1059 .slave = &omap44xx_dsp_hwmod,
1060 .clk = "l4_div_ck",
1061 .user = OCP_USER_MPU | OCP_USER_SDMA,
1062};
1063
1064/* dsp slave ports */
1065static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1066 &omap44xx_l4_cfg__dsp,
1067};
1068
1069/* Pseudo hwmod for reset control purpose only */
1070static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1071 .name = "dsp_c0",
1072 .class = &omap44xx_dsp_hwmod_class,
1073 .flags = HWMOD_INIT_NO_RESET,
1074 .rst_lines = omap44xx_dsp_c0_resets,
1075 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1076 .prcm = {
1077 .omap4 = {
1078 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1079 },
1080 },
1081 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1082};
1083
1084static struct omap_hwmod omap44xx_dsp_hwmod = {
1085 .name = "dsp",
1086 .class = &omap44xx_dsp_hwmod_class,
1087 .mpu_irqs = omap44xx_dsp_irqs,
8f25bdc5
BC		 1088 .rst_lines = omap44xx_dsp_resets,
1089 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1090 .main_clk = "dsp_fck",
1091 .prcm = {
1092 .omap4 = {
1093 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1094 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1095 },
1096 },
1097 .slaves = omap44xx_dsp_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1099 .masters = omap44xx_dsp_masters,
1100 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1102};
1103
d63bd74f
BC		 1104/*
1105 * 'dss' class
1106 * display sub-system
1107 */
1108
1109static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1110 .rev_offs = 0x0000,
1111 .syss_offs = 0x0014,
1112 .sysc_flags = SYSS_HAS_RESET_STATUS,
1113};
1114
1115static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1116 .name = "dss",
1117 .sysc = &omap44xx_dss_sysc,
1118};
1119
1120/* dss */
1121/* dss master ports */
1122static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1123 &omap44xx_dss__l3_main_1,
1124};
1125
1126static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1127 {
1128 .pa_start = 0x58000000,
1129 .pa_end = 0x5800007f,
1130 .flags = ADDR_TYPE_RT
1131 },
78183f3f 1132 { }
d63bd74f
BC		 1133};
1134
1135/* l3_main_2 -> dss */
1136static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1137 .master = &omap44xx_l3_main_2_hwmod,
1138 .slave = &omap44xx_dss_hwmod,
da7cdfac 1139 .clk = "dss_fck",
d63bd74f 1140 .addr = omap44xx_dss_dma_addrs,
d63bd74f
BC		 1141 .user = OCP_USER_SDMA,
1142};
1143
1144static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1145 {
1146 .pa_start = 0x48040000,
1147 .pa_end = 0x4804007f,
1148 .flags = ADDR_TYPE_RT
1149 },
78183f3f 1150 { }
d63bd74f
BC		 1151};
1152
1153/* l4_per -> dss */
1154static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1155 .master = &omap44xx_l4_per_hwmod,
1156 .slave = &omap44xx_dss_hwmod,
1157 .clk = "l4_div_ck",
1158 .addr = omap44xx_dss_addrs,
d63bd74f
BC		 1159 .user = OCP_USER_MPU,
1160};
1161
1162/* dss slave ports */
1163static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1164 &omap44xx_l3_main_2__dss,
1165 &omap44xx_l4_per__dss,
1166};
1167
1168static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1169 { .role = "sys_clk", .clk = "dss_sys_clk" },
1170 { .role = "tv_clk", .clk = "dss_tv_clk" },
1171 { .role = "dss_clk", .clk = "dss_dss_clk" },
1172 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1173};
1174
1175static struct omap_hwmod omap44xx_dss_hwmod = {
1176 .name = "dss_core",
1177 .class = &omap44xx_dss_hwmod_class,
da7cdfac 1178 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1179 .prcm = {
1180 .omap4 = {
1181 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1182 },
1183 },
1184 .opt_clks = dss_opt_clks,
1185 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1186 .slaves = omap44xx_dss_slaves,
1187 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1188 .masters = omap44xx_dss_masters,
1189 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191};
1192
1193/*
1194 * 'dispc' class
1195 * display controller
1196 */
1197
1198static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1199 .rev_offs = 0x0000,
1200 .sysc_offs = 0x0010,
1201 .syss_offs = 0x0014,
1202 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1203 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1205 SYSS_HAS_RESET_STATUS),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1208 .sysc_fields = &omap_hwmod_sysc_type1,
1209};
1210
1211static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1212 .name = "dispc",
1213 .sysc = &omap44xx_dispc_sysc,
1214};
1215
1216/* dss_dispc */
1217static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1218static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1219 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
212738a4 1220 { .irq = -1 }
d63bd74f
BC		 1221};
1222
1223static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1224 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
bc614958 1225 { .dma_req = -1 }
d63bd74f
BC		 1226};
1227
1228static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1229 {
1230 .pa_start = 0x58001000,
1231 .pa_end = 0x58001fff,
1232 .flags = ADDR_TYPE_RT
1233 },
78183f3f 1234 { }
d63bd74f
BC		 1235};
1236
1237/* l3_main_2 -> dss_dispc */
1238static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1239 .master = &omap44xx_l3_main_2_hwmod,
1240 .slave = &omap44xx_dss_dispc_hwmod,
da7cdfac 1241 .clk = "dss_fck",
d63bd74f 1242 .addr = omap44xx_dss_dispc_dma_addrs,
d63bd74f
BC		 1243 .user = OCP_USER_SDMA,
1244};
1245
1246static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1247 {
1248 .pa_start = 0x48041000,
1249 .pa_end = 0x48041fff,
1250 .flags = ADDR_TYPE_RT
1251 },
78183f3f 1252 { }
d63bd74f
BC		 1253};
1254
1255/* l4_per -> dss_dispc */
1256static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1257 .master = &omap44xx_l4_per_hwmod,
1258 .slave = &omap44xx_dss_dispc_hwmod,
1259 .clk = "l4_div_ck",
1260 .addr = omap44xx_dss_dispc_addrs,
d63bd74f
BC		 1261 .user = OCP_USER_MPU,
1262};
1263
1264/* dss_dispc slave ports */
1265static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1266 &omap44xx_l3_main_2__dss_dispc,
1267 &omap44xx_l4_per__dss_dispc,
1268};
1269
3a23aafc
TV		 1270static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1271 { .role = "sys_clk", .clk = "dss_sys_clk" },
1272 { .role = "tv_clk", .clk = "dss_tv_clk" },
1273 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1274};
1275
d63bd74f
BC		 1276static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1277 .name = "dss_dispc",
1278 .class = &omap44xx_dispc_hwmod_class,
3a23aafc 1279 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
d63bd74f 1280 .mpu_irqs = omap44xx_dss_dispc_irqs,
d63bd74f 1281 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
da7cdfac 1282 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1283 .prcm = {
1284 .omap4 = {
1285 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1286 },
1287 },
3a23aafc
TV		 1288 .opt_clks = dss_dispc_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
d63bd74f
BC		 1290 .slaves = omap44xx_dss_dispc_slaves,
1291 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1292 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1293};
1294
1295/*
1296 * 'dsi' class
1297 * display serial interface controller
1298 */
1299
1300static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1301 .rev_offs = 0x0000,
1302 .sysc_offs = 0x0010,
1303 .syss_offs = 0x0014,
1304 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1305 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1306 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308 .sysc_fields = &omap_hwmod_sysc_type1,
1309};
1310
1311static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1312 .name = "dsi",
1313 .sysc = &omap44xx_dsi_sysc,
1314};
1315
1316/* dss_dsi1 */
1317static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1318static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1319 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
212738a4 1320 { .irq = -1 }
d63bd74f
BC		 1321};
1322
1323static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1324 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
bc614958 1325 { .dma_req = -1 }
d63bd74f
BC		 1326};
1327
1328static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1329 {
1330 .pa_start = 0x58004000,
1331 .pa_end = 0x580041ff,
1332 .flags = ADDR_TYPE_RT
1333 },
78183f3f 1334 { }
d63bd74f
BC		 1335};
1336
1337/* l3_main_2 -> dss_dsi1 */
1338static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1339 .master = &omap44xx_l3_main_2_hwmod,
1340 .slave = &omap44xx_dss_dsi1_hwmod,
da7cdfac 1341 .clk = "dss_fck",
d63bd74f 1342 .addr = omap44xx_dss_dsi1_dma_addrs,
d63bd74f
BC		 1343 .user = OCP_USER_SDMA,
1344};
1345
1346static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1347 {
1348 .pa_start = 0x48044000,
1349 .pa_end = 0x480441ff,
1350 .flags = ADDR_TYPE_RT
1351 },
78183f3f 1352 { }
d63bd74f
BC		 1353};
1354
1355/* l4_per -> dss_dsi1 */
1356static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1357 .master = &omap44xx_l4_per_hwmod,
1358 .slave = &omap44xx_dss_dsi1_hwmod,
1359 .clk = "l4_div_ck",
1360 .addr = omap44xx_dss_dsi1_addrs,
d63bd74f
BC		 1361 .user = OCP_USER_MPU,
1362};
1363
1364/* dss_dsi1 slave ports */
1365static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1366 &omap44xx_l3_main_2__dss_dsi1,
1367 &omap44xx_l4_per__dss_dsi1,
1368};
1369
3a23aafc
TV		 1370static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1371 { .role = "sys_clk", .clk = "dss_sys_clk" },
1372};
1373
d63bd74f
BC		 1374static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1375 .name = "dss_dsi1",
1376 .class = &omap44xx_dsi_hwmod_class,
1377 .mpu_irqs = omap44xx_dss_dsi1_irqs,
d63bd74f 1378 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
da7cdfac 1379 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1383 },
1384 },
3a23aafc
TV		 1385 .opt_clks = dss_dsi1_opt_clks,
1386 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
d63bd74f
BC		 1387 .slaves = omap44xx_dss_dsi1_slaves,
1388 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1390};
1391
1392/* dss_dsi2 */
1393static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1394static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1395 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
212738a4 1396 { .irq = -1 }
d63bd74f
BC		 1397};
1398
1399static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1400 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
bc614958 1401 { .dma_req = -1 }
d63bd74f
BC		 1402};
1403
1404static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1405 {
1406 .pa_start = 0x58005000,
1407 .pa_end = 0x580051ff,
1408 .flags = ADDR_TYPE_RT
1409 },
78183f3f 1410 { }
d63bd74f
BC		 1411};
1412
1413/* l3_main_2 -> dss_dsi2 */
1414static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1415 .master = &omap44xx_l3_main_2_hwmod,
1416 .slave = &omap44xx_dss_dsi2_hwmod,
da7cdfac 1417 .clk = "dss_fck",
d63bd74f 1418 .addr = omap44xx_dss_dsi2_dma_addrs,
d63bd74f
BC		 1419 .user = OCP_USER_SDMA,
1420};
1421
1422static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1423 {
1424 .pa_start = 0x48045000,
1425 .pa_end = 0x480451ff,
1426 .flags = ADDR_TYPE_RT
1427 },
78183f3f 1428 { }
d63bd74f
BC		 1429};
1430
1431/* l4_per -> dss_dsi2 */
1432static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1433 .master = &omap44xx_l4_per_hwmod,
1434 .slave = &omap44xx_dss_dsi2_hwmod,
1435 .clk = "l4_div_ck",
1436 .addr = omap44xx_dss_dsi2_addrs,
d63bd74f
BC		 1437 .user = OCP_USER_MPU,
1438};
1439
1440/* dss_dsi2 slave ports */
1441static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1442 &omap44xx_l3_main_2__dss_dsi2,
1443 &omap44xx_l4_per__dss_dsi2,
1444};
1445
3a23aafc
TV		 1446static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1447 { .role = "sys_clk", .clk = "dss_sys_clk" },
1448};
1449
d63bd74f
BC		 1450static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1451 .name = "dss_dsi2",
1452 .class = &omap44xx_dsi_hwmod_class,
1453 .mpu_irqs = omap44xx_dss_dsi2_irqs,
d63bd74f 1454 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
da7cdfac 1455 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1456 .prcm = {
1457 .omap4 = {
1458 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1459 },
1460 },
3a23aafc
TV		 1461 .opt_clks = dss_dsi2_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
d63bd74f
BC		 1463 .slaves = omap44xx_dss_dsi2_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1465 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1466};
1467
1468/*
1469 * 'hdmi' class
1470 * hdmi controller
1471 */
1472
1473static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1474 .rev_offs = 0x0000,
1475 .sysc_offs = 0x0010,
1476 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1477 SYSC_HAS_SOFTRESET),
1478 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1479 SIDLE_SMART_WKUP),
1480 .sysc_fields = &omap_hwmod_sysc_type2,
1481};
1482
1483static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1484 .name = "hdmi",
1485 .sysc = &omap44xx_hdmi_sysc,
1486};
1487
1488/* dss_hdmi */
1489static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1490static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1491 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
212738a4 1492 { .irq = -1 }
d63bd74f
BC		 1493};
1494
1495static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1496 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
bc614958 1497 { .dma_req = -1 }
d63bd74f
BC		 1498};
1499
1500static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1501 {
1502 .pa_start = 0x58006000,
1503 .pa_end = 0x58006fff,
1504 .flags = ADDR_TYPE_RT
1505 },
78183f3f 1506 { }
d63bd74f
BC		 1507};
1508
1509/* l3_main_2 -> dss_hdmi */
1510static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1511 .master = &omap44xx_l3_main_2_hwmod,
1512 .slave = &omap44xx_dss_hdmi_hwmod,
da7cdfac 1513 .clk = "dss_fck",
d63bd74f 1514 .addr = omap44xx_dss_hdmi_dma_addrs,
d63bd74f
BC		 1515 .user = OCP_USER_SDMA,
1516};
1517
1518static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1519 {
1520 .pa_start = 0x48046000,
1521 .pa_end = 0x48046fff,
1522 .flags = ADDR_TYPE_RT
1523 },
78183f3f 1524 { }
d63bd74f
BC		 1525};
1526
1527/* l4_per -> dss_hdmi */
1528static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1529 .master = &omap44xx_l4_per_hwmod,
1530 .slave = &omap44xx_dss_hdmi_hwmod,
1531 .clk = "l4_div_ck",
1532 .addr = omap44xx_dss_hdmi_addrs,
d63bd74f
BC		 1533 .user = OCP_USER_MPU,
1534};
1535
1536/* dss_hdmi slave ports */
1537static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1538 &omap44xx_l3_main_2__dss_hdmi,
1539 &omap44xx_l4_per__dss_hdmi,
1540};
1541
3a23aafc
TV		 1542static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1543 { .role = "sys_clk", .clk = "dss_sys_clk" },
1544};
1545
d63bd74f
BC		 1546static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1547 .name = "dss_hdmi",
1548 .class = &omap44xx_hdmi_hwmod_class,
1549 .mpu_irqs = omap44xx_dss_hdmi_irqs,
d63bd74f 1550 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
da7cdfac 1551 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1552 .prcm = {
1553 .omap4 = {
1554 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1555 },
1556 },
3a23aafc
TV		 1557 .opt_clks = dss_hdmi_opt_clks,
1558 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
d63bd74f
BC		 1559 .slaves = omap44xx_dss_hdmi_slaves,
1560 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1562};
1563
1564/*
1565 * 'rfbi' class
1566 * remote frame buffer interface
1567 */
1568
1569static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1570 .rev_offs = 0x0000,
1571 .sysc_offs = 0x0010,
1572 .syss_offs = 0x0014,
1573 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1574 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1575 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1576 .sysc_fields = &omap_hwmod_sysc_type1,
1577};
1578
1579static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1580 .name = "rfbi",
1581 .sysc = &omap44xx_rfbi_sysc,
1582};
1583
1584/* dss_rfbi */
1585static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1586static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1587 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
bc614958 1588 { .dma_req = -1 }
d63bd74f
BC		 1589};
1590
1591static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1592 {
1593 .pa_start = 0x58002000,
1594 .pa_end = 0x580020ff,
1595 .flags = ADDR_TYPE_RT
1596 },
78183f3f 1597 { }
d63bd74f
BC		 1598};
1599
1600/* l3_main_2 -> dss_rfbi */
1601static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1602 .master = &omap44xx_l3_main_2_hwmod,
1603 .slave = &omap44xx_dss_rfbi_hwmod,
da7cdfac 1604 .clk = "dss_fck",
d63bd74f 1605 .addr = omap44xx_dss_rfbi_dma_addrs,
d63bd74f
BC		 1606 .user = OCP_USER_SDMA,
1607};
1608
1609static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1610 {
1611 .pa_start = 0x48042000,
1612 .pa_end = 0x480420ff,
1613 .flags = ADDR_TYPE_RT
1614 },
78183f3f 1615 { }
d63bd74f
BC		 1616};
1617
1618/* l4_per -> dss_rfbi */
1619static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1620 .master = &omap44xx_l4_per_hwmod,
1621 .slave = &omap44xx_dss_rfbi_hwmod,
1622 .clk = "l4_div_ck",
1623 .addr = omap44xx_dss_rfbi_addrs,
d63bd74f
BC		 1624 .user = OCP_USER_MPU,
1625};
1626
1627/* dss_rfbi slave ports */
1628static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1629 &omap44xx_l3_main_2__dss_rfbi,
1630 &omap44xx_l4_per__dss_rfbi,
1631};
1632
3a23aafc
TV		 1633static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1634 { .role = "ick", .clk = "dss_fck" },
1635};
1636
d63bd74f
BC		 1637static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1638 .name = "dss_rfbi",
1639 .class = &omap44xx_rfbi_hwmod_class,
1640 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
da7cdfac 1641 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1645 },
1646 },
3a23aafc
TV		 1647 .opt_clks = dss_rfbi_opt_clks,
1648 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
d63bd74f
BC		 1649 .slaves = omap44xx_dss_rfbi_slaves,
1650 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1651 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1652};
1653
1654/*
1655 * 'venc' class
1656 * video encoder
1657 */
1658
1659static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1660 .name = "venc",
1661};
1662
1663/* dss_venc */
1664static struct omap_hwmod omap44xx_dss_venc_hwmod;
1665static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1666 {
1667 .pa_start = 0x58003000,
1668 .pa_end = 0x580030ff,
1669 .flags = ADDR_TYPE_RT
1670 },
78183f3f 1671 { }
d63bd74f
BC		 1672};
1673
1674/* l3_main_2 -> dss_venc */
1675static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1676 .master = &omap44xx_l3_main_2_hwmod,
1677 .slave = &omap44xx_dss_venc_hwmod,
da7cdfac 1678 .clk = "dss_fck",
d63bd74f 1679 .addr = omap44xx_dss_venc_dma_addrs,
d63bd74f
BC		 1680 .user = OCP_USER_SDMA,
1681};
1682
1683static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1684 {
1685 .pa_start = 0x48043000,
1686 .pa_end = 0x480430ff,
1687 .flags = ADDR_TYPE_RT
1688 },
78183f3f 1689 { }
d63bd74f
BC		 1690};
1691
1692/* l4_per -> dss_venc */
1693static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1694 .master = &omap44xx_l4_per_hwmod,
1695 .slave = &omap44xx_dss_venc_hwmod,
1696 .clk = "l4_div_ck",
1697 .addr = omap44xx_dss_venc_addrs,
d63bd74f
BC		 1698 .user = OCP_USER_MPU,
1699};
1700
1701/* dss_venc slave ports */
1702static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1703 &omap44xx_l3_main_2__dss_venc,
1704 &omap44xx_l4_per__dss_venc,
1705};
1706
1707static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1708 .name = "dss_venc",
1709 .class = &omap44xx_venc_hwmod_class,
da7cdfac 1710 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1711 .prcm = {
1712 .omap4 = {
1713 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1714 },
1715 },
1716 .slaves = omap44xx_dss_venc_slaves,
1717 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1718 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1719};
1720
3b54baad
BC		 1721/*
1722 * 'gpio' class
1723 * general purpose io module
1724 */
1725
1726static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1727 .rev_offs = 0x0000,
f776471f 1728 .sysc_offs = 0x0010,
3b54baad 1729 .syss_offs = 0x0114,
0cfe8751
BC		 1730 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1731 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1732 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1734 SIDLE_SMART_WKUP),
f776471f
BC		 1735 .sysc_fields = &omap_hwmod_sysc_type1,
1736};
1737
3b54baad 1738static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1739 .name = "gpio",
1740 .sysc = &omap44xx_gpio_sysc,
1741 .rev = 2,
f776471f
BC		 1742};
1743
3b54baad
BC		 1744/* gpio dev_attr */
1745static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1746 .bank_width = 32,
1747 .dbck_flag = true,
f776471f
BC		 1748};
1749
3b54baad
BC		 1750/* gpio1 */
1751static struct omap_hwmod omap44xx_gpio1_hwmod;
1752static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1753 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
212738a4 1754 { .irq = -1 }
f776471f
BC		 1755};
1756
3b54baad 1757static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1758 {
3b54baad
BC		 1759 .pa_start = 0x4a310000,
1760 .pa_end = 0x4a3101ff,
f776471f
BC		 1761 .flags = ADDR_TYPE_RT
1762 },
78183f3f 1763 { }
f776471f
BC		 1764};
1765
3b54baad
BC		 1766/* l4_wkup -> gpio1 */
1767static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1768 .master = &omap44xx_l4_wkup_hwmod,
1769 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1770 .clk = "l4_wkup_clk_mux_ck",
3b54baad 1771 .addr = omap44xx_gpio1_addrs,
f776471f
BC		 1772 .user = OCP_USER_MPU | OCP_USER_SDMA,
1773};
1774
3b54baad
BC		 1775/* gpio1 slave ports */
1776static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1777 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1778};
1779
3b54baad 1780static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1781 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1782};
1783
1784static struct omap_hwmod omap44xx_gpio1_hwmod = {
1785 .name = "gpio1",
1786 .class = &omap44xx_gpio_hwmod_class,
1787 .mpu_irqs = omap44xx_gpio1_irqs,
3b54baad 1788 .main_clk = "gpio1_ick",
f776471f
BC		 1789 .prcm = {
1790 .omap4 = {
3b54baad 1791 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1792 },
1793 },
3b54baad
BC		 1794 .opt_clks = gpio1_opt_clks,
1795 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1796 .dev_attr = &gpio_dev_attr,
1797 .slaves = omap44xx_gpio1_slaves,
1798 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1799 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1800};
1801
3b54baad
BC		 1802/* gpio2 */
1803static struct omap_hwmod omap44xx_gpio2_hwmod;
1804static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1805 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
212738a4 1806 { .irq = -1 }
f776471f
BC		 1807};
1808
3b54baad 1809static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1810 {
3b54baad
BC		 1811 .pa_start = 0x48055000,
1812 .pa_end = 0x480551ff,
f776471f
BC		 1813 .flags = ADDR_TYPE_RT
1814 },
78183f3f 1815 { }
f776471f
BC		 1816};
1817
3b54baad
BC		 1818/* l4_per -> gpio2 */
1819static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1820 .master = &omap44xx_l4_per_hwmod,
3b54baad 1821 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1822 .clk = "l4_div_ck",
3b54baad 1823 .addr = omap44xx_gpio2_addrs,
f776471f
BC		 1824 .user = OCP_USER_MPU | OCP_USER_SDMA,
1825};
1826
3b54baad
BC		 1827/* gpio2 slave ports */
1828static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1829 &omap44xx_l4_per__gpio2,
f776471f
BC		 1830};
1831
3b54baad 1832static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1833 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1834};
1835
1836static struct omap_hwmod omap44xx_gpio2_hwmod = {
1837 .name = "gpio2",
1838 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1839 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1840 .mpu_irqs = omap44xx_gpio2_irqs,
3b54baad 1841 .main_clk = "gpio2_ick",
f776471f
BC		 1842 .prcm = {
1843 .omap4 = {
3b54baad 1844 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1845 },
1846 },
3b54baad
BC		 1847 .opt_clks = gpio2_opt_clks,
1848 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1849 .dev_attr = &gpio_dev_attr,
1850 .slaves = omap44xx_gpio2_slaves,
1851 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1852 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1853};
1854
3b54baad
BC		 1855/* gpio3 */
1856static struct omap_hwmod omap44xx_gpio3_hwmod;
1857static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1858 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
212738a4 1859 { .irq = -1 }
f776471f
BC		 1860};
1861
3b54baad 1862static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1863 {
3b54baad
BC		 1864 .pa_start = 0x48057000,
1865 .pa_end = 0x480571ff,
f776471f
BC		 1866 .flags = ADDR_TYPE_RT
1867 },
78183f3f 1868 { }
f776471f
BC		 1869};
1870
3b54baad
BC		 1871/* l4_per -> gpio3 */
1872static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1873 .master = &omap44xx_l4_per_hwmod,
3b54baad 1874 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1875 .clk = "l4_div_ck",
3b54baad 1876 .addr = omap44xx_gpio3_addrs,
f776471f
BC		 1877 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878};
1879
3b54baad
BC		 1880/* gpio3 slave ports */
1881static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1882 &omap44xx_l4_per__gpio3,
f776471f
BC		 1883};
1884
3b54baad 1885static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1886 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1887};
1888
1889static struct omap_hwmod omap44xx_gpio3_hwmod = {
1890 .name = "gpio3",
1891 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1892 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1893 .mpu_irqs = omap44xx_gpio3_irqs,
3b54baad 1894 .main_clk = "gpio3_ick",
f776471f
BC		 1895 .prcm = {
1896 .omap4 = {
3b54baad 1897 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1898 },
1899 },
3b54baad
BC		 1900 .opt_clks = gpio3_opt_clks,
1901 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1902 .dev_attr = &gpio_dev_attr,
1903 .slaves = omap44xx_gpio3_slaves,
1904 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1905 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1906};
1907
3b54baad
BC		 1908/* gpio4 */
1909static struct omap_hwmod omap44xx_gpio4_hwmod;
1910static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1911 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
212738a4 1912 { .irq = -1 }
f776471f
BC		 1913};
1914
3b54baad 1915static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1916 {
3b54baad
BC		 1917 .pa_start = 0x48059000,
1918 .pa_end = 0x480591ff,
f776471f
BC		 1919 .flags = ADDR_TYPE_RT
1920 },
78183f3f 1921 { }
f776471f
BC		 1922};
1923
3b54baad
BC		 1924/* l4_per -> gpio4 */
1925static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1926 .master = &omap44xx_l4_per_hwmod,
3b54baad 1927 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1928 .clk = "l4_div_ck",
3b54baad 1929 .addr = omap44xx_gpio4_addrs,
f776471f
BC		 1930 .user = OCP_USER_MPU | OCP_USER_SDMA,
1931};
1932
3b54baad
BC		 1933/* gpio4 slave ports */
1934static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1935 &omap44xx_l4_per__gpio4,
f776471f
BC		 1936};
1937
3b54baad 1938static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1939 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1940};
1941
1942static struct omap_hwmod omap44xx_gpio4_hwmod = {
1943 .name = "gpio4",
1944 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1946 .mpu_irqs = omap44xx_gpio4_irqs,
3b54baad 1947 .main_clk = "gpio4_ick",
f776471f
BC		 1948 .prcm = {
1949 .omap4 = {
3b54baad 1950 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1951 },
1952 },
3b54baad
BC		 1953 .opt_clks = gpio4_opt_clks,
1954 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1955 .dev_attr = &gpio_dev_attr,
1956 .slaves = omap44xx_gpio4_slaves,
1957 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1958 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1959};
1960
3b54baad
BC		 1961/* gpio5 */
1962static struct omap_hwmod omap44xx_gpio5_hwmod;
1963static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1964 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
212738a4 1965 { .irq = -1 }
55d2cb08
BC		 1966};
1967
3b54baad
BC		 1968static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1969 {
1970 .pa_start = 0x4805b000,
1971 .pa_end = 0x4805b1ff,
1972 .flags = ADDR_TYPE_RT
1973 },
78183f3f 1974 { }
55d2cb08
BC		 1975};
1976
3b54baad
BC		 1977/* l4_per -> gpio5 */
1978static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1979 .master = &omap44xx_l4_per_hwmod,
1980 .slave = &omap44xx_gpio5_hwmod,
b399bca8 1981 .clk = "l4_div_ck",
3b54baad 1982 .addr = omap44xx_gpio5_addrs,
3b54baad 1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 1984};
1985
3b54baad
BC		 1986/* gpio5 slave ports */
1987static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1988 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1989};
1990
3b54baad 1991static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1992 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1993};
1994
3b54baad
BC		 1995static struct omap_hwmod omap44xx_gpio5_hwmod = {
1996 .name = "gpio5",
1997 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1998 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1999 .mpu_irqs = omap44xx_gpio5_irqs,
3b54baad 2000 .main_clk = "gpio5_ick",
55d2cb08
BC		 2001 .prcm = {
2002 .omap4 = {
3b54baad 2003 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 2004 },
2005 },
3b54baad
BC		 2006 .opt_clks = gpio5_opt_clks,
2007 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2008 .dev_attr = &gpio_dev_attr,
2009 .slaves = omap44xx_gpio5_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 2011 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2012};
2013
3b54baad
BC		 2014/* gpio6 */
2015static struct omap_hwmod omap44xx_gpio6_hwmod;
2016static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2017 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
212738a4 2018 { .irq = -1 }
92b18d1c
BC		 2019};
2020
3b54baad 2021static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 2022 {
3b54baad
BC		 2023 .pa_start = 0x4805d000,
2024 .pa_end = 0x4805d1ff,
92b18d1c
BC		 2025 .flags = ADDR_TYPE_RT
2026 },
78183f3f 2027 { }
92b18d1c
BC		 2028};
2029
3b54baad
BC		 2030/* l4_per -> gpio6 */
2031static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2032 .master = &omap44xx_l4_per_hwmod,
2033 .slave = &omap44xx_gpio6_hwmod,
b399bca8 2034 .clk = "l4_div_ck",
3b54baad 2035 .addr = omap44xx_gpio6_addrs,
3b54baad 2036 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 2037};
2038
3b54baad
BC		 2039/* gpio6 slave ports */
2040static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2041 &omap44xx_l4_per__gpio6,
db12ba53
BC		 2042};
2043
3b54baad 2044static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 2045 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 2046};
2047
3b54baad
BC		 2048static struct omap_hwmod omap44xx_gpio6_hwmod = {
2049 .name = "gpio6",
2050 .class = &omap44xx_gpio_hwmod_class,
b399bca8 2051 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2052 .mpu_irqs = omap44xx_gpio6_irqs,
3b54baad
BC		 2053 .main_clk = "gpio6_ick",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2057 },
db12ba53 2058 },
3b54baad
BC		 2059 .opt_clks = gpio6_opt_clks,
2060 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2061 .dev_attr = &gpio_dev_attr,
2062 .slaves = omap44xx_gpio6_slaves,
2063 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2064 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 2065};
2066
407a6888
BC		 2067/*
2068 * 'hsi' class
2069 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2070 * serial if)
2071 */
2072
2073static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2074 .rev_offs = 0x0000,
2075 .sysc_offs = 0x0010,
2076 .syss_offs = 0x0014,
2077 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2078 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2079 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2080 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2081 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2082 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2083 .sysc_fields = &omap_hwmod_sysc_type1,
2084};
2085
2086static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2087 .name = "hsi",
2088 .sysc = &omap44xx_hsi_sysc,
2089};
2090
2091/* hsi */
2092static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2093 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2094 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2095 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
212738a4 2096 { .irq = -1 }
407a6888
BC		 2097};
2098
2099/* hsi master ports */
2100static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2101 &omap44xx_hsi__l3_main_2,
2102};
2103
2104static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2105 {
2106 .pa_start = 0x4a058000,
2107 .pa_end = 0x4a05bfff,
2108 .flags = ADDR_TYPE_RT
2109 },
78183f3f 2110 { }
407a6888
BC		 2111};
2112
2113/* l4_cfg -> hsi */
2114static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2115 .master = &omap44xx_l4_cfg_hwmod,
2116 .slave = &omap44xx_hsi_hwmod,
2117 .clk = "l4_div_ck",
2118 .addr = omap44xx_hsi_addrs,
407a6888
BC		 2119 .user = OCP_USER_MPU | OCP_USER_SDMA,
2120};
2121
2122/* hsi slave ports */
2123static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2124 &omap44xx_l4_cfg__hsi,
2125};
2126
2127static struct omap_hwmod omap44xx_hsi_hwmod = {
2128 .name = "hsi",
2129 .class = &omap44xx_hsi_hwmod_class,
2130 .mpu_irqs = omap44xx_hsi_irqs,
407a6888 2131 .main_clk = "hsi_fck",
00fe610b 2132 .prcm = {
407a6888
BC		 2133 .omap4 = {
2134 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2135 },
2136 },
2137 .slaves = omap44xx_hsi_slaves,
2138 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2139 .masters = omap44xx_hsi_masters,
2140 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2141 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2142};
2143
3b54baad
BC		 2144/*
2145 * 'i2c' class
2146 * multimaster high-speed i2c controller
2147 */
db12ba53 2148
3b54baad
BC		 2149static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2150 .sysc_offs = 0x0010,
2151 .syss_offs = 0x0090,
2152 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2154 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2156 SIDLE_SMART_WKUP),
3b54baad 2157 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2158};
2159
3b54baad 2160static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2161 .name = "i2c",
2162 .sysc = &omap44xx_i2c_sysc,
db12ba53
BC		 2163};
2164
3b54baad
BC		 2165/* i2c1 */
2166static struct omap_hwmod omap44xx_i2c1_hwmod;
2167static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2168 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
212738a4 2169 { .irq = -1 }
db12ba53
BC		 2170};
2171
3b54baad
BC		 2172static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2173 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2174 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
bc614958 2175 { .dma_req = -1 }
db12ba53
BC		 2176};
2177
3b54baad 2178static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2179 {
3b54baad
BC		 2180 .pa_start = 0x48070000,
2181 .pa_end = 0x480700ff,
db12ba53
BC		 2182 .flags = ADDR_TYPE_RT
2183 },
78183f3f 2184 { }
db12ba53
BC		 2185};
2186
3b54baad
BC		 2187/* l4_per -> i2c1 */
2188static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2189 .master = &omap44xx_l4_per_hwmod,
2190 .slave = &omap44xx_i2c1_hwmod,
2191 .clk = "l4_div_ck",
2192 .addr = omap44xx_i2c1_addrs,
92b18d1c
BC		 2193 .user = OCP_USER_MPU | OCP_USER_SDMA,
2194};
2195
3b54baad
BC		 2196/* i2c1 slave ports */
2197static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2198 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2199};
2200
3b54baad
BC		 2201static struct omap_hwmod omap44xx_i2c1_hwmod = {
2202 .name = "i2c1",
2203 .class = &omap44xx_i2c_hwmod_class,
2204 .flags = HWMOD_INIT_NO_RESET,
2205 .mpu_irqs = omap44xx_i2c1_irqs,
3b54baad 2206 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
3b54baad 2207 .main_clk = "i2c1_fck",
92b18d1c
BC		 2208 .prcm = {
2209 .omap4 = {
3b54baad 2210 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 2211 },
2212 },
3b54baad
BC		 2213 .slaves = omap44xx_i2c1_slaves,
2214 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 2215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2216};
2217
3b54baad
BC		 2218/* i2c2 */
2219static struct omap_hwmod omap44xx_i2c2_hwmod;
2220static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2221 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
212738a4 2222 { .irq = -1 }
92b18d1c
BC		 2223};
2224
3b54baad
BC		 2225static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2226 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2227 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
bc614958 2228 { .dma_req = -1 }
3b54baad
BC		 2229};
2230
2231static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2232 {
3b54baad
BC		 2233 .pa_start = 0x48072000,
2234 .pa_end = 0x480720ff,
92b18d1c
BC		 2235 .flags = ADDR_TYPE_RT
2236 },
78183f3f 2237 { }
92b18d1c
BC		 2238};
2239
3b54baad
BC		 2240/* l4_per -> i2c2 */
2241static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2242 .master = &omap44xx_l4_per_hwmod,
3b54baad 2243 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2244 .clk = "l4_div_ck",
3b54baad 2245 .addr = omap44xx_i2c2_addrs,
db12ba53
BC		 2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2247};
2248
3b54baad
BC		 2249/* i2c2 slave ports */
2250static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2251 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2252};
2253
3b54baad
BC		 2254static struct omap_hwmod omap44xx_i2c2_hwmod = {
2255 .name = "i2c2",
2256 .class = &omap44xx_i2c_hwmod_class,
2257 .flags = HWMOD_INIT_NO_RESET,
2258 .mpu_irqs = omap44xx_i2c2_irqs,
3b54baad 2259 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
3b54baad 2260 .main_clk = "i2c2_fck",
db12ba53
BC		 2261 .prcm = {
2262 .omap4 = {
3b54baad 2263 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 2264 },
2265 },
3b54baad
BC		 2266 .slaves = omap44xx_i2c2_slaves,
2267 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 2268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2269};
2270
3b54baad
BC		 2271/* i2c3 */
2272static struct omap_hwmod omap44xx_i2c3_hwmod;
2273static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2274 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
212738a4 2275 { .irq = -1 }
db12ba53
BC		 2276};
2277
3b54baad
BC		 2278static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2279 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2280 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
bc614958 2281 { .dma_req = -1 }
92b18d1c
BC		 2282};
2283
3b54baad 2284static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2285 {
3b54baad
BC		 2286 .pa_start = 0x48060000,
2287 .pa_end = 0x480600ff,
92b18d1c
BC		 2288 .flags = ADDR_TYPE_RT
2289 },
78183f3f 2290 { }
92b18d1c
BC		 2291};
2292
3b54baad
BC		 2293/* l4_per -> i2c3 */
2294static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2295 .master = &omap44xx_l4_per_hwmod,
3b54baad 2296 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2297 .clk = "l4_div_ck",
3b54baad 2298 .addr = omap44xx_i2c3_addrs,
db12ba53
BC		 2299 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300};
2301
3b54baad
BC		 2302/* i2c3 slave ports */
2303static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2304 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2305};
2306
3b54baad
BC		 2307static struct omap_hwmod omap44xx_i2c3_hwmod = {
2308 .name = "i2c3",
2309 .class = &omap44xx_i2c_hwmod_class,
2310 .flags = HWMOD_INIT_NO_RESET,
2311 .mpu_irqs = omap44xx_i2c3_irqs,
3b54baad 2312 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
3b54baad 2313 .main_clk = "i2c3_fck",
db12ba53
BC		 2314 .prcm = {
2315 .omap4 = {
3b54baad 2316 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 2317 },
2318 },
3b54baad
BC		 2319 .slaves = omap44xx_i2c3_slaves,
2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 2321 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2322};
2323
3b54baad
BC		 2324/* i2c4 */
2325static struct omap_hwmod omap44xx_i2c4_hwmod;
2326static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2327 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
212738a4 2328 { .irq = -1 }
db12ba53
BC		 2329};
2330
3b54baad
BC		 2331static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2332 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2333 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
bc614958 2334 { .dma_req = -1 }
db12ba53
BC		 2335};
2336
3b54baad 2337static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2338 {
3b54baad
BC		 2339 .pa_start = 0x48350000,
2340 .pa_end = 0x483500ff,
db12ba53
BC		 2341 .flags = ADDR_TYPE_RT
2342 },
78183f3f 2343 { }
db12ba53
BC		 2344};
2345
3b54baad
BC		 2346/* l4_per -> i2c4 */
2347static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2348 .master = &omap44xx_l4_per_hwmod,
2349 .slave = &omap44xx_i2c4_hwmod,
2350 .clk = "l4_div_ck",
2351 .addr = omap44xx_i2c4_addrs,
3b54baad 2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2353};
2354
3b54baad
BC		 2355/* i2c4 slave ports */
2356static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2357 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2358};
2359
3b54baad
BC		 2360static struct omap_hwmod omap44xx_i2c4_hwmod = {
2361 .name = "i2c4",
2362 .class = &omap44xx_i2c_hwmod_class,
2363 .flags = HWMOD_INIT_NO_RESET,
2364 .mpu_irqs = omap44xx_i2c4_irqs,
3b54baad 2365 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
3b54baad 2366 .main_clk = "i2c4_fck",
92b18d1c
BC		 2367 .prcm = {
2368 .omap4 = {
3b54baad 2369 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 2370 },
2371 },
3b54baad
BC		 2372 .slaves = omap44xx_i2c4_slaves,
2373 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 2374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2375};
2376
407a6888
BC		 2377/*
2378 * 'ipu' class
2379 * imaging processor unit
2380 */
2381
2382static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2383 .name = "ipu",
2384};
2385
2386/* ipu */
2387static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2388 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
212738a4 2389 { .irq = -1 }
407a6888
BC		 2390};
2391
2392static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2393 { .name = "cpu0", .rst_shift = 0 },
2394};
2395
2396static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2397 { .name = "cpu1", .rst_shift = 1 },
2398};
2399
2400static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2401 { .name = "mmu_cache", .rst_shift = 2 },
2402};
2403
2404/* ipu master ports */
2405static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2406 &omap44xx_ipu__l3_main_2,
2407};
2408
2409/* l3_main_2 -> ipu */
2410static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2411 .master = &omap44xx_l3_main_2_hwmod,
2412 .slave = &omap44xx_ipu_hwmod,
2413 .clk = "l3_div_ck",
2414 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415};
2416
2417/* ipu slave ports */
2418static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2419 &omap44xx_l3_main_2__ipu,
2420};
2421
2422/* Pseudo hwmod for reset control purpose only */
2423static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2424 .name = "ipu_c0",
2425 .class = &omap44xx_ipu_hwmod_class,
2426 .flags = HWMOD_INIT_NO_RESET,
2427 .rst_lines = omap44xx_ipu_c0_resets,
2428 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
00fe610b 2429 .prcm = {
407a6888
BC		 2430 .omap4 = {
2431 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2432 },
2433 },
2434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2435};
2436
2437/* Pseudo hwmod for reset control purpose only */
2438static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2439 .name = "ipu_c1",
2440 .class = &omap44xx_ipu_hwmod_class,
2441 .flags = HWMOD_INIT_NO_RESET,
2442 .rst_lines = omap44xx_ipu_c1_resets,
2443 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
00fe610b 2444 .prcm = {
407a6888
BC		 2445 .omap4 = {
2446 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2447 },
2448 },
2449 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2450};
2451
2452static struct omap_hwmod omap44xx_ipu_hwmod = {
2453 .name = "ipu",
2454 .class = &omap44xx_ipu_hwmod_class,
2455 .mpu_irqs = omap44xx_ipu_irqs,
407a6888
BC		 2456 .rst_lines = omap44xx_ipu_resets,
2457 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2458 .main_clk = "ipu_fck",
00fe610b 2459 .prcm = {
407a6888
BC		 2460 .omap4 = {
2461 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2462 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2463 },
2464 },
2465 .slaves = omap44xx_ipu_slaves,
2466 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2467 .masters = omap44xx_ipu_masters,
2468 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2469 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2470};
2471
2472/*
2473 * 'iss' class
2474 * external images sensor pixel data processor
2475 */
2476
2477static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2478 .rev_offs = 0x0000,
2479 .sysc_offs = 0x0010,
2480 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2481 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2482 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2483 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2484 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2485 .sysc_fields = &omap_hwmod_sysc_type2,
2486};
2487
2488static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2489 .name = "iss",
2490 .sysc = &omap44xx_iss_sysc,
2491};
2492
2493/* iss */
2494static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2495 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
212738a4 2496 { .irq = -1 }
407a6888
BC		 2497};
2498
2499static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2500 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2501 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2502 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2503 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
bc614958 2504 { .dma_req = -1 }
407a6888
BC		 2505};
2506
2507/* iss master ports */
2508static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2509 &omap44xx_iss__l3_main_2,
2510};
2511
2512static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2513 {
2514 .pa_start = 0x52000000,
2515 .pa_end = 0x520000ff,
2516 .flags = ADDR_TYPE_RT
2517 },
78183f3f 2518 { }
407a6888
BC		 2519};
2520
2521/* l3_main_2 -> iss */
2522static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2523 .master = &omap44xx_l3_main_2_hwmod,
2524 .slave = &omap44xx_iss_hwmod,
2525 .clk = "l3_div_ck",
2526 .addr = omap44xx_iss_addrs,
407a6888
BC		 2527 .user = OCP_USER_MPU | OCP_USER_SDMA,
2528};
2529
2530/* iss slave ports */
2531static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2532 &omap44xx_l3_main_2__iss,
2533};
2534
2535static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2536 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2537};
2538
2539static struct omap_hwmod omap44xx_iss_hwmod = {
2540 .name = "iss",
2541 .class = &omap44xx_iss_hwmod_class,
2542 .mpu_irqs = omap44xx_iss_irqs,
407a6888 2543 .sdma_reqs = omap44xx_iss_sdma_reqs,
407a6888 2544 .main_clk = "iss_fck",
00fe610b 2545 .prcm = {
407a6888
BC		 2546 .omap4 = {
2547 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2548 },
2549 },
2550 .opt_clks = iss_opt_clks,
2551 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2552 .slaves = omap44xx_iss_slaves,
2553 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2554 .masters = omap44xx_iss_masters,
2555 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2557};
2558
8f25bdc5
BC		 2559/*
2560 * 'iva' class
2561 * multi-standard video encoder/decoder hardware accelerator
2562 */
2563
2564static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2565 .name = "iva",
8f25bdc5
BC		 2566};
2567
2568/* iva */
2569static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2570 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2571 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2572 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
212738a4 2573 { .irq = -1 }
8f25bdc5
BC		 2574};
2575
2576static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2577 { .name = "logic", .rst_shift = 2 },
2578};
2579
2580static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2581 { .name = "seq0", .rst_shift = 0 },
2582};
2583
2584static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2585 { .name = "seq1", .rst_shift = 1 },
2586};
2587
2588/* iva master ports */
2589static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2590 &omap44xx_iva__l3_main_2,
2591 &omap44xx_iva__l3_instr,
2592};
2593
2594static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2595 {
2596 .pa_start = 0x5a000000,
2597 .pa_end = 0x5a07ffff,
2598 .flags = ADDR_TYPE_RT
2599 },
78183f3f 2600 { }
8f25bdc5
BC		 2601};
2602
2603/* l3_main_2 -> iva */
2604static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2605 .master = &omap44xx_l3_main_2_hwmod,
2606 .slave = &omap44xx_iva_hwmod,
2607 .clk = "l3_div_ck",
2608 .addr = omap44xx_iva_addrs,
8f25bdc5
BC		 2609 .user = OCP_USER_MPU,
2610};
2611
2612/* iva slave ports */
2613static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2614 &omap44xx_dsp__iva,
2615 &omap44xx_l3_main_2__iva,
2616};
2617
2618/* Pseudo hwmod for reset control purpose only */
2619static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2620 .name = "iva_seq0",
2621 .class = &omap44xx_iva_hwmod_class,
2622 .flags = HWMOD_INIT_NO_RESET,
2623 .rst_lines = omap44xx_iva_seq0_resets,
2624 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2625 .prcm = {
2626 .omap4 = {
2627 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2628 },
2629 },
2630 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2631};
2632
2633/* Pseudo hwmod for reset control purpose only */
2634static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2635 .name = "iva_seq1",
2636 .class = &omap44xx_iva_hwmod_class,
2637 .flags = HWMOD_INIT_NO_RESET,
2638 .rst_lines = omap44xx_iva_seq1_resets,
2639 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2640 .prcm = {
2641 .omap4 = {
2642 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2643 },
2644 },
2645 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2646};
2647
2648static struct omap_hwmod omap44xx_iva_hwmod = {
2649 .name = "iva",
2650 .class = &omap44xx_iva_hwmod_class,
2651 .mpu_irqs = omap44xx_iva_irqs,
8f25bdc5
BC		 2652 .rst_lines = omap44xx_iva_resets,
2653 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2654 .main_clk = "iva_fck",
2655 .prcm = {
2656 .omap4 = {
2657 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2658 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2659 },
2660 },
2661 .slaves = omap44xx_iva_slaves,
2662 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2663 .masters = omap44xx_iva_masters,
2664 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2665 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2666};
2667
407a6888
BC		 2668/*
2669 * 'kbd' class
2670 * keyboard controller
2671 */
2672
2673static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2674 .rev_offs = 0x0000,
2675 .sysc_offs = 0x0010,
2676 .syss_offs = 0x0014,
2677 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2678 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2679 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2680 SYSS_HAS_RESET_STATUS),
2681 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2682 .sysc_fields = &omap_hwmod_sysc_type1,
2683};
2684
2685static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2686 .name = "kbd",
2687 .sysc = &omap44xx_kbd_sysc,
2688};
2689
2690/* kbd */
2691static struct omap_hwmod omap44xx_kbd_hwmod;
2692static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2693 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
212738a4 2694 { .irq = -1 }
407a6888
BC		 2695};
2696
2697static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2698 {
2699 .pa_start = 0x4a31c000,
2700 .pa_end = 0x4a31c07f,
2701 .flags = ADDR_TYPE_RT
2702 },
78183f3f 2703 { }
407a6888
BC		 2704};
2705
2706/* l4_wkup -> kbd */
2707static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2708 .master = &omap44xx_l4_wkup_hwmod,
2709 .slave = &omap44xx_kbd_hwmod,
2710 .clk = "l4_wkup_clk_mux_ck",
2711 .addr = omap44xx_kbd_addrs,
407a6888
BC		 2712 .user = OCP_USER_MPU | OCP_USER_SDMA,
2713};
2714
2715/* kbd slave ports */
2716static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2717 &omap44xx_l4_wkup__kbd,
2718};
2719
2720static struct omap_hwmod omap44xx_kbd_hwmod = {
2721 .name = "kbd",
2722 .class = &omap44xx_kbd_hwmod_class,
2723 .mpu_irqs = omap44xx_kbd_irqs,
407a6888 2724 .main_clk = "kbd_fck",
00fe610b 2725 .prcm = {
407a6888
BC		 2726 .omap4 = {
2727 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2728 },
2729 },
2730 .slaves = omap44xx_kbd_slaves,
2731 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2732 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2733};
2734
ec5df927
BC		 2735/*
2736 * 'mailbox' class
2737 * mailbox module allowing communication between the on-chip processors using a
2738 * queued mailbox-interrupt mechanism.
2739 */
2740
2741static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2742 .rev_offs = 0x0000,
2743 .sysc_offs = 0x0010,
2744 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2745 SYSC_HAS_SOFTRESET),
2746 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2747 .sysc_fields = &omap_hwmod_sysc_type2,
2748};
2749
2750static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2751 .name = "mailbox",
2752 .sysc = &omap44xx_mailbox_sysc,
2753};
2754
2755/* mailbox */
2756static struct omap_hwmod omap44xx_mailbox_hwmod;
2757static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2758 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
212738a4 2759 { .irq = -1 }
ec5df927
BC		 2760};
2761
2762static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2763 {
2764 .pa_start = 0x4a0f4000,
2765 .pa_end = 0x4a0f41ff,
2766 .flags = ADDR_TYPE_RT
2767 },
78183f3f 2768 { }
ec5df927
BC		 2769};
2770
2771/* l4_cfg -> mailbox */
2772static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2773 .master = &omap44xx_l4_cfg_hwmod,
2774 .slave = &omap44xx_mailbox_hwmod,
2775 .clk = "l4_div_ck",
2776 .addr = omap44xx_mailbox_addrs,
ec5df927
BC		 2777 .user = OCP_USER_MPU | OCP_USER_SDMA,
2778};
2779
2780/* mailbox slave ports */
2781static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2782 &omap44xx_l4_cfg__mailbox,
2783};
2784
2785static struct omap_hwmod omap44xx_mailbox_hwmod = {
2786 .name = "mailbox",
2787 .class = &omap44xx_mailbox_hwmod_class,
2788 .mpu_irqs = omap44xx_mailbox_irqs,
00fe610b 2789 .prcm = {
ec5df927
BC		 2790 .omap4 = {
2791 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2792 },
2793 },
2794 .slaves = omap44xx_mailbox_slaves,
2795 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2796 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2797};
2798
4ddff493
BC		 2799/*
2800 * 'mcbsp' class
2801 * multi channel buffered serial port controller
2802 */
2803
2804static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2805 .sysc_offs = 0x008c,
2806 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2807 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2808 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2809 .sysc_fields = &omap_hwmod_sysc_type1,
2810};
2811
2812static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2813 .name = "mcbsp",
2814 .sysc = &omap44xx_mcbsp_sysc,
cb7e9ded 2815 .rev = MCBSP_CONFIG_TYPE4,
4ddff493
BC		 2816};
2817
2818/* mcbsp1 */
2819static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2820static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2821 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
212738a4 2822 { .irq = -1 }
4ddff493
BC		 2823};
2824
2825static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2826 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2827 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
bc614958 2828 { .dma_req = -1 }
4ddff493
BC		 2829};
2830
2831static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2832 {
cb7e9ded 2833 .name = "mpu",
4ddff493
BC		 2834 .pa_start = 0x40122000,
2835 .pa_end = 0x401220ff,
2836 .flags = ADDR_TYPE_RT
2837 },
78183f3f 2838 { }
4ddff493
BC		 2839};
2840
2841/* l4_abe -> mcbsp1 */
2842static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2843 .master = &omap44xx_l4_abe_hwmod,
2844 .slave = &omap44xx_mcbsp1_hwmod,
2845 .clk = "ocp_abe_iclk",
2846 .addr = omap44xx_mcbsp1_addrs,
4ddff493
BC		 2847 .user = OCP_USER_MPU,
2848};
2849
2850static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2851 {
cb7e9ded 2852 .name = "dma",
4ddff493
BC		 2853 .pa_start = 0x49022000,
2854 .pa_end = 0x490220ff,
2855 .flags = ADDR_TYPE_RT
2856 },
78183f3f 2857 { }
4ddff493
BC		 2858};
2859
2860/* l4_abe -> mcbsp1 (dma) */
2861static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2862 .master = &omap44xx_l4_abe_hwmod,
2863 .slave = &omap44xx_mcbsp1_hwmod,
2864 .clk = "ocp_abe_iclk",
2865 .addr = omap44xx_mcbsp1_dma_addrs,
4ddff493
BC		 2866 .user = OCP_USER_SDMA,
2867};
2868
2869/* mcbsp1 slave ports */
2870static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2871 &omap44xx_l4_abe__mcbsp1,
2872 &omap44xx_l4_abe__mcbsp1_dma,
2873};
2874
2875static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2876 .name = "mcbsp1",
2877 .class = &omap44xx_mcbsp_hwmod_class,
2878 .mpu_irqs = omap44xx_mcbsp1_irqs,
4ddff493 2879 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
4ddff493
BC		 2880 .main_clk = "mcbsp1_fck",
2881 .prcm = {
2882 .omap4 = {
2883 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2884 },
2885 },
2886 .slaves = omap44xx_mcbsp1_slaves,
2887 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2888 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2889};
2890
2891/* mcbsp2 */
2892static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2893static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2894 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
212738a4 2895 { .irq = -1 }
4ddff493
BC		 2896};
2897
2898static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2899 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2900 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
bc614958 2901 { .dma_req = -1 }
4ddff493
BC		 2902};
2903
2904static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2905 {
cb7e9ded 2906 .name = "mpu",
4ddff493
BC		 2907 .pa_start = 0x40124000,
2908 .pa_end = 0x401240ff,
2909 .flags = ADDR_TYPE_RT
2910 },
78183f3f 2911 { }
4ddff493
BC		 2912};
2913
2914/* l4_abe -> mcbsp2 */
2915static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2916 .master = &omap44xx_l4_abe_hwmod,
2917 .slave = &omap44xx_mcbsp2_hwmod,
2918 .clk = "ocp_abe_iclk",
2919 .addr = omap44xx_mcbsp2_addrs,
4ddff493
BC		 2920 .user = OCP_USER_MPU,
2921};
2922
2923static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2924 {
cb7e9ded 2925 .name = "dma",
4ddff493
BC		 2926 .pa_start = 0x49024000,
2927 .pa_end = 0x490240ff,
2928 .flags = ADDR_TYPE_RT
2929 },
78183f3f 2930 { }
4ddff493
BC		 2931};
2932
2933/* l4_abe -> mcbsp2 (dma) */
2934static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2935 .master = &omap44xx_l4_abe_hwmod,
2936 .slave = &omap44xx_mcbsp2_hwmod,
2937 .clk = "ocp_abe_iclk",
2938 .addr = omap44xx_mcbsp2_dma_addrs,
4ddff493
BC		 2939 .user = OCP_USER_SDMA,
2940};
2941
2942/* mcbsp2 slave ports */
2943static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2944 &omap44xx_l4_abe__mcbsp2,
2945 &omap44xx_l4_abe__mcbsp2_dma,
2946};
2947
2948static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2949 .name = "mcbsp2",
2950 .class = &omap44xx_mcbsp_hwmod_class,
2951 .mpu_irqs = omap44xx_mcbsp2_irqs,
4ddff493 2952 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
4ddff493
BC		 2953 .main_clk = "mcbsp2_fck",
2954 .prcm = {
2955 .omap4 = {
2956 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2957 },
2958 },
2959 .slaves = omap44xx_mcbsp2_slaves,
2960 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2961 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2962};
2963
2964/* mcbsp3 */
2965static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2966static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2967 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
212738a4 2968 { .irq = -1 }
4ddff493
BC		 2969};
2970
2971static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2972 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2973 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
bc614958 2974 { .dma_req = -1 }
4ddff493
BC		 2975};
2976
2977static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2978 {
cb7e9ded 2979 .name = "mpu",
4ddff493
BC		 2980 .pa_start = 0x40126000,
2981 .pa_end = 0x401260ff,
2982 .flags = ADDR_TYPE_RT
2983 },
78183f3f 2984 { }
4ddff493
BC		 2985};
2986
2987/* l4_abe -> mcbsp3 */
2988static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2989 .master = &omap44xx_l4_abe_hwmod,
2990 .slave = &omap44xx_mcbsp3_hwmod,
2991 .clk = "ocp_abe_iclk",
2992 .addr = omap44xx_mcbsp3_addrs,
4ddff493
BC		 2993 .user = OCP_USER_MPU,
2994};
2995
2996static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2997 {
cb7e9ded 2998 .name = "dma",
4ddff493
BC		 2999 .pa_start = 0x49026000,
3000 .pa_end = 0x490260ff,
3001 .flags = ADDR_TYPE_RT
3002 },
78183f3f 3003 { }
4ddff493
BC		 3004};
3005
3006/* l4_abe -> mcbsp3 (dma) */
3007static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3008 .master = &omap44xx_l4_abe_hwmod,
3009 .slave = &omap44xx_mcbsp3_hwmod,
3010 .clk = "ocp_abe_iclk",
3011 .addr = omap44xx_mcbsp3_dma_addrs,
4ddff493
BC		 3012 .user = OCP_USER_SDMA,
3013};
3014
3015/* mcbsp3 slave ports */
3016static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3017 &omap44xx_l4_abe__mcbsp3,
3018 &omap44xx_l4_abe__mcbsp3_dma,
3019};
3020
3021static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3022 .name = "mcbsp3",
3023 .class = &omap44xx_mcbsp_hwmod_class,
3024 .mpu_irqs = omap44xx_mcbsp3_irqs,
4ddff493 3025 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
4ddff493
BC		 3026 .main_clk = "mcbsp3_fck",
3027 .prcm = {
3028 .omap4 = {
3029 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3030 },
3031 },
3032 .slaves = omap44xx_mcbsp3_slaves,
3033 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3034 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3035};
3036
3037/* mcbsp4 */
3038static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3039static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3040 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
212738a4 3041 { .irq = -1 }
4ddff493
BC		 3042};
3043
3044static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3045 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3046 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
bc614958 3047 { .dma_req = -1 }
4ddff493
BC		 3048};
3049
3050static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3051 {
3052 .pa_start = 0x48096000,
3053 .pa_end = 0x480960ff,
3054 .flags = ADDR_TYPE_RT
3055 },
78183f3f 3056 { }
4ddff493
BC		 3057};
3058
3059/* l4_per -> mcbsp4 */
3060static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3061 .master = &omap44xx_l4_per_hwmod,
3062 .slave = &omap44xx_mcbsp4_hwmod,
3063 .clk = "l4_div_ck",
3064 .addr = omap44xx_mcbsp4_addrs,
4ddff493
BC		 3065 .user = OCP_USER_MPU | OCP_USER_SDMA,
3066};
3067
3068/* mcbsp4 slave ports */
3069static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3070 &omap44xx_l4_per__mcbsp4,
3071};
3072
3073static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3074 .name = "mcbsp4",
3075 .class = &omap44xx_mcbsp_hwmod_class,
3076 .mpu_irqs = omap44xx_mcbsp4_irqs,
4ddff493 3077 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
4ddff493
BC		 3078 .main_clk = "mcbsp4_fck",
3079 .prcm = {
3080 .omap4 = {
3081 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3082 },
3083 },
3084 .slaves = omap44xx_mcbsp4_slaves,
3085 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3086 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3087};
3088
407a6888
BC		 3089/*
3090 * 'mcpdm' class
3091 * multi channel pdm controller (proprietary interface with phoenix power
3092 * ic)
3093 */
3094
3095static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3096 .rev_offs = 0x0000,
3097 .sysc_offs = 0x0010,
3098 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3099 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3100 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3101 SIDLE_SMART_WKUP),
3102 .sysc_fields = &omap_hwmod_sysc_type2,
3103};
3104
3105static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3106 .name = "mcpdm",
3107 .sysc = &omap44xx_mcpdm_sysc,
3108};
3109
3110/* mcpdm */
3111static struct omap_hwmod omap44xx_mcpdm_hwmod;
3112static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3113 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
212738a4 3114 { .irq = -1 }
407a6888
BC		 3115};
3116
3117static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3118 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3119 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
bc614958 3120 { .dma_req = -1 }
407a6888
BC		 3121};
3122
3123static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3124 {
3125 .pa_start = 0x40132000,
3126 .pa_end = 0x4013207f,
3127 .flags = ADDR_TYPE_RT
3128 },
78183f3f 3129 { }
407a6888
BC		 3130};
3131
3132/* l4_abe -> mcpdm */
3133static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3134 .master = &omap44xx_l4_abe_hwmod,
3135 .slave = &omap44xx_mcpdm_hwmod,
3136 .clk = "ocp_abe_iclk",
3137 .addr = omap44xx_mcpdm_addrs,
407a6888
BC		 3138 .user = OCP_USER_MPU,
3139};
3140
3141static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3142 {
3143 .pa_start = 0x49032000,
3144 .pa_end = 0x4903207f,
3145 .flags = ADDR_TYPE_RT
3146 },
78183f3f 3147 { }
407a6888
BC		 3148};
3149
3150/* l4_abe -> mcpdm (dma) */
3151static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3152 .master = &omap44xx_l4_abe_hwmod,
3153 .slave = &omap44xx_mcpdm_hwmod,
3154 .clk = "ocp_abe_iclk",
3155 .addr = omap44xx_mcpdm_dma_addrs,
407a6888
BC		 3156 .user = OCP_USER_SDMA,
3157};
3158
3159/* mcpdm slave ports */
3160static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3161 &omap44xx_l4_abe__mcpdm,
3162 &omap44xx_l4_abe__mcpdm_dma,
3163};
3164
3165static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3166 .name = "mcpdm",
3167 .class = &omap44xx_mcpdm_hwmod_class,
3168 .mpu_irqs = omap44xx_mcpdm_irqs,
407a6888 3169 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
407a6888 3170 .main_clk = "mcpdm_fck",
00fe610b 3171 .prcm = {
407a6888
BC		 3172 .omap4 = {
3173 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3174 },
3175 },
3176 .slaves = omap44xx_mcpdm_slaves,
3177 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3179};
3180
9bcbd7f0
BC		 3181/*
3182 * 'mcspi' class
3183 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3184 * bus
3185 */
3186
3187static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3188 .rev_offs = 0x0000,
3189 .sysc_offs = 0x0010,
3190 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3191 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3192 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3193 SIDLE_SMART_WKUP),
3194 .sysc_fields = &omap_hwmod_sysc_type2,
3195};
3196
3197static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3198 .name = "mcspi",
3199 .sysc = &omap44xx_mcspi_sysc,
905a74d9 3200 .rev = OMAP4_MCSPI_REV,
9bcbd7f0
BC		 3201};
3202
3203/* mcspi1 */
3204static struct omap_hwmod omap44xx_mcspi1_hwmod;
3205static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3206 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
212738a4 3207 { .irq = -1 }
9bcbd7f0
BC		 3208};
3209
3210static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3211 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3212 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3213 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3214 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3215 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3216 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3217 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3218 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
bc614958 3219 { .dma_req = -1 }
9bcbd7f0
BC		 3220};
3221
3222static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3223 {
3224 .pa_start = 0x48098000,
3225 .pa_end = 0x480981ff,
3226 .flags = ADDR_TYPE_RT
3227 },
78183f3f 3228 { }
9bcbd7f0
BC		 3229};
3230
3231/* l4_per -> mcspi1 */
3232static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3233 .master = &omap44xx_l4_per_hwmod,
3234 .slave = &omap44xx_mcspi1_hwmod,
3235 .clk = "l4_div_ck",
3236 .addr = omap44xx_mcspi1_addrs,
9bcbd7f0
BC		 3237 .user = OCP_USER_MPU | OCP_USER_SDMA,
3238};
3239
3240/* mcspi1 slave ports */
3241static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3242 &omap44xx_l4_per__mcspi1,
3243};
3244
905a74d9
BC		 3245/* mcspi1 dev_attr */
3246static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3247 .num_chipselect = 4,
3248};
3249
9bcbd7f0
BC		 3250static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3251 .name = "mcspi1",
3252 .class = &omap44xx_mcspi_hwmod_class,
3253 .mpu_irqs = omap44xx_mcspi1_irqs,
9bcbd7f0 3254 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
9bcbd7f0
BC		 3255 .main_clk = "mcspi1_fck",
3256 .prcm = {
3257 .omap4 = {
3258 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3259 },
3260 },
905a74d9 3261 .dev_attr = &mcspi1_dev_attr,
9bcbd7f0
BC		 3262 .slaves = omap44xx_mcspi1_slaves,
3263 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3264 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3265};
3266
3267/* mcspi2 */
3268static struct omap_hwmod omap44xx_mcspi2_hwmod;
3269static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3270 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
212738a4 3271 { .irq = -1 }
9bcbd7f0
BC		 3272};
3273
3274static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3275 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3276 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3277 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3278 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
bc614958 3279 { .dma_req = -1 }
9bcbd7f0
BC		 3280};
3281
3282static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3283 {
3284 .pa_start = 0x4809a000,
3285 .pa_end = 0x4809a1ff,
3286 .flags = ADDR_TYPE_RT
3287 },
78183f3f 3288 { }
9bcbd7f0
BC		 3289};
3290
3291/* l4_per -> mcspi2 */
3292static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3293 .master = &omap44xx_l4_per_hwmod,
3294 .slave = &omap44xx_mcspi2_hwmod,
3295 .clk = "l4_div_ck",
3296 .addr = omap44xx_mcspi2_addrs,
9bcbd7f0
BC		 3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298};
3299
3300/* mcspi2 slave ports */
3301static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3302 &omap44xx_l4_per__mcspi2,
3303};
3304
905a74d9
BC		 3305/* mcspi2 dev_attr */
3306static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3307 .num_chipselect = 2,
3308};
3309
9bcbd7f0
BC		 3310static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3311 .name = "mcspi2",
3312 .class = &omap44xx_mcspi_hwmod_class,
3313 .mpu_irqs = omap44xx_mcspi2_irqs,
9bcbd7f0 3314 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
9bcbd7f0
BC		 3315 .main_clk = "mcspi2_fck",
3316 .prcm = {
3317 .omap4 = {
3318 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3319 },
3320 },
905a74d9 3321 .dev_attr = &mcspi2_dev_attr,
9bcbd7f0
BC		 3322 .slaves = omap44xx_mcspi2_slaves,
3323 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3324 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3325};
3326
3327/* mcspi3 */
3328static struct omap_hwmod omap44xx_mcspi3_hwmod;
3329static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3330 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
212738a4 3331 { .irq = -1 }
9bcbd7f0
BC		 3332};
3333
3334static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3335 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3336 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3337 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3338 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
bc614958 3339 { .dma_req = -1 }
9bcbd7f0
BC		 3340};
3341
3342static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3343 {
3344 .pa_start = 0x480b8000,
3345 .pa_end = 0x480b81ff,
3346 .flags = ADDR_TYPE_RT
3347 },
78183f3f 3348 { }
9bcbd7f0
BC		 3349};
3350
3351/* l4_per -> mcspi3 */
3352static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3353 .master = &omap44xx_l4_per_hwmod,
3354 .slave = &omap44xx_mcspi3_hwmod,
3355 .clk = "l4_div_ck",
3356 .addr = omap44xx_mcspi3_addrs,
9bcbd7f0
BC		 3357 .user = OCP_USER_MPU | OCP_USER_SDMA,
3358};
3359
3360/* mcspi3 slave ports */
3361static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3362 &omap44xx_l4_per__mcspi3,
3363};
3364
905a74d9
BC		 3365/* mcspi3 dev_attr */
3366static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3367 .num_chipselect = 2,
3368};
3369
9bcbd7f0
BC		 3370static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3371 .name = "mcspi3",
3372 .class = &omap44xx_mcspi_hwmod_class,
3373 .mpu_irqs = omap44xx_mcspi3_irqs,
9bcbd7f0 3374 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
9bcbd7f0
BC		 3375 .main_clk = "mcspi3_fck",
3376 .prcm = {
3377 .omap4 = {
3378 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3379 },
3380 },
905a74d9 3381 .dev_attr = &mcspi3_dev_attr,
9bcbd7f0
BC		 3382 .slaves = omap44xx_mcspi3_slaves,
3383 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3385};
3386
3387/* mcspi4 */
3388static struct omap_hwmod omap44xx_mcspi4_hwmod;
3389static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3390 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
212738a4 3391 { .irq = -1 }
9bcbd7f0
BC		 3392};
3393
3394static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3395 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3396 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
bc614958 3397 { .dma_req = -1 }
9bcbd7f0
BC		 3398};
3399
3400static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3401 {
3402 .pa_start = 0x480ba000,
3403 .pa_end = 0x480ba1ff,
3404 .flags = ADDR_TYPE_RT
3405 },
78183f3f 3406 { }
9bcbd7f0
BC		 3407};
3408
3409/* l4_per -> mcspi4 */
3410static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3411 .master = &omap44xx_l4_per_hwmod,
3412 .slave = &omap44xx_mcspi4_hwmod,
3413 .clk = "l4_div_ck",
3414 .addr = omap44xx_mcspi4_addrs,
9bcbd7f0
BC		 3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416};
3417
3418/* mcspi4 slave ports */
3419static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3420 &omap44xx_l4_per__mcspi4,
3421};
3422
905a74d9
BC		 3423/* mcspi4 dev_attr */
3424static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3425 .num_chipselect = 1,
3426};
3427
9bcbd7f0
BC		 3428static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3429 .name = "mcspi4",
3430 .class = &omap44xx_mcspi_hwmod_class,
3431 .mpu_irqs = omap44xx_mcspi4_irqs,
9bcbd7f0 3432 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
9bcbd7f0
BC		 3433 .main_clk = "mcspi4_fck",
3434 .prcm = {
3435 .omap4 = {
3436 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3437 },
3438 },
905a74d9 3439 .dev_attr = &mcspi4_dev_attr,
9bcbd7f0
BC		 3440 .slaves = omap44xx_mcspi4_slaves,
3441 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3442 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3443};
3444
407a6888
BC		 3445/*
3446 * 'mmc' class
3447 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3448 */
3449
3450static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3451 .rev_offs = 0x0000,
3452 .sysc_offs = 0x0010,
3453 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3454 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3455 SYSC_HAS_SOFTRESET),
3456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3457 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 3458 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 3459 .sysc_fields = &omap_hwmod_sysc_type2,
3460};
3461
3462static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3463 .name = "mmc",
3464 .sysc = &omap44xx_mmc_sysc,
3465};
3466
3467/* mmc1 */
3468static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3469 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
212738a4 3470 { .irq = -1 }
407a6888
BC		 3471};
3472
3473static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3474 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3475 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
bc614958 3476 { .dma_req = -1 }
407a6888
BC		 3477};
3478
3479/* mmc1 master ports */
3480static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3481 &omap44xx_mmc1__l3_main_1,
3482};
3483
3484static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3485 {
3486 .pa_start = 0x4809c000,
3487 .pa_end = 0x4809c3ff,
3488 .flags = ADDR_TYPE_RT
3489 },
78183f3f 3490 { }
407a6888
BC		 3491};
3492
3493/* l4_per -> mmc1 */
3494static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3495 .master = &omap44xx_l4_per_hwmod,
3496 .slave = &omap44xx_mmc1_hwmod,
3497 .clk = "l4_div_ck",
3498 .addr = omap44xx_mmc1_addrs,
407a6888
BC		 3499 .user = OCP_USER_MPU | OCP_USER_SDMA,
3500};
3501
3502/* mmc1 slave ports */
3503static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3504 &omap44xx_l4_per__mmc1,
3505};
3506
6ab8946f
KK		 3507/* mmc1 dev_attr */
3508static struct omap_mmc_dev_attr mmc1_dev_attr = {
3509 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3510};
3511
407a6888
BC		 3512static struct omap_hwmod omap44xx_mmc1_hwmod = {
3513 .name = "mmc1",
3514 .class = &omap44xx_mmc_hwmod_class,
3515 .mpu_irqs = omap44xx_mmc1_irqs,
407a6888 3516 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
407a6888 3517 .main_clk = "mmc1_fck",
00fe610b 3518 .prcm = {
407a6888
BC		 3519 .omap4 = {
3520 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3521 },
3522 },
6ab8946f 3523 .dev_attr = &mmc1_dev_attr,
407a6888
BC		 3524 .slaves = omap44xx_mmc1_slaves,
3525 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3526 .masters = omap44xx_mmc1_masters,
3527 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3528 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3529};
3530
3531/* mmc2 */
3532static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3533 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
212738a4 3534 { .irq = -1 }
407a6888
BC		 3535};
3536
3537static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3538 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3539 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
bc614958 3540 { .dma_req = -1 }
407a6888
BC		 3541};
3542
3543/* mmc2 master ports */
3544static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3545 &omap44xx_mmc2__l3_main_1,
3546};
3547
3548static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3549 {
3550 .pa_start = 0x480b4000,
3551 .pa_end = 0x480b43ff,
3552 .flags = ADDR_TYPE_RT
3553 },
78183f3f 3554 { }
407a6888
BC		 3555};
3556
3557/* l4_per -> mmc2 */
3558static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3559 .master = &omap44xx_l4_per_hwmod,
3560 .slave = &omap44xx_mmc2_hwmod,
3561 .clk = "l4_div_ck",
3562 .addr = omap44xx_mmc2_addrs,
407a6888
BC		 3563 .user = OCP_USER_MPU | OCP_USER_SDMA,
3564};
3565
3566/* mmc2 slave ports */
3567static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3568 &omap44xx_l4_per__mmc2,
3569};
3570
3571static struct omap_hwmod omap44xx_mmc2_hwmod = {
3572 .name = "mmc2",
3573 .class = &omap44xx_mmc_hwmod_class,
3574 .mpu_irqs = omap44xx_mmc2_irqs,
407a6888 3575 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
407a6888 3576 .main_clk = "mmc2_fck",
00fe610b 3577 .prcm = {
407a6888
BC		 3578 .omap4 = {
3579 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3580 },
3581 },
3582 .slaves = omap44xx_mmc2_slaves,
3583 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3584 .masters = omap44xx_mmc2_masters,
3585 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3586 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3587};
3588
3589/* mmc3 */
3590static struct omap_hwmod omap44xx_mmc3_hwmod;
3591static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3592 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
212738a4 3593 { .irq = -1 }
407a6888
BC		 3594};
3595
3596static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3597 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3598 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
bc614958 3599 { .dma_req = -1 }
407a6888
BC		 3600};
3601
3602static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3603 {
3604 .pa_start = 0x480ad000,
3605 .pa_end = 0x480ad3ff,
3606 .flags = ADDR_TYPE_RT
3607 },
78183f3f 3608 { }
407a6888
BC		 3609};
3610
3611/* l4_per -> mmc3 */
3612static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3613 .master = &omap44xx_l4_per_hwmod,
3614 .slave = &omap44xx_mmc3_hwmod,
3615 .clk = "l4_div_ck",
3616 .addr = omap44xx_mmc3_addrs,
407a6888
BC		 3617 .user = OCP_USER_MPU | OCP_USER_SDMA,
3618};
3619
3620/* mmc3 slave ports */
3621static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3622 &omap44xx_l4_per__mmc3,
3623};
3624
3625static struct omap_hwmod omap44xx_mmc3_hwmod = {
3626 .name = "mmc3",
3627 .class = &omap44xx_mmc_hwmod_class,
3628 .mpu_irqs = omap44xx_mmc3_irqs,
407a6888 3629 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
407a6888 3630 .main_clk = "mmc3_fck",
00fe610b 3631 .prcm = {
407a6888
BC		 3632 .omap4 = {
3633 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3634 },
3635 },
3636 .slaves = omap44xx_mmc3_slaves,
3637 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3638 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3639};
3640
3641/* mmc4 */
3642static struct omap_hwmod omap44xx_mmc4_hwmod;
3643static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3644 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
212738a4 3645 { .irq = -1 }
407a6888
BC		 3646};
3647
3648static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3649 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3650 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
bc614958 3651 { .dma_req = -1 }
407a6888
BC		 3652};
3653
3654static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3655 {
3656 .pa_start = 0x480d1000,
3657 .pa_end = 0x480d13ff,
3658 .flags = ADDR_TYPE_RT
3659 },
78183f3f 3660 { }
407a6888
BC		 3661};
3662
3663/* l4_per -> mmc4 */
3664static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3665 .master = &omap44xx_l4_per_hwmod,
3666 .slave = &omap44xx_mmc4_hwmod,
3667 .clk = "l4_div_ck",
3668 .addr = omap44xx_mmc4_addrs,
407a6888
BC		 3669 .user = OCP_USER_MPU | OCP_USER_SDMA,
3670};
3671
3672/* mmc4 slave ports */
3673static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3674 &omap44xx_l4_per__mmc4,
3675};
3676
3677static struct omap_hwmod omap44xx_mmc4_hwmod = {
3678 .name = "mmc4",
3679 .class = &omap44xx_mmc_hwmod_class,
3680 .mpu_irqs = omap44xx_mmc4_irqs,
212738a4 3681
407a6888 3682 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
407a6888 3683 .main_clk = "mmc4_fck",
00fe610b 3684 .prcm = {
407a6888
BC		 3685 .omap4 = {
3686 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3687 },
3688 },
3689 .slaves = omap44xx_mmc4_slaves,
3690 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3692};
3693
3694/* mmc5 */
3695static struct omap_hwmod omap44xx_mmc5_hwmod;
3696static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3697 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
212738a4 3698 { .irq = -1 }
407a6888
BC		 3699};
3700
3701static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3702 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3703 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
bc614958 3704 { .dma_req = -1 }
407a6888
BC		 3705};
3706
3707static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3708 {
3709 .pa_start = 0x480d5000,
3710 .pa_end = 0x480d53ff,
3711 .flags = ADDR_TYPE_RT
3712 },
78183f3f 3713 { }
407a6888
BC		 3714};
3715
3716/* l4_per -> mmc5 */
3717static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3718 .master = &omap44xx_l4_per_hwmod,
3719 .slave = &omap44xx_mmc5_hwmod,
3720 .clk = "l4_div_ck",
3721 .addr = omap44xx_mmc5_addrs,
407a6888
BC		 3722 .user = OCP_USER_MPU | OCP_USER_SDMA,
3723};
3724
3725/* mmc5 slave ports */
3726static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3727 &omap44xx_l4_per__mmc5,
3728};
3729
3730static struct omap_hwmod omap44xx_mmc5_hwmod = {
3731 .name = "mmc5",
3732 .class = &omap44xx_mmc_hwmod_class,
3733 .mpu_irqs = omap44xx_mmc5_irqs,
407a6888 3734 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
407a6888 3735 .main_clk = "mmc5_fck",
00fe610b 3736 .prcm = {
407a6888
BC		 3737 .omap4 = {
3738 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3739 },
3740 },
3741 .slaves = omap44xx_mmc5_slaves,
3742 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3743 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3744};
3745
3b54baad
BC		 3746/*
3747 * 'mpu' class
3748 * mpu sub-system
3749 */
3750
3751static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3752 .name = "mpu",
db12ba53
BC		 3753};
3754
3b54baad
BC		 3755/* mpu */
3756static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3757 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3758 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3759 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
212738a4 3760 { .irq = -1 }
db12ba53
BC		 3761};
3762
3b54baad
BC		 3763/* mpu master ports */
3764static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3765 &omap44xx_mpu__l3_main_1,
3766 &omap44xx_mpu__l4_abe,
3767 &omap44xx_mpu__dmm,
3768};
3769
3770static struct omap_hwmod omap44xx_mpu_hwmod = {
3771 .name = "mpu",
3772 .class = &omap44xx_mpu_hwmod_class,
7ecc5373 3773 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 3774 .mpu_irqs = omap44xx_mpu_irqs,
3b54baad 3775 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3776 .prcm = {
3777 .omap4 = {
3b54baad 3778 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 3779 },
3780 },
3b54baad
BC		 3781 .masters = omap44xx_mpu_masters,
3782 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3783 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3784};
3785
1f6a717f
BC		 3786/*
3787 * 'smartreflex' class
3788 * smartreflex module (monitor silicon performance and outputs a measure of
3789 * performance error)
3790 */
3791
3792/* The IP is not compliant to type1 / type2 scheme */
3793static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3794 .sidle_shift = 24,
3795 .enwkup_shift = 26,
3796};
3797
3798static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3799 .sysc_offs = 0x0038,
3800 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3801 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3802 SIDLE_SMART_WKUP),
3803 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3804};
3805
3806static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3807 .name = "smartreflex",
3808 .sysc = &omap44xx_smartreflex_sysc,
3809 .rev = 2,
1f6a717f
BC		 3810};
3811
3812/* smartreflex_core */
3813static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3814static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3815 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
212738a4 3816 { .irq = -1 }
1f6a717f
BC		 3817};
3818
3819static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3820 {
3821 .pa_start = 0x4a0dd000,
3822 .pa_end = 0x4a0dd03f,
3823 .flags = ADDR_TYPE_RT
3824 },
78183f3f 3825 { }
1f6a717f
BC		 3826};
3827
3828/* l4_cfg -> smartreflex_core */
3829static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3830 .master = &omap44xx_l4_cfg_hwmod,
3831 .slave = &omap44xx_smartreflex_core_hwmod,
3832 .clk = "l4_div_ck",
3833 .addr = omap44xx_smartreflex_core_addrs,
1f6a717f
BC		 3834 .user = OCP_USER_MPU | OCP_USER_SDMA,
3835};
3836
3837/* smartreflex_core slave ports */
3838static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3839 &omap44xx_l4_cfg__smartreflex_core,
3840};
3841
3842static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3843 .name = "smartreflex_core",
3844 .class = &omap44xx_smartreflex_hwmod_class,
3845 .mpu_irqs = omap44xx_smartreflex_core_irqs,
212738a4 3846
1f6a717f
BC		 3847 .main_clk = "smartreflex_core_fck",
3848 .vdd_name = "core",
3849 .prcm = {
3850 .omap4 = {
3851 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3852 },
3853 },
3854 .slaves = omap44xx_smartreflex_core_slaves,
3855 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3856 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3857};
3858
3859/* smartreflex_iva */
3860static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3861static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3862 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
212738a4 3863 { .irq = -1 }
1f6a717f
BC		 3864};
3865
3866static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3867 {
3868 .pa_start = 0x4a0db000,
3869 .pa_end = 0x4a0db03f,
3870 .flags = ADDR_TYPE_RT
3871 },
78183f3f 3872 { }
1f6a717f
BC		 3873};
3874
3875/* l4_cfg -> smartreflex_iva */
3876static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3877 .master = &omap44xx_l4_cfg_hwmod,
3878 .slave = &omap44xx_smartreflex_iva_hwmod,
3879 .clk = "l4_div_ck",
3880 .addr = omap44xx_smartreflex_iva_addrs,
1f6a717f
BC		 3881 .user = OCP_USER_MPU | OCP_USER_SDMA,
3882};
3883
3884/* smartreflex_iva slave ports */
3885static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3886 &omap44xx_l4_cfg__smartreflex_iva,
3887};
3888
3889static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3890 .name = "smartreflex_iva",
3891 .class = &omap44xx_smartreflex_hwmod_class,
3892 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1f6a717f
BC		 3893 .main_clk = "smartreflex_iva_fck",
3894 .vdd_name = "iva",
3895 .prcm = {
3896 .omap4 = {
3897 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3898 },
3899 },
3900 .slaves = omap44xx_smartreflex_iva_slaves,
3901 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3902 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3903};
3904
3905/* smartreflex_mpu */
3906static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3907static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3908 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
212738a4 3909 { .irq = -1 }
1f6a717f
BC		 3910};
3911
3912static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3913 {
3914 .pa_start = 0x4a0d9000,
3915 .pa_end = 0x4a0d903f,
3916 .flags = ADDR_TYPE_RT
3917 },
78183f3f 3918 { }
1f6a717f
BC		 3919};
3920
3921/* l4_cfg -> smartreflex_mpu */
3922static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3923 .master = &omap44xx_l4_cfg_hwmod,
3924 .slave = &omap44xx_smartreflex_mpu_hwmod,
3925 .clk = "l4_div_ck",
3926 .addr = omap44xx_smartreflex_mpu_addrs,
1f6a717f
BC		 3927 .user = OCP_USER_MPU | OCP_USER_SDMA,
3928};
3929
3930/* smartreflex_mpu slave ports */
3931static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3932 &omap44xx_l4_cfg__smartreflex_mpu,
3933};
3934
3935static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3936 .name = "smartreflex_mpu",
3937 .class = &omap44xx_smartreflex_hwmod_class,
3938 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1f6a717f
BC		 3939 .main_clk = "smartreflex_mpu_fck",
3940 .vdd_name = "mpu",
3941 .prcm = {
3942 .omap4 = {
3943 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3944 },
3945 },
3946 .slaves = omap44xx_smartreflex_mpu_slaves,
3947 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3948 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3949};
3950
d11c217f
BC		 3951/*
3952 * 'spinlock' class
3953 * spinlock provides hardware assistance for synchronizing the processes
3954 * running on multiple processors
3955 */
3956
3957static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3958 .rev_offs = 0x0000,
3959 .sysc_offs = 0x0010,
3960 .syss_offs = 0x0014,
3961 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3962 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3963 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3964 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3965 SIDLE_SMART_WKUP),
3966 .sysc_fields = &omap_hwmod_sysc_type1,
3967};
3968
3969static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3970 .name = "spinlock",
3971 .sysc = &omap44xx_spinlock_sysc,
3972};
3973
3974/* spinlock */
3975static struct omap_hwmod omap44xx_spinlock_hwmod;
3976static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3977 {
3978 .pa_start = 0x4a0f6000,
3979 .pa_end = 0x4a0f6fff,
3980 .flags = ADDR_TYPE_RT
3981 },
78183f3f 3982 { }
d11c217f
BC		 3983};
3984
3985/* l4_cfg -> spinlock */
3986static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3987 .master = &omap44xx_l4_cfg_hwmod,
3988 .slave = &omap44xx_spinlock_hwmod,
3989 .clk = "l4_div_ck",
3990 .addr = omap44xx_spinlock_addrs,
d11c217f
BC		 3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3992};
3993
3994/* spinlock slave ports */
3995static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3996 &omap44xx_l4_cfg__spinlock,
3997};
3998
3999static struct omap_hwmod omap44xx_spinlock_hwmod = {
4000 .name = "spinlock",
4001 .class = &omap44xx_spinlock_hwmod_class,
4002 .prcm = {
4003 .omap4 = {
4004 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
4005 },
4006 },
4007 .slaves = omap44xx_spinlock_slaves,
4008 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4010};
4011
35d1a66a
BC		 4012/*
4013 * 'timer' class
4014 * general purpose timer module with accurate 1ms tick
4015 * This class contains several variants: ['timer_1ms', 'timer']
4016 */
4017
4018static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4019 .rev_offs = 0x0000,
4020 .sysc_offs = 0x0010,
4021 .syss_offs = 0x0014,
4022 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4023 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4024 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4025 SYSS_HAS_RESET_STATUS),
4026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4027 .sysc_fields = &omap_hwmod_sysc_type1,
4028};
4029
4030static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4031 .name = "timer",
4032 .sysc = &omap44xx_timer_1ms_sysc,
4033};
4034
4035static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4036 .rev_offs = 0x0000,
4037 .sysc_offs = 0x0010,
4038 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4039 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4040 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4041 SIDLE_SMART_WKUP),
4042 .sysc_fields = &omap_hwmod_sysc_type2,
4043};
4044
4045static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4046 .name = "timer",
4047 .sysc = &omap44xx_timer_sysc,
4048};
4049
4050/* timer1 */
4051static struct omap_hwmod omap44xx_timer1_hwmod;
4052static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4053 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
212738a4 4054 { .irq = -1 }
35d1a66a
BC		 4055};
4056
4057static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4058 {
4059 .pa_start = 0x4a318000,
4060 .pa_end = 0x4a31807f,
4061 .flags = ADDR_TYPE_RT
4062 },
78183f3f 4063 { }
35d1a66a
BC		 4064};
4065
4066/* l4_wkup -> timer1 */
4067static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4068 .master = &omap44xx_l4_wkup_hwmod,
4069 .slave = &omap44xx_timer1_hwmod,
4070 .clk = "l4_wkup_clk_mux_ck",
4071 .addr = omap44xx_timer1_addrs,
35d1a66a
BC		 4072 .user = OCP_USER_MPU | OCP_USER_SDMA,
4073};
4074
4075/* timer1 slave ports */
4076static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4077 &omap44xx_l4_wkup__timer1,
4078};
4079
4080static struct omap_hwmod omap44xx_timer1_hwmod = {
4081 .name = "timer1",
4082 .class = &omap44xx_timer_1ms_hwmod_class,
4083 .mpu_irqs = omap44xx_timer1_irqs,
35d1a66a
BC		 4084 .main_clk = "timer1_fck",
4085 .prcm = {
4086 .omap4 = {
4087 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4088 },
4089 },
4090 .slaves = omap44xx_timer1_slaves,
4091 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4092 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4093};
4094
4095/* timer2 */
4096static struct omap_hwmod omap44xx_timer2_hwmod;
4097static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4098 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
212738a4 4099 { .irq = -1 }
35d1a66a
BC		 4100};
4101
4102static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4103 {
4104 .pa_start = 0x48032000,
4105 .pa_end = 0x4803207f,
4106 .flags = ADDR_TYPE_RT
4107 },
78183f3f 4108 { }
35d1a66a
BC		 4109};
4110
4111/* l4_per -> timer2 */
4112static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4113 .master = &omap44xx_l4_per_hwmod,
4114 .slave = &omap44xx_timer2_hwmod,
4115 .clk = "l4_div_ck",
4116 .addr = omap44xx_timer2_addrs,
35d1a66a
BC		 4117 .user = OCP_USER_MPU | OCP_USER_SDMA,
4118};
4119
4120/* timer2 slave ports */
4121static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4122 &omap44xx_l4_per__timer2,
4123};
4124
4125static struct omap_hwmod omap44xx_timer2_hwmod = {
4126 .name = "timer2",
4127 .class = &omap44xx_timer_1ms_hwmod_class,
4128 .mpu_irqs = omap44xx_timer2_irqs,
35d1a66a
BC		 4129 .main_clk = "timer2_fck",
4130 .prcm = {
4131 .omap4 = {
4132 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4133 },
4134 },
4135 .slaves = omap44xx_timer2_slaves,
4136 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4138};
4139
4140/* timer3 */
4141static struct omap_hwmod omap44xx_timer3_hwmod;
4142static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4143 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
212738a4 4144 { .irq = -1 }
35d1a66a
BC		 4145};
4146
4147static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4148 {
4149 .pa_start = 0x48034000,
4150 .pa_end = 0x4803407f,
4151 .flags = ADDR_TYPE_RT
4152 },
78183f3f 4153 { }
35d1a66a
BC		 4154};
4155
4156/* l4_per -> timer3 */
4157static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4158 .master = &omap44xx_l4_per_hwmod,
4159 .slave = &omap44xx_timer3_hwmod,
4160 .clk = "l4_div_ck",
4161 .addr = omap44xx_timer3_addrs,
35d1a66a
BC		 4162 .user = OCP_USER_MPU | OCP_USER_SDMA,
4163};
4164
4165/* timer3 slave ports */
4166static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4167 &omap44xx_l4_per__timer3,
4168};
4169
4170static struct omap_hwmod omap44xx_timer3_hwmod = {
4171 .name = "timer3",
4172 .class = &omap44xx_timer_hwmod_class,
4173 .mpu_irqs = omap44xx_timer3_irqs,
35d1a66a
BC		 4174 .main_clk = "timer3_fck",
4175 .prcm = {
4176 .omap4 = {
4177 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4178 },
4179 },
4180 .slaves = omap44xx_timer3_slaves,
4181 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4183};
4184
4185/* timer4 */
4186static struct omap_hwmod omap44xx_timer4_hwmod;
4187static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4188 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
212738a4 4189 { .irq = -1 }
35d1a66a
BC		 4190};
4191
4192static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4193 {
4194 .pa_start = 0x48036000,
4195 .pa_end = 0x4803607f,
4196 .flags = ADDR_TYPE_RT
4197 },
78183f3f 4198 { }
35d1a66a
BC		 4199};
4200
4201/* l4_per -> timer4 */
4202static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4203 .master = &omap44xx_l4_per_hwmod,
4204 .slave = &omap44xx_timer4_hwmod,
4205 .clk = "l4_div_ck",
4206 .addr = omap44xx_timer4_addrs,
35d1a66a
BC		 4207 .user = OCP_USER_MPU | OCP_USER_SDMA,
4208};
4209
4210/* timer4 slave ports */
4211static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4212 &omap44xx_l4_per__timer4,
4213};
4214
4215static struct omap_hwmod omap44xx_timer4_hwmod = {
4216 .name = "timer4",
4217 .class = &omap44xx_timer_hwmod_class,
4218 .mpu_irqs = omap44xx_timer4_irqs,
35d1a66a
BC		 4219 .main_clk = "timer4_fck",
4220 .prcm = {
4221 .omap4 = {
4222 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4223 },
4224 },
4225 .slaves = omap44xx_timer4_slaves,
4226 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4228};
4229
4230/* timer5 */
4231static struct omap_hwmod omap44xx_timer5_hwmod;
4232static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4233 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
212738a4 4234 { .irq = -1 }
35d1a66a
BC		 4235};
4236
4237static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4238 {
4239 .pa_start = 0x40138000,
4240 .pa_end = 0x4013807f,
4241 .flags = ADDR_TYPE_RT
4242 },
78183f3f 4243 { }
35d1a66a
BC		 4244};
4245
4246/* l4_abe -> timer5 */
4247static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4248 .master = &omap44xx_l4_abe_hwmod,
4249 .slave = &omap44xx_timer5_hwmod,
4250 .clk = "ocp_abe_iclk",
4251 .addr = omap44xx_timer5_addrs,
35d1a66a
BC		 4252 .user = OCP_USER_MPU,
4253};
4254
4255static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4256 {
4257 .pa_start = 0x49038000,
4258 .pa_end = 0x4903807f,
4259 .flags = ADDR_TYPE_RT
4260 },
78183f3f 4261 { }
35d1a66a
BC		 4262};
4263
4264/* l4_abe -> timer5 (dma) */
4265static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4266 .master = &omap44xx_l4_abe_hwmod,
4267 .slave = &omap44xx_timer5_hwmod,
4268 .clk = "ocp_abe_iclk",
4269 .addr = omap44xx_timer5_dma_addrs,
35d1a66a
BC		 4270 .user = OCP_USER_SDMA,
4271};
4272
4273/* timer5 slave ports */
4274static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4275 &omap44xx_l4_abe__timer5,
4276 &omap44xx_l4_abe__timer5_dma,
4277};
4278
4279static struct omap_hwmod omap44xx_timer5_hwmod = {
4280 .name = "timer5",
4281 .class = &omap44xx_timer_hwmod_class,
4282 .mpu_irqs = omap44xx_timer5_irqs,
35d1a66a
BC		 4283 .main_clk = "timer5_fck",
4284 .prcm = {
4285 .omap4 = {
4286 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4287 },
4288 },
4289 .slaves = omap44xx_timer5_slaves,
4290 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4292};
4293
4294/* timer6 */
4295static struct omap_hwmod omap44xx_timer6_hwmod;
4296static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4297 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
212738a4 4298 { .irq = -1 }
35d1a66a
BC		 4299};
4300
4301static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4302 {
4303 .pa_start = 0x4013a000,
4304 .pa_end = 0x4013a07f,
4305 .flags = ADDR_TYPE_RT
4306 },
78183f3f 4307 { }
35d1a66a
BC		 4308};
4309
4310/* l4_abe -> timer6 */
4311static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4312 .master = &omap44xx_l4_abe_hwmod,
4313 .slave = &omap44xx_timer6_hwmod,
4314 .clk = "ocp_abe_iclk",
4315 .addr = omap44xx_timer6_addrs,
35d1a66a
BC		 4316 .user = OCP_USER_MPU,
4317};
4318
4319static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4320 {
4321 .pa_start = 0x4903a000,
4322 .pa_end = 0x4903a07f,
4323 .flags = ADDR_TYPE_RT
4324 },
78183f3f 4325 { }
35d1a66a
BC		 4326};
4327
4328/* l4_abe -> timer6 (dma) */
4329static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4330 .master = &omap44xx_l4_abe_hwmod,
4331 .slave = &omap44xx_timer6_hwmod,
4332 .clk = "ocp_abe_iclk",
4333 .addr = omap44xx_timer6_dma_addrs,
35d1a66a
BC		 4334 .user = OCP_USER_SDMA,
4335};
4336
4337/* timer6 slave ports */
4338static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4339 &omap44xx_l4_abe__timer6,
4340 &omap44xx_l4_abe__timer6_dma,
4341};
4342
4343static struct omap_hwmod omap44xx_timer6_hwmod = {
4344 .name = "timer6",
4345 .class = &omap44xx_timer_hwmod_class,
4346 .mpu_irqs = omap44xx_timer6_irqs,
212738a4 4347
35d1a66a
BC		 4348 .main_clk = "timer6_fck",
4349 .prcm = {
4350 .omap4 = {
4351 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4352 },
4353 },
4354 .slaves = omap44xx_timer6_slaves,
4355 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4357};
4358
4359/* timer7 */
4360static struct omap_hwmod omap44xx_timer7_hwmod;
4361static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4362 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
212738a4 4363 { .irq = -1 }
35d1a66a
BC		 4364};
4365
4366static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4367 {
4368 .pa_start = 0x4013c000,
4369 .pa_end = 0x4013c07f,
4370 .flags = ADDR_TYPE_RT
4371 },
78183f3f 4372 { }
35d1a66a
BC		 4373};
4374
4375/* l4_abe -> timer7 */
4376static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4377 .master = &omap44xx_l4_abe_hwmod,
4378 .slave = &omap44xx_timer7_hwmod,
4379 .clk = "ocp_abe_iclk",
4380 .addr = omap44xx_timer7_addrs,
35d1a66a
BC		 4381 .user = OCP_USER_MPU,
4382};
4383
4384static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4385 {
4386 .pa_start = 0x4903c000,
4387 .pa_end = 0x4903c07f,
4388 .flags = ADDR_TYPE_RT
4389 },
78183f3f 4390 { }
35d1a66a
BC		 4391};
4392
4393/* l4_abe -> timer7 (dma) */
4394static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4395 .master = &omap44xx_l4_abe_hwmod,
4396 .slave = &omap44xx_timer7_hwmod,
4397 .clk = "ocp_abe_iclk",
4398 .addr = omap44xx_timer7_dma_addrs,
35d1a66a
BC		 4399 .user = OCP_USER_SDMA,
4400};
4401
4402/* timer7 slave ports */
4403static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4404 &omap44xx_l4_abe__timer7,
4405 &omap44xx_l4_abe__timer7_dma,
4406};
4407
4408static struct omap_hwmod omap44xx_timer7_hwmod = {
4409 .name = "timer7",
4410 .class = &omap44xx_timer_hwmod_class,
4411 .mpu_irqs = omap44xx_timer7_irqs,
35d1a66a
BC		 4412 .main_clk = "timer7_fck",
4413 .prcm = {
4414 .omap4 = {
4415 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4416 },
4417 },
4418 .slaves = omap44xx_timer7_slaves,
4419 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4420 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4421};
4422
4423/* timer8 */
4424static struct omap_hwmod omap44xx_timer8_hwmod;
4425static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4426 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
212738a4 4427 { .irq = -1 }
35d1a66a
BC		 4428};
4429
4430static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4431 {
4432 .pa_start = 0x4013e000,
4433 .pa_end = 0x4013e07f,
4434 .flags = ADDR_TYPE_RT
4435 },
78183f3f 4436 { }
35d1a66a
BC		 4437};
4438
4439/* l4_abe -> timer8 */
4440static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4441 .master = &omap44xx_l4_abe_hwmod,
4442 .slave = &omap44xx_timer8_hwmod,
4443 .clk = "ocp_abe_iclk",
4444 .addr = omap44xx_timer8_addrs,
35d1a66a
BC		 4445 .user = OCP_USER_MPU,
4446};
4447
4448static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4449 {
4450 .pa_start = 0x4903e000,
4451 .pa_end = 0x4903e07f,
4452 .flags = ADDR_TYPE_RT
4453 },
78183f3f 4454 { }
35d1a66a
BC		 4455};
4456
4457/* l4_abe -> timer8 (dma) */
4458static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4459 .master = &omap44xx_l4_abe_hwmod,
4460 .slave = &omap44xx_timer8_hwmod,
4461 .clk = "ocp_abe_iclk",
4462 .addr = omap44xx_timer8_dma_addrs,
35d1a66a
BC		 4463 .user = OCP_USER_SDMA,
4464};
4465
4466/* timer8 slave ports */
4467static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4468 &omap44xx_l4_abe__timer8,
4469 &omap44xx_l4_abe__timer8_dma,
4470};
4471
4472static struct omap_hwmod omap44xx_timer8_hwmod = {
4473 .name = "timer8",
4474 .class = &omap44xx_timer_hwmod_class,
4475 .mpu_irqs = omap44xx_timer8_irqs,
35d1a66a
BC		 4476 .main_clk = "timer8_fck",
4477 .prcm = {
4478 .omap4 = {
4479 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4480 },
4481 },
4482 .slaves = omap44xx_timer8_slaves,
4483 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4484 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4485};
4486
4487/* timer9 */
4488static struct omap_hwmod omap44xx_timer9_hwmod;
4489static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4490 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
212738a4 4491 { .irq = -1 }
35d1a66a
BC		 4492};
4493
4494static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4495 {
4496 .pa_start = 0x4803e000,
4497 .pa_end = 0x4803e07f,
4498 .flags = ADDR_TYPE_RT
4499 },
78183f3f 4500 { }
35d1a66a
BC		 4501};
4502
4503/* l4_per -> timer9 */
4504static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4505 .master = &omap44xx_l4_per_hwmod,
4506 .slave = &omap44xx_timer9_hwmod,
4507 .clk = "l4_div_ck",
4508 .addr = omap44xx_timer9_addrs,
35d1a66a
BC		 4509 .user = OCP_USER_MPU | OCP_USER_SDMA,
4510};
4511
4512/* timer9 slave ports */
4513static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4514 &omap44xx_l4_per__timer9,
4515};
4516
4517static struct omap_hwmod omap44xx_timer9_hwmod = {
4518 .name = "timer9",
4519 .class = &omap44xx_timer_hwmod_class,
4520 .mpu_irqs = omap44xx_timer9_irqs,
35d1a66a
BC		 4521 .main_clk = "timer9_fck",
4522 .prcm = {
4523 .omap4 = {
4524 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4525 },
4526 },
4527 .slaves = omap44xx_timer9_slaves,
4528 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4530};
4531
4532/* timer10 */
4533static struct omap_hwmod omap44xx_timer10_hwmod;
4534static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4535 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
212738a4 4536 { .irq = -1 }
35d1a66a
BC		 4537};
4538
4539static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4540 {
4541 .pa_start = 0x48086000,
4542 .pa_end = 0x4808607f,
4543 .flags = ADDR_TYPE_RT
4544 },
78183f3f 4545 { }
35d1a66a
BC		 4546};
4547
4548/* l4_per -> timer10 */
4549static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4550 .master = &omap44xx_l4_per_hwmod,
4551 .slave = &omap44xx_timer10_hwmod,
4552 .clk = "l4_div_ck",
4553 .addr = omap44xx_timer10_addrs,
35d1a66a
BC		 4554 .user = OCP_USER_MPU | OCP_USER_SDMA,
4555};
4556
4557/* timer10 slave ports */
4558static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4559 &omap44xx_l4_per__timer10,
4560};
4561
4562static struct omap_hwmod omap44xx_timer10_hwmod = {
4563 .name = "timer10",
4564 .class = &omap44xx_timer_1ms_hwmod_class,
4565 .mpu_irqs = omap44xx_timer10_irqs,
35d1a66a
BC		 4566 .main_clk = "timer10_fck",
4567 .prcm = {
4568 .omap4 = {
4569 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4570 },
4571 },
4572 .slaves = omap44xx_timer10_slaves,
4573 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4575};
4576
4577/* timer11 */
4578static struct omap_hwmod omap44xx_timer11_hwmod;
4579static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4580 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
212738a4 4581 { .irq = -1 }
35d1a66a
BC		 4582};
4583
4584static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4585 {
4586 .pa_start = 0x48088000,
4587 .pa_end = 0x4808807f,
4588 .flags = ADDR_TYPE_RT
4589 },
78183f3f 4590 { }
35d1a66a
BC		 4591};
4592
4593/* l4_per -> timer11 */
4594static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4595 .master = &omap44xx_l4_per_hwmod,
4596 .slave = &omap44xx_timer11_hwmod,
4597 .clk = "l4_div_ck",
4598 .addr = omap44xx_timer11_addrs,
35d1a66a
BC		 4599 .user = OCP_USER_MPU | OCP_USER_SDMA,
4600};
4601
4602/* timer11 slave ports */
4603static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4604 &omap44xx_l4_per__timer11,
4605};
4606
4607static struct omap_hwmod omap44xx_timer11_hwmod = {
4608 .name = "timer11",
4609 .class = &omap44xx_timer_hwmod_class,
4610 .mpu_irqs = omap44xx_timer11_irqs,
35d1a66a
BC		 4611 .main_clk = "timer11_fck",
4612 .prcm = {
4613 .omap4 = {
4614 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4615 },
4616 },
4617 .slaves = omap44xx_timer11_slaves,
4618 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4619 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4620};
4621
9780a9cf 4622/*
3b54baad
BC		 4623 * 'uart' class
4624 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4625 */
4626
3b54baad
BC		 4627static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4628 .rev_offs = 0x0050,
4629 .sysc_offs = 0x0054,
4630 .syss_offs = 0x0058,
4631 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4632 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4633 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4634 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4635 SIDLE_SMART_WKUP),
9780a9cf
BC		 4636 .sysc_fields = &omap_hwmod_sysc_type1,
4637};
4638
3b54baad 4639static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4640 .name = "uart",
4641 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4642};
4643
3b54baad
BC		 4644/* uart1 */
4645static struct omap_hwmod omap44xx_uart1_hwmod;
4646static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4647 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
212738a4 4648 { .irq = -1 }
9780a9cf
BC		 4649};
4650
3b54baad
BC		 4651static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4652 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4653 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
bc614958 4654 { .dma_req = -1 }
9780a9cf
BC		 4655};
4656
3b54baad 4657static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4658 {
3b54baad
BC		 4659 .pa_start = 0x4806a000,
4660 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4661 .flags = ADDR_TYPE_RT
4662 },
78183f3f 4663 { }
9780a9cf
BC		 4664};
4665
3b54baad
BC		 4666/* l4_per -> uart1 */
4667static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4668 .master = &omap44xx_l4_per_hwmod,
4669 .slave = &omap44xx_uart1_hwmod,
4670 .clk = "l4_div_ck",
4671 .addr = omap44xx_uart1_addrs,
9780a9cf
BC		 4672 .user = OCP_USER_MPU | OCP_USER_SDMA,
4673};
4674
3b54baad
BC		 4675/* uart1 slave ports */
4676static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4677 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4678};
4679
3b54baad
BC		 4680static struct omap_hwmod omap44xx_uart1_hwmod = {
4681 .name = "uart1",
4682 .class = &omap44xx_uart_hwmod_class,
4683 .mpu_irqs = omap44xx_uart1_irqs,
3b54baad 4684 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3b54baad 4685 .main_clk = "uart1_fck",
9780a9cf
BC		 4686 .prcm = {
4687 .omap4 = {
3b54baad 4688 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 4689 },
4690 },
3b54baad
BC		 4691 .slaves = omap44xx_uart1_slaves,
4692 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4693 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4694};
4695
3b54baad
BC		 4696/* uart2 */
4697static struct omap_hwmod omap44xx_uart2_hwmod;
4698static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4699 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
212738a4 4700 { .irq = -1 }
9780a9cf
BC		 4701};
4702
3b54baad
BC		 4703static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4704 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4705 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
bc614958 4706 { .dma_req = -1 }
3b54baad
BC		 4707};
4708
4709static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4710 {
3b54baad
BC		 4711 .pa_start = 0x4806c000,
4712 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4713 .flags = ADDR_TYPE_RT
4714 },
78183f3f 4715 { }
9780a9cf
BC		 4716};
4717
3b54baad
BC		 4718/* l4_per -> uart2 */
4719static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4720 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4721 .slave = &omap44xx_uart2_hwmod,
4722 .clk = "l4_div_ck",
4723 .addr = omap44xx_uart2_addrs,
9780a9cf
BC		 4724 .user = OCP_USER_MPU | OCP_USER_SDMA,
4725};
4726
3b54baad
BC		 4727/* uart2 slave ports */
4728static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4729 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4730};
4731
3b54baad
BC		 4732static struct omap_hwmod omap44xx_uart2_hwmod = {
4733 .name = "uart2",
4734 .class = &omap44xx_uart_hwmod_class,
4735 .mpu_irqs = omap44xx_uart2_irqs,
3b54baad 4736 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3b54baad 4737 .main_clk = "uart2_fck",
9780a9cf
BC		 4738 .prcm = {
4739 .omap4 = {
3b54baad 4740 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 4741 },
4742 },
3b54baad
BC		 4743 .slaves = omap44xx_uart2_slaves,
4744 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4745 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4746};
4747
3b54baad
BC		 4748/* uart3 */
4749static struct omap_hwmod omap44xx_uart3_hwmod;
4750static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4751 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
212738a4 4752 { .irq = -1 }
9780a9cf
BC		 4753};
4754
3b54baad
BC		 4755static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4756 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4757 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
bc614958 4758 { .dma_req = -1 }
3b54baad
BC		 4759};
4760
4761static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4762 {
3b54baad
BC		 4763 .pa_start = 0x48020000,
4764 .pa_end = 0x480200ff,
9780a9cf
BC		 4765 .flags = ADDR_TYPE_RT
4766 },
78183f3f 4767 { }
9780a9cf
BC		 4768};
4769
3b54baad
BC		 4770/* l4_per -> uart3 */
4771static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4772 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4773 .slave = &omap44xx_uart3_hwmod,
4774 .clk = "l4_div_ck",
4775 .addr = omap44xx_uart3_addrs,
9780a9cf
BC		 4776 .user = OCP_USER_MPU | OCP_USER_SDMA,
4777};
4778
3b54baad
BC		 4779/* uart3 slave ports */
4780static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4781 &omap44xx_l4_per__uart3,
4782};
4783
4784static struct omap_hwmod omap44xx_uart3_hwmod = {
4785 .name = "uart3",
4786 .class = &omap44xx_uart_hwmod_class,
7ecc5373 4787 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 4788 .mpu_irqs = omap44xx_uart3_irqs,
3b54baad 4789 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3b54baad 4790 .main_clk = "uart3_fck",
9780a9cf
BC		 4791 .prcm = {
4792 .omap4 = {
3b54baad 4793 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 4794 },
4795 },
3b54baad
BC		 4796 .slaves = omap44xx_uart3_slaves,
4797 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4798 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4799};
4800
3b54baad
BC		 4801/* uart4 */
4802static struct omap_hwmod omap44xx_uart4_hwmod;
4803static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4804 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
212738a4 4805 { .irq = -1 }
9780a9cf
BC		 4806};
4807
3b54baad
BC		 4808static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4809 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4810 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
bc614958 4811 { .dma_req = -1 }
3b54baad
BC		 4812};
4813
4814static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4815 {
3b54baad
BC		 4816 .pa_start = 0x4806e000,
4817 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4818 .flags = ADDR_TYPE_RT
4819 },
78183f3f 4820 { }
9780a9cf
BC		 4821};
4822
3b54baad
BC		 4823/* l4_per -> uart4 */
4824static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4825 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4826 .slave = &omap44xx_uart4_hwmod,
4827 .clk = "l4_div_ck",
4828 .addr = omap44xx_uart4_addrs,
9780a9cf
BC		 4829 .user = OCP_USER_MPU | OCP_USER_SDMA,
4830};
4831
3b54baad
BC		 4832/* uart4 slave ports */
4833static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4834 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4835};
4836
3b54baad
BC		 4837static struct omap_hwmod omap44xx_uart4_hwmod = {
4838 .name = "uart4",
4839 .class = &omap44xx_uart_hwmod_class,
4840 .mpu_irqs = omap44xx_uart4_irqs,
3b54baad 4841 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3b54baad 4842 .main_clk = "uart4_fck",
9780a9cf
BC		 4843 .prcm = {
4844 .omap4 = {
3b54baad 4845 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 4846 },
4847 },
3b54baad
BC		 4848 .slaves = omap44xx_uart4_slaves,
4849 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4850 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4851};
4852
5844c4ea
BC		 4853/*
4854 * 'usb_otg_hs' class
4855 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4856 */
4857
4858static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4859 .rev_offs = 0x0400,
4860 .sysc_offs = 0x0404,
4861 .syss_offs = 0x0408,
4862 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4863 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4864 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4865 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4866 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4867 MSTANDBY_SMART),
4868 .sysc_fields = &omap_hwmod_sysc_type1,
4869};
4870
4871static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
00fe610b
BC		 4872 .name = "usb_otg_hs",
4873 .sysc = &omap44xx_usb_otg_hs_sysc,
5844c4ea
BC		 4874};
4875
4876/* usb_otg_hs */
4877static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4878 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4879 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
212738a4 4880 { .irq = -1 }
5844c4ea
BC		 4881};
4882
4883/* usb_otg_hs master ports */
4884static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4885 &omap44xx_usb_otg_hs__l3_main_2,
4886};
4887
4888static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4889 {
4890 .pa_start = 0x4a0ab000,
4891 .pa_end = 0x4a0ab003,
4892 .flags = ADDR_TYPE_RT
4893 },
78183f3f 4894 { }
5844c4ea
BC		 4895};
4896
4897/* l4_cfg -> usb_otg_hs */
4898static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4899 .master = &omap44xx_l4_cfg_hwmod,
4900 .slave = &omap44xx_usb_otg_hs_hwmod,
4901 .clk = "l4_div_ck",
4902 .addr = omap44xx_usb_otg_hs_addrs,
5844c4ea
BC		 4903 .user = OCP_USER_MPU | OCP_USER_SDMA,
4904};
4905
4906/* usb_otg_hs slave ports */
4907static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4908 &omap44xx_l4_cfg__usb_otg_hs,
4909};
4910
4911static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4912 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4913};
4914
4915static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4916 .name = "usb_otg_hs",
4917 .class = &omap44xx_usb_otg_hs_hwmod_class,
4918 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4919 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5844c4ea
BC		 4920 .main_clk = "usb_otg_hs_ick",
4921 .prcm = {
4922 .omap4 = {
4923 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4924 },
4925 },
4926 .opt_clks = usb_otg_hs_opt_clks,
00fe610b 4927 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5844c4ea
BC		 4928 .slaves = omap44xx_usb_otg_hs_slaves,
4929 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4930 .masters = omap44xx_usb_otg_hs_masters,
4931 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4932 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4933};
4934
3b54baad
BC		 4935/*
4936 * 'wd_timer' class
4937 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4938 * overflow condition
4939 */
4940
4941static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4942 .rev_offs = 0x0000,
4943 .sysc_offs = 0x0010,
4944 .syss_offs = 0x0014,
4945 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 4946 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4947 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4948 SIDLE_SMART_WKUP),
3b54baad 4949 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 4950};
4951
3b54baad
BC		 4952static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4953 .name = "wd_timer",
4954 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 4955 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 4956};
4957
4958/* wd_timer2 */
4959static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4960static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4961 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
212738a4 4962 { .irq = -1 }
3b54baad
BC		 4963};
4964
4965static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 4966 {
3b54baad
BC		 4967 .pa_start = 0x4a314000,
4968 .pa_end = 0x4a31407f,
9780a9cf
BC		 4969 .flags = ADDR_TYPE_RT
4970 },
78183f3f 4971 { }
9780a9cf
BC		 4972};
4973
3b54baad
BC		 4974/* l4_wkup -> wd_timer2 */
4975static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4976 .master = &omap44xx_l4_wkup_hwmod,
4977 .slave = &omap44xx_wd_timer2_hwmod,
4978 .clk = "l4_wkup_clk_mux_ck",
4979 .addr = omap44xx_wd_timer2_addrs,
9780a9cf
BC		 4980 .user = OCP_USER_MPU | OCP_USER_SDMA,
4981};
4982
3b54baad
BC		 4983/* wd_timer2 slave ports */
4984static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4985 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 4986};
4987
3b54baad
BC		 4988static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4989 .name = "wd_timer2",
4990 .class = &omap44xx_wd_timer_hwmod_class,
4991 .mpu_irqs = omap44xx_wd_timer2_irqs,
3b54baad 4992 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 4993 .prcm = {
4994 .omap4 = {
3b54baad 4995 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 4996 },
4997 },
3b54baad
BC		 4998 .slaves = omap44xx_wd_timer2_slaves,
4999 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 5000 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5001};
5002
3b54baad
BC		 5003/* wd_timer3 */
5004static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5005static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5006 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
212738a4 5007 { .irq = -1 }
9780a9cf
BC		 5008};
5009
3b54baad 5010static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 5011 {
3b54baad
BC		 5012 .pa_start = 0x40130000,
5013 .pa_end = 0x4013007f,
9780a9cf
BC		 5014 .flags = ADDR_TYPE_RT
5015 },
78183f3f 5016 { }
9780a9cf
BC		 5017};
5018
3b54baad
BC		 5019/* l4_abe -> wd_timer3 */
5020static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5021 .master = &omap44xx_l4_abe_hwmod,
5022 .slave = &omap44xx_wd_timer3_hwmod,
5023 .clk = "ocp_abe_iclk",
5024 .addr = omap44xx_wd_timer3_addrs,
3b54baad 5025 .user = OCP_USER_MPU,
9780a9cf
BC		 5026};
5027
3b54baad
BC		 5028static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5029 {
5030 .pa_start = 0x49030000,
5031 .pa_end = 0x4903007f,
5032 .flags = ADDR_TYPE_RT
5033 },
78183f3f 5034 { }
9780a9cf
BC		 5035};
5036
3b54baad
BC		 5037/* l4_abe -> wd_timer3 (dma) */
5038static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5039 .master = &omap44xx_l4_abe_hwmod,
5040 .slave = &omap44xx_wd_timer3_hwmod,
5041 .clk = "ocp_abe_iclk",
5042 .addr = omap44xx_wd_timer3_dma_addrs,
3b54baad 5043 .user = OCP_USER_SDMA,
9780a9cf
BC		 5044};
5045
3b54baad
BC		 5046/* wd_timer3 slave ports */
5047static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5048 &omap44xx_l4_abe__wd_timer3,
5049 &omap44xx_l4_abe__wd_timer3_dma,
5050};
5051
5052static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5053 .name = "wd_timer3",
5054 .class = &omap44xx_wd_timer_hwmod_class,
5055 .mpu_irqs = omap44xx_wd_timer3_irqs,
3b54baad 5056 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 5057 .prcm = {
5058 .omap4 = {
3b54baad 5059 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 5060 },
5061 },
3b54baad
BC		 5062 .slaves = omap44xx_wd_timer3_slaves,
5063 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 5064 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5065};
531ce0d5 5066
55d2cb08 5067static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 5068
55d2cb08
BC		 5069 /* dmm class */
5070 &omap44xx_dmm_hwmod,
3b54baad 5071
55d2cb08
BC		 5072 /* emif_fw class */
5073 &omap44xx_emif_fw_hwmod,
3b54baad 5074
55d2cb08
BC		 5075 /* l3 class */
5076 &omap44xx_l3_instr_hwmod,
5077 &omap44xx_l3_main_1_hwmod,
5078 &omap44xx_l3_main_2_hwmod,
5079 &omap44xx_l3_main_3_hwmod,
3b54baad 5080
55d2cb08
BC		 5081 /* l4 class */
5082 &omap44xx_l4_abe_hwmod,
5083 &omap44xx_l4_cfg_hwmod,
5084 &omap44xx_l4_per_hwmod,
5085 &omap44xx_l4_wkup_hwmod,
531ce0d5 5086
55d2cb08
BC		 5087 /* mpu_bus class */
5088 &omap44xx_mpu_private_hwmod,
5089
407a6888
BC		 5090 /* aess class */
5091/* &omap44xx_aess_hwmod, */
5092
5093 /* bandgap class */
5094 &omap44xx_bandgap_hwmod,
5095
5096 /* counter class */
5097/* &omap44xx_counter_32k_hwmod, */
5098
d7cf5f33
BC		 5099 /* dma class */
5100 &omap44xx_dma_system_hwmod,
5101
8ca476da
BC		 5102 /* dmic class */
5103 &omap44xx_dmic_hwmod,
5104
8f25bdc5
BC		 5105 /* dsp class */
5106 &omap44xx_dsp_hwmod,
5107 &omap44xx_dsp_c0_hwmod,
5108
d63bd74f
BC		 5109 /* dss class */
5110 &omap44xx_dss_hwmod,
5111 &omap44xx_dss_dispc_hwmod,
5112 &omap44xx_dss_dsi1_hwmod,
5113 &omap44xx_dss_dsi2_hwmod,
5114 &omap44xx_dss_hdmi_hwmod,
5115 &omap44xx_dss_rfbi_hwmod,
5116 &omap44xx_dss_venc_hwmod,
5117
9780a9cf
BC		 5118 /* gpio class */
5119 &omap44xx_gpio1_hwmod,
5120 &omap44xx_gpio2_hwmod,
5121 &omap44xx_gpio3_hwmod,
5122 &omap44xx_gpio4_hwmod,
5123 &omap44xx_gpio5_hwmod,
5124 &omap44xx_gpio6_hwmod,
5125
407a6888
BC		 5126 /* hsi class */
5127/* &omap44xx_hsi_hwmod, */
5128
3b54baad
BC		 5129 /* i2c class */
5130 &omap44xx_i2c1_hwmod,
5131 &omap44xx_i2c2_hwmod,
5132 &omap44xx_i2c3_hwmod,
5133 &omap44xx_i2c4_hwmod,
5134
407a6888
BC		 5135 /* ipu class */
5136 &omap44xx_ipu_hwmod,
5137 &omap44xx_ipu_c0_hwmod,
5138 &omap44xx_ipu_c1_hwmod,
5139
5140 /* iss class */
5141/* &omap44xx_iss_hwmod, */
5142
8f25bdc5
BC		 5143 /* iva class */
5144 &omap44xx_iva_hwmod,
5145 &omap44xx_iva_seq0_hwmod,
5146 &omap44xx_iva_seq1_hwmod,
5147
407a6888 5148 /* kbd class */
4998b245 5149 &omap44xx_kbd_hwmod,
407a6888 5150
ec5df927
BC		 5151 /* mailbox class */
5152 &omap44xx_mailbox_hwmod,
5153
4ddff493
BC		 5154 /* mcbsp class */
5155 &omap44xx_mcbsp1_hwmod,
5156 &omap44xx_mcbsp2_hwmod,
5157 &omap44xx_mcbsp3_hwmod,
5158 &omap44xx_mcbsp4_hwmod,
5159
407a6888
BC		 5160 /* mcpdm class */
5161/* &omap44xx_mcpdm_hwmod, */
5162
9bcbd7f0
BC		 5163 /* mcspi class */
5164 &omap44xx_mcspi1_hwmod,
5165 &omap44xx_mcspi2_hwmod,
5166 &omap44xx_mcspi3_hwmod,
5167 &omap44xx_mcspi4_hwmod,
5168
407a6888 5169 /* mmc class */
17203bda
AG		 5170 &omap44xx_mmc1_hwmod,
5171 &omap44xx_mmc2_hwmod,
5172 &omap44xx_mmc3_hwmod,
5173 &omap44xx_mmc4_hwmod,
5174 &omap44xx_mmc5_hwmod,
407a6888 5175
55d2cb08
BC		 5176 /* mpu class */
5177 &omap44xx_mpu_hwmod,
db12ba53 5178
1f6a717f
BC		 5179 /* smartreflex class */
5180 &omap44xx_smartreflex_core_hwmod,
5181 &omap44xx_smartreflex_iva_hwmod,
5182 &omap44xx_smartreflex_mpu_hwmod,
5183
d11c217f
BC		 5184 /* spinlock class */
5185 &omap44xx_spinlock_hwmod,
5186
35d1a66a
BC		 5187 /* timer class */
5188 &omap44xx_timer1_hwmod,
5189 &omap44xx_timer2_hwmod,
5190 &omap44xx_timer3_hwmod,
5191 &omap44xx_timer4_hwmod,
5192 &omap44xx_timer5_hwmod,
5193 &omap44xx_timer6_hwmod,
5194 &omap44xx_timer7_hwmod,
5195 &omap44xx_timer8_hwmod,
5196 &omap44xx_timer9_hwmod,
5197 &omap44xx_timer10_hwmod,
5198 &omap44xx_timer11_hwmod,
5199
db12ba53
BC		 5200 /* uart class */
5201 &omap44xx_uart1_hwmod,
5202 &omap44xx_uart2_hwmod,
5203 &omap44xx_uart3_hwmod,
5204 &omap44xx_uart4_hwmod,
3b54baad 5205
5844c4ea
BC		 5206 /* usb_otg_hs class */
5207 &omap44xx_usb_otg_hs_hwmod,
5208
3b54baad
BC		 5209 /* wd_timer class */
5210 &omap44xx_wd_timer2_hwmod,
5211 &omap44xx_wd_timer3_hwmod,
5212
55d2cb08
BC		 5213 NULL,
5214};
5215
5216int __init omap44xx_hwmod_init(void)
5217{
550c8092 5218 return omap_hwmod_register(omap44xx_hwmods);
55d2cb08
BC		 5219}
5220
Linux 6.x block layer and io_uring tree(s)