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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
b86aeafc | 17 | #include <linux/power/smartreflex.h> |
4b25408f | 18 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 19 | |
7359154e | 20 | #include <plat/omap_hwmod.h> |
7359154e | 21 | #include <plat/dma.h> |
046465b7 | 22 | #include <plat/serial.h> |
e04d9e1e | 23 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
24 | #include <plat/l4_3xxx.h> |
25 | #include <plat/i2c.h> | |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
5486474c | 30 | #include <plat/iommu.h> |
7359154e | 31 | |
7d7e1eba TL |
32 | #include <mach/am35xx.h> |
33 | ||
dbc04161 | 34 | #include "soc.h" |
43b40992 | 35 | #include "omap_hwmod_common_data.h" |
7359154e | 36 | #include "prm-regbits-34xx.h" |
6b667f88 | 37 | #include "cm-regbits-34xx.h" |
ff2516fb | 38 | #include "wd_timer.h" |
7359154e PW |
39 | |
40 | /* | |
41 | * OMAP3xxx hardware module integration data | |
42 | * | |
844a3b63 | 43 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
44 | * TI hardware database or other technical documentation. Data that |
45 | * is driver-specific or driver-kernel integration-specific belongs | |
46 | * elsewhere. | |
47 | */ | |
48 | ||
844a3b63 PW |
49 | /* |
50 | * IP blocks | |
51 | */ | |
7359154e | 52 | |
844a3b63 | 53 | /* L3 */ |
4bb194dc | 54 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
7d7e1eba TL |
55 | { .irq = 9 + OMAP_INTC_START, }, |
56 | { .irq = 10 + OMAP_INTC_START, }, | |
57 | { .irq = -1 }, | |
4bb194dc | 58 | }; |
59 | ||
4a7cf90a | 60 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 61 | .name = "l3_main", |
43b40992 | 62 | .class = &l3_hwmod_class, |
0d619a89 | 63 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 64 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
65 | }; |
66 | ||
844a3b63 PW |
67 | /* L4 CORE */ |
68 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
69 | .name = "l4_core", | |
70 | .class = &l4_hwmod_class, | |
71 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 72 | }; |
7359154e | 73 | |
844a3b63 PW |
74 | /* L4 PER */ |
75 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
76 | .name = "l4_per", | |
77 | .class = &l4_hwmod_class, | |
78 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 79 | }; |
844a3b63 PW |
80 | |
81 | /* L4 WKUP */ | |
82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
83 | .name = "l4_wkup", | |
84 | .class = &l4_hwmod_class, | |
85 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
86 | }; |
87 | ||
844a3b63 PW |
88 | /* L4 SEC */ |
89 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
90 | .name = "l4_sec", | |
91 | .class = &l4_hwmod_class, | |
92 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
93 | }; |
94 | ||
844a3b63 PW |
95 | /* MPU */ |
96 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
97 | .name = "mpu", | |
98 | .class = &mpu_hwmod_class, | |
99 | .main_clk = "arm_fck", | |
b163605e PW |
100 | }; |
101 | ||
844a3b63 | 102 | /* IVA2 (IVA2) */ |
f42c5496 | 103 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
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104 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
105 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
106 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
107 | }; |
108 | ||
844a3b63 PW |
109 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
110 | .name = "iva", | |
111 | .class = &iva_hwmod_class, | |
f42c5496 PW |
112 | .clkdm_name = "iva2_clkdm", |
113 | .rst_lines = omap3xxx_iva_resets, | |
114 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
115 | .main_clk = "iva2_ck", | |
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116 | .prcm = { |
117 | .omap2 = { | |
118 | .module_offs = OMAP3430_IVA2_MOD, | |
119 | .prcm_reg_id = 1, | |
120 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
121 | .idlest_reg_id = 1, | |
122 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
123 | } | |
124 | }, | |
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125 | }; |
126 | ||
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127 | /* timer class */ |
128 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
129 | .rev_offs = 0x0000, | |
130 | .sysc_offs = 0x0010, | |
131 | .syss_offs = 0x0014, | |
132 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
133 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
134 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
135 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
136 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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137 | }; |
138 | ||
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139 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
140 | .name = "timer", | |
141 | .sysc = &omap3xxx_timer_1ms_sysc, | |
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142 | }; |
143 | ||
844a3b63 PW |
144 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
145 | .rev_offs = 0x0000, | |
146 | .sysc_offs = 0x0010, | |
147 | .syss_offs = 0x0014, | |
148 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
149 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
150 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
151 | .sysc_fields = &omap_hwmod_sysc_type1, | |
b163605e PW |
152 | }; |
153 | ||
844a3b63 PW |
154 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
155 | .name = "timer", | |
156 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
157 | }; |
158 | ||
844a3b63 PW |
159 | /* secure timers dev attribute */ |
160 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 161 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
162 | }; |
163 | ||
844a3b63 PW |
164 | /* always-on timers dev attribute */ |
165 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
166 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
167 | }; |
168 | ||
844a3b63 PW |
169 | /* pwm timers dev attribute */ |
170 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
171 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
172 | }; |
173 | ||
5c3e4ec4 JH |
174 | /* timers with DSP interrupt dev attribute */ |
175 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
176 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
177 | }; | |
178 | ||
179 | /* pwm timers with DSP interrupt dev attribute */ | |
180 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
181 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
182 | }; | |
183 | ||
844a3b63 PW |
184 | /* timer1 */ |
185 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
186 | .name = "timer1", | |
187 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
188 | .main_clk = "gpt1_fck", | |
189 | .prcm = { | |
190 | .omap2 = { | |
191 | .prcm_reg_id = 1, | |
192 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
193 | .module_offs = WKUP_MOD, | |
194 | .idlest_reg_id = 1, | |
195 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
196 | }, | |
046465b7 | 197 | }, |
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198 | .dev_attr = &capability_alwon_dev_attr, |
199 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
200 | }; |
201 | ||
844a3b63 PW |
202 | /* timer2 */ |
203 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
204 | .name = "timer2", | |
205 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
206 | .main_clk = "gpt2_fck", | |
207 | .prcm = { | |
208 | .omap2 = { | |
209 | .prcm_reg_id = 1, | |
210 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
211 | .module_offs = OMAP3430_PER_MOD, | |
212 | .idlest_reg_id = 1, | |
213 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
214 | }, | |
215 | }, | |
844a3b63 | 216 | .class = &omap3xxx_timer_1ms_hwmod_class, |
046465b7 KH |
217 | }; |
218 | ||
844a3b63 PW |
219 | /* timer3 */ |
220 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
221 | .name = "timer3", | |
222 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
223 | .main_clk = "gpt3_fck", | |
224 | .prcm = { | |
225 | .omap2 = { | |
226 | .prcm_reg_id = 1, | |
227 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
228 | .module_offs = OMAP3430_PER_MOD, | |
229 | .idlest_reg_id = 1, | |
230 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
231 | }, | |
232 | }, | |
844a3b63 | 233 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
234 | }; |
235 | ||
844a3b63 PW |
236 | /* timer4 */ |
237 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
238 | .name = "timer4", | |
239 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
240 | .main_clk = "gpt4_fck", | |
241 | .prcm = { | |
242 | .omap2 = { | |
243 | .prcm_reg_id = 1, | |
244 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
245 | .module_offs = OMAP3430_PER_MOD, | |
246 | .idlest_reg_id = 1, | |
247 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
248 | }, | |
249 | }, | |
844a3b63 | 250 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
251 | }; |
252 | ||
844a3b63 PW |
253 | /* timer5 */ |
254 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
255 | .name = "timer5", | |
256 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
257 | .main_clk = "gpt5_fck", | |
258 | .prcm = { | |
259 | .omap2 = { | |
260 | .prcm_reg_id = 1, | |
261 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
262 | .module_offs = OMAP3430_PER_MOD, | |
263 | .idlest_reg_id = 1, | |
264 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
265 | }, | |
4bf90f65 | 266 | }, |
5c3e4ec4 | 267 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 268 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
269 | }; |
270 | ||
844a3b63 PW |
271 | /* timer6 */ |
272 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
273 | .name = "timer6", | |
274 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
275 | .main_clk = "gpt6_fck", | |
276 | .prcm = { | |
277 | .omap2 = { | |
278 | .prcm_reg_id = 1, | |
279 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
280 | .module_offs = OMAP3430_PER_MOD, | |
281 | .idlest_reg_id = 1, | |
282 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
283 | }, | |
284 | }, | |
5c3e4ec4 | 285 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 286 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
287 | }; |
288 | ||
844a3b63 PW |
289 | /* timer7 */ |
290 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
291 | .name = "timer7", | |
292 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
293 | .main_clk = "gpt7_fck", | |
294 | .prcm = { | |
4fe20e97 | 295 | .omap2 = { |
844a3b63 PW |
296 | .prcm_reg_id = 1, |
297 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
298 | .module_offs = OMAP3430_PER_MOD, | |
299 | .idlest_reg_id = 1, | |
300 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
301 | }, | |
4fe20e97 | 302 | }, |
5c3e4ec4 | 303 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 304 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
305 | }; |
306 | ||
844a3b63 PW |
307 | /* timer8 */ |
308 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
309 | .name = "timer8", | |
310 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
311 | .main_clk = "gpt8_fck", | |
312 | .prcm = { | |
4fe20e97 | 313 | .omap2 = { |
844a3b63 PW |
314 | .prcm_reg_id = 1, |
315 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
316 | .module_offs = OMAP3430_PER_MOD, | |
317 | .idlest_reg_id = 1, | |
318 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
319 | }, | |
4fe20e97 | 320 | }, |
5c3e4ec4 | 321 | .dev_attr = &capability_dsp_pwm_dev_attr, |
844a3b63 | 322 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
323 | }; |
324 | ||
844a3b63 PW |
325 | /* timer9 */ |
326 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
327 | .name = "timer9", | |
328 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
329 | .main_clk = "gpt9_fck", | |
330 | .prcm = { | |
331 | .omap2 = { | |
332 | .prcm_reg_id = 1, | |
333 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
334 | .module_offs = OMAP3430_PER_MOD, | |
335 | .idlest_reg_id = 1, | |
336 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
337 | }, | |
4fe20e97 | 338 | }, |
844a3b63 PW |
339 | .dev_attr = &capability_pwm_dev_attr, |
340 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
341 | }; |
342 | ||
844a3b63 PW |
343 | /* timer10 */ |
344 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
345 | .name = "timer10", | |
346 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
347 | .main_clk = "gpt10_fck", | |
348 | .prcm = { | |
4fe20e97 | 349 | .omap2 = { |
844a3b63 PW |
350 | .prcm_reg_id = 1, |
351 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
352 | .module_offs = CORE_MOD, | |
353 | .idlest_reg_id = 1, | |
354 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
355 | }, | |
4fe20e97 | 356 | }, |
844a3b63 PW |
357 | .dev_attr = &capability_pwm_dev_attr, |
358 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
359 | }; |
360 | ||
844a3b63 PW |
361 | /* timer11 */ |
362 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
363 | .name = "timer11", | |
364 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
365 | .main_clk = "gpt11_fck", | |
366 | .prcm = { | |
367 | .omap2 = { | |
368 | .prcm_reg_id = 1, | |
369 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
370 | .module_offs = CORE_MOD, | |
371 | .idlest_reg_id = 1, | |
372 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
373 | }, | |
374 | }, | |
375 | .dev_attr = &capability_pwm_dev_attr, | |
376 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
377 | }; |
378 | ||
844a3b63 PW |
379 | /* timer12 */ |
380 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
7d7e1eba TL |
381 | { .irq = 95 + OMAP_INTC_START, }, |
382 | { .irq = -1 }, | |
d62bc78a NM |
383 | }; |
384 | ||
844a3b63 PW |
385 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
386 | .name = "timer12", | |
387 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
388 | .main_clk = "gpt12_fck", | |
389 | .prcm = { | |
390 | .omap2 = { | |
391 | .prcm_reg_id = 1, | |
392 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
393 | .module_offs = WKUP_MOD, | |
394 | .idlest_reg_id = 1, | |
395 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
396 | }, | |
d3442726 | 397 | }, |
844a3b63 PW |
398 | .dev_attr = &capability_secure_dev_attr, |
399 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
400 | }; |
401 | ||
844a3b63 PW |
402 | /* |
403 | * 'wd_timer' class | |
404 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
405 | * overflow condition | |
406 | */ | |
407 | ||
408 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
409 | .rev_offs = 0x0000, | |
410 | .sysc_offs = 0x0010, | |
411 | .syss_offs = 0x0014, | |
412 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
413 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
414 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
415 | SYSS_HAS_RESET_STATUS), | |
416 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
417 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
418 | }; |
419 | ||
844a3b63 PW |
420 | /* I2C common */ |
421 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
422 | .rev_offs = 0x00, | |
423 | .sysc_offs = 0x20, | |
424 | .syss_offs = 0x10, | |
425 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
426 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
427 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
428 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
429 | .clockact = CLOCKACT_TEST_ICLK, | |
430 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
431 | }; |
432 | ||
844a3b63 PW |
433 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
434 | .name = "wd_timer", | |
435 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
436 | .pre_shutdown = &omap2_wd_timer_disable, |
437 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
438 | }; |
439 | ||
844a3b63 PW |
440 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
441 | .name = "wd_timer2", | |
442 | .class = &omap3xxx_wd_timer_hwmod_class, | |
443 | .main_clk = "wdt2_fck", | |
444 | .prcm = { | |
445 | .omap2 = { | |
446 | .prcm_reg_id = 1, | |
447 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
448 | .module_offs = WKUP_MOD, | |
449 | .idlest_reg_id = 1, | |
450 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
451 | }, | |
452 | }, | |
453 | /* | |
454 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
455 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
456 | */ | |
457 | .flags = HWMOD_SWSUP_SIDLE, | |
458 | }; | |
870ea2b8 | 459 | |
844a3b63 PW |
460 | /* UART1 */ |
461 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
462 | .name = "uart1", | |
463 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
464 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
465 | .main_clk = "uart1_fck", | |
466 | .prcm = { | |
467 | .omap2 = { | |
468 | .module_offs = CORE_MOD, | |
469 | .prcm_reg_id = 1, | |
470 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
471 | .idlest_reg_id = 1, | |
472 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
473 | }, | |
870ea2b8 | 474 | }, |
844a3b63 | 475 | .class = &omap2_uart_class, |
870ea2b8 HH |
476 | }; |
477 | ||
844a3b63 PW |
478 | /* UART2 */ |
479 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
480 | .name = "uart2", | |
481 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
482 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
483 | .main_clk = "uart2_fck", | |
484 | .prcm = { | |
485 | .omap2 = { | |
486 | .module_offs = CORE_MOD, | |
487 | .prcm_reg_id = 1, | |
488 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
489 | .idlest_reg_id = 1, | |
490 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
491 | }, | |
492 | }, | |
493 | .class = &omap2_uart_class, | |
870ea2b8 HH |
494 | }; |
495 | ||
844a3b63 PW |
496 | /* UART3 */ |
497 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
498 | .name = "uart3", | |
499 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
500 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
501 | .main_clk = "uart3_fck", | |
502 | .prcm = { | |
503 | .omap2 = { | |
504 | .module_offs = OMAP3430_PER_MOD, | |
505 | .prcm_reg_id = 1, | |
506 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
507 | .idlest_reg_id = 1, | |
508 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
509 | }, | |
273ff8c3 | 510 | }, |
844a3b63 | 511 | .class = &omap2_uart_class, |
273ff8c3 HH |
512 | }; |
513 | ||
844a3b63 PW |
514 | /* UART4 */ |
515 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
7d7e1eba TL |
516 | { .irq = 80 + OMAP_INTC_START, }, |
517 | { .irq = -1 }, | |
273ff8c3 HH |
518 | }; |
519 | ||
844a3b63 PW |
520 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
521 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
522 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
523 | { .dma_req = -1 } | |
7359154e PW |
524 | }; |
525 | ||
844a3b63 PW |
526 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
527 | .name = "uart4", | |
528 | .mpu_irqs = uart4_mpu_irqs, | |
529 | .sdma_reqs = uart4_sdma_reqs, | |
530 | .main_clk = "uart4_fck", | |
531 | .prcm = { | |
532 | .omap2 = { | |
533 | .module_offs = OMAP3430_PER_MOD, | |
534 | .prcm_reg_id = 1, | |
535 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
536 | .idlest_reg_id = 1, | |
537 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
538 | }, | |
539 | }, | |
540 | .class = &omap2_uart_class, | |
7359154e PW |
541 | }; |
542 | ||
844a3b63 | 543 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
7d7e1eba TL |
544 | { .irq = 84 + OMAP_INTC_START, }, |
545 | { .irq = -1 }, | |
43085705 PW |
546 | }; |
547 | ||
844a3b63 PW |
548 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
549 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
550 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
bf765237 | 551 | { .dma_req = -1 } |
7359154e PW |
552 | }; |
553 | ||
82ee620d PW |
554 | /* |
555 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
556 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
557 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
558 | * should not be needed. The functional clock structure of the AM35xx | |
559 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
560 | * of uart1/2_fck is for the UART4. Any clarification from either | |
561 | * empirical testing or the AM3505/3517 hardware designers would be | |
562 | * most welcome. | |
563 | */ | |
564 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
565 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
566 | }; | |
567 | ||
844a3b63 PW |
568 | static struct omap_hwmod am35xx_uart4_hwmod = { |
569 | .name = "uart4", | |
570 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
571 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
572 | .main_clk = "uart4_fck", | |
573 | .prcm = { | |
574 | .omap2 = { | |
575 | .module_offs = CORE_MOD, | |
576 | .prcm_reg_id = 1, | |
bf765237 | 577 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 578 | .idlest_reg_id = 1, |
bf765237 | 579 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
580 | }, |
581 | }, | |
82ee620d PW |
582 | .opt_clks = am35xx_uart4_opt_clks, |
583 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
584 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
585 | .class = &omap2_uart_class, |
586 | }; | |
587 | ||
588 | static struct omap_hwmod_class i2c_class = { | |
589 | .name = "i2c", | |
590 | .sysc = &i2c_sysc, | |
591 | .rev = OMAP_I2C_IP_VERSION_1, | |
592 | .reset = &omap_i2c_reset, | |
593 | }; | |
594 | ||
595 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
596 | { .name = "dispc", .dma_req = 5 }, | |
597 | { .name = "dsi1", .dma_req = 74 }, | |
598 | { .dma_req = -1 } | |
43085705 PW |
599 | }; |
600 | ||
844a3b63 PW |
601 | /* dss */ |
602 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
603 | /* | |
604 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
605 | * driver does not use these clocks. | |
606 | */ | |
607 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
608 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
609 | /* required only on OMAP3430 */ | |
610 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
611 | }; |
612 | ||
844a3b63 PW |
613 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
614 | .name = "dss_core", | |
615 | .class = &omap2_dss_hwmod_class, | |
616 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
617 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
618 | .prcm = { | |
619 | .omap2 = { | |
620 | .prcm_reg_id = 1, | |
621 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
622 | .module_offs = OMAP3430_DSS_MOD, | |
623 | .idlest_reg_id = 1, | |
624 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
625 | }, | |
626 | }, | |
627 | .opt_clks = dss_opt_clks, | |
628 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
629 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
630 | }; | |
540064bf | 631 | |
844a3b63 PW |
632 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
633 | .name = "dss_core", | |
634 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
635 | .class = &omap2_dss_hwmod_class, | |
636 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
637 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
638 | .prcm = { | |
639 | .omap2 = { | |
640 | .prcm_reg_id = 1, | |
641 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
642 | .module_offs = OMAP3430_DSS_MOD, | |
643 | .idlest_reg_id = 1, | |
644 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
645 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
646 | }, | |
647 | }, | |
648 | .opt_clks = dss_opt_clks, | |
649 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
650 | }; |
651 | ||
540064bf | 652 | /* |
844a3b63 PW |
653 | * 'dispc' class |
654 | * display controller | |
540064bf KH |
655 | */ |
656 | ||
844a3b63 | 657 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
658 | .rev_offs = 0x0000, |
659 | .sysc_offs = 0x0010, | |
660 | .syss_offs = 0x0014, | |
844a3b63 PW |
661 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
662 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
663 | SYSC_HAS_ENAWAKEUP), | |
664 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
665 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 666 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
667 | }; |
668 | ||
844a3b63 PW |
669 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
670 | .name = "dispc", | |
671 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
672 | }; |
673 | ||
844a3b63 PW |
674 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
675 | .name = "dss_dispc", | |
676 | .class = &omap3_dispc_hwmod_class, | |
677 | .mpu_irqs = omap2_dispc_irqs, | |
678 | .main_clk = "dss1_alwon_fck", | |
679 | .prcm = { | |
680 | .omap2 = { | |
681 | .prcm_reg_id = 1, | |
682 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
683 | .module_offs = OMAP3430_DSS_MOD, | |
684 | }, | |
685 | }, | |
686 | .flags = HWMOD_NO_IDLEST, | |
687 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
688 | }; |
689 | ||
844a3b63 PW |
690 | /* |
691 | * 'dsi' class | |
692 | * display serial interface controller | |
693 | */ | |
4fe20e97 | 694 | |
844a3b63 PW |
695 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
696 | .name = "dsi", | |
c345c8b0 TKD |
697 | }; |
698 | ||
844a3b63 | 699 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
7d7e1eba TL |
700 | { .irq = 25 + OMAP_INTC_START, }, |
701 | { .irq = -1 }, | |
c345c8b0 TKD |
702 | }; |
703 | ||
844a3b63 PW |
704 | /* dss_dsi1 */ |
705 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
706 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
707 | }; |
708 | ||
844a3b63 PW |
709 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
710 | .name = "dss_dsi1", | |
711 | .class = &omap3xxx_dsi_hwmod_class, | |
712 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
713 | .main_clk = "dss1_alwon_fck", | |
714 | .prcm = { | |
715 | .omap2 = { | |
716 | .prcm_reg_id = 1, | |
717 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
718 | .module_offs = OMAP3430_DSS_MOD, | |
719 | }, | |
ce722d26 | 720 | }, |
844a3b63 PW |
721 | .opt_clks = dss_dsi1_opt_clks, |
722 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
723 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
724 | }; |
725 | ||
844a3b63 PW |
726 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
727 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
728 | }; |
729 | ||
844a3b63 PW |
730 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
731 | .name = "dss_rfbi", | |
732 | .class = &omap2_rfbi_hwmod_class, | |
733 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
734 | .prcm = { |
735 | .omap2 = { | |
736 | .prcm_reg_id = 1, | |
844a3b63 PW |
737 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
738 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
739 | }, |
740 | }, | |
844a3b63 PW |
741 | .opt_clks = dss_rfbi_opt_clks, |
742 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
743 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
744 | }; |
745 | ||
844a3b63 PW |
746 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
747 | /* required only on OMAP3430 */ | |
748 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
749 | }; |
750 | ||
844a3b63 PW |
751 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
752 | .name = "dss_venc", | |
753 | .class = &omap2_venc_hwmod_class, | |
754 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
755 | .prcm = { |
756 | .omap2 = { | |
046465b7 | 757 | .prcm_reg_id = 1, |
844a3b63 PW |
758 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
759 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
760 | }, |
761 | }, | |
844a3b63 PW |
762 | .opt_clks = dss_venc_opt_clks, |
763 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
764 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
765 | }; |
766 | ||
844a3b63 PW |
767 | /* I2C1 */ |
768 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
769 | .fifo_depth = 8, /* bytes */ | |
770 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
771 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
772 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
773 | }; |
774 | ||
844a3b63 PW |
775 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
776 | .name = "i2c1", | |
777 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
778 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
779 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
780 | .main_clk = "i2c1_fck", | |
046465b7 KH |
781 | .prcm = { |
782 | .omap2 = { | |
844a3b63 | 783 | .module_offs = CORE_MOD, |
046465b7 | 784 | .prcm_reg_id = 1, |
844a3b63 | 785 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 786 | .idlest_reg_id = 1, |
844a3b63 | 787 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
788 | }, |
789 | }, | |
844a3b63 PW |
790 | .class = &i2c_class, |
791 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
792 | }; |
793 | ||
844a3b63 PW |
794 | /* I2C2 */ |
795 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
796 | .fifo_depth = 8, /* bytes */ | |
797 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
798 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
799 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
800 | }; |
801 | ||
844a3b63 PW |
802 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
803 | .name = "i2c2", | |
804 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
805 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
806 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
807 | .main_clk = "i2c2_fck", | |
046465b7 KH |
808 | .prcm = { |
809 | .omap2 = { | |
844a3b63 | 810 | .module_offs = CORE_MOD, |
046465b7 | 811 | .prcm_reg_id = 1, |
844a3b63 | 812 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 813 | .idlest_reg_id = 1, |
844a3b63 | 814 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
815 | }, |
816 | }, | |
844a3b63 PW |
817 | .class = &i2c_class, |
818 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
819 | }; |
820 | ||
844a3b63 PW |
821 | /* I2C3 */ |
822 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
823 | .fifo_depth = 64, /* bytes */ | |
824 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
825 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
826 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
827 | }; | |
046465b7 | 828 | |
844a3b63 | 829 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
7d7e1eba TL |
830 | { .irq = 61 + OMAP_INTC_START, }, |
831 | { .irq = -1 }, | |
046465b7 KH |
832 | }; |
833 | ||
844a3b63 PW |
834 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
835 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
836 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
837 | { .dma_req = -1 } | |
046465b7 KH |
838 | }; |
839 | ||
844a3b63 PW |
840 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
841 | .name = "i2c3", | |
842 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
843 | .mpu_irqs = i2c3_mpu_irqs, | |
844 | .sdma_reqs = i2c3_sdma_reqs, | |
845 | .main_clk = "i2c3_fck", | |
046465b7 KH |
846 | .prcm = { |
847 | .omap2 = { | |
844a3b63 | 848 | .module_offs = CORE_MOD, |
046465b7 | 849 | .prcm_reg_id = 1, |
844a3b63 | 850 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 851 | .idlest_reg_id = 1, |
844a3b63 | 852 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
853 | }, |
854 | }, | |
844a3b63 PW |
855 | .class = &i2c_class, |
856 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
857 | }; |
858 | ||
844a3b63 PW |
859 | /* |
860 | * 'gpio' class | |
861 | * general purpose io module | |
862 | */ | |
4fe20e97 | 863 | |
844a3b63 PW |
864 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
865 | .rev_offs = 0x0000, | |
866 | .sysc_offs = 0x0010, | |
867 | .syss_offs = 0x0014, | |
868 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
869 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
870 | SYSS_HAS_RESET_STATUS), | |
871 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
872 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
873 | }; |
874 | ||
844a3b63 PW |
875 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
876 | .name = "gpio", | |
877 | .sysc = &omap3xxx_gpio_sysc, | |
878 | .rev = 1, | |
4fe20e97 RN |
879 | }; |
880 | ||
844a3b63 PW |
881 | /* gpio_dev_attr */ |
882 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
883 | .bank_width = 32, | |
884 | .dbck_flag = true, | |
885 | }; | |
886 | ||
887 | /* gpio1 */ | |
888 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
889 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
890 | }; | |
891 | ||
892 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
893 | .name = "gpio1", | |
894 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
895 | .mpu_irqs = omap2_gpio1_irqs, | |
896 | .main_clk = "gpio1_ick", | |
897 | .opt_clks = gpio1_opt_clks, | |
898 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
899 | .prcm = { |
900 | .omap2 = { | |
4fe20e97 | 901 | .prcm_reg_id = 1, |
844a3b63 PW |
902 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
903 | .module_offs = WKUP_MOD, | |
4fe20e97 | 904 | .idlest_reg_id = 1, |
844a3b63 | 905 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
906 | }, |
907 | }, | |
844a3b63 PW |
908 | .class = &omap3xxx_gpio_hwmod_class, |
909 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
910 | }; |
911 | ||
844a3b63 PW |
912 | /* gpio2 */ |
913 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
914 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
915 | }; |
916 | ||
844a3b63 PW |
917 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
918 | .name = "gpio2", | |
919 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
920 | .mpu_irqs = omap2_gpio2_irqs, | |
921 | .main_clk = "gpio2_ick", | |
922 | .opt_clks = gpio2_opt_clks, | |
923 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
924 | .prcm = { |
925 | .omap2 = { | |
4fe20e97 | 926 | .prcm_reg_id = 1, |
844a3b63 | 927 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 928 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 929 | .idlest_reg_id = 1, |
844a3b63 | 930 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
931 | }, |
932 | }, | |
844a3b63 PW |
933 | .class = &omap3xxx_gpio_hwmod_class, |
934 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
935 | }; |
936 | ||
844a3b63 PW |
937 | /* gpio3 */ |
938 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
939 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
940 | }; |
941 | ||
844a3b63 PW |
942 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
943 | .name = "gpio3", | |
944 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
945 | .mpu_irqs = omap2_gpio3_irqs, | |
946 | .main_clk = "gpio3_ick", | |
947 | .opt_clks = gpio3_opt_clks, | |
948 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
949 | .prcm = { |
950 | .omap2 = { | |
4fe20e97 | 951 | .prcm_reg_id = 1, |
844a3b63 | 952 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 953 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 954 | .idlest_reg_id = 1, |
844a3b63 | 955 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
956 | }, |
957 | }, | |
844a3b63 PW |
958 | .class = &omap3xxx_gpio_hwmod_class, |
959 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
960 | }; |
961 | ||
844a3b63 PW |
962 | /* gpio4 */ |
963 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
964 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
965 | }; |
966 | ||
844a3b63 PW |
967 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
968 | .name = "gpio4", | |
969 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
970 | .mpu_irqs = omap2_gpio4_irqs, | |
971 | .main_clk = "gpio4_ick", | |
972 | .opt_clks = gpio4_opt_clks, | |
973 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
974 | .prcm = { |
975 | .omap2 = { | |
976 | .prcm_reg_id = 1, | |
844a3b63 | 977 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
978 | .module_offs = OMAP3430_PER_MOD, |
979 | .idlest_reg_id = 1, | |
844a3b63 | 980 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 981 | }, |
70034d38 | 982 | }, |
844a3b63 PW |
983 | .class = &omap3xxx_gpio_hwmod_class, |
984 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
985 | }; |
986 | ||
844a3b63 PW |
987 | /* gpio5 */ |
988 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
7d7e1eba TL |
989 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
990 | { .irq = -1 }, | |
844a3b63 | 991 | }; |
70034d38 | 992 | |
844a3b63 PW |
993 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
994 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
995 | }; |
996 | ||
844a3b63 PW |
997 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
998 | .name = "gpio5", | |
999 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1000 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
1001 | .main_clk = "gpio5_ick", | |
1002 | .opt_clks = gpio5_opt_clks, | |
1003 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
1004 | .prcm = { |
1005 | .omap2 = { | |
1006 | .prcm_reg_id = 1, | |
844a3b63 PW |
1007 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
1008 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1009 | .idlest_reg_id = 1, |
844a3b63 | 1010 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 1011 | }, |
70034d38 | 1012 | }, |
844a3b63 PW |
1013 | .class = &omap3xxx_gpio_hwmod_class, |
1014 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1015 | }; |
1016 | ||
844a3b63 PW |
1017 | /* gpio6 */ |
1018 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
7d7e1eba TL |
1019 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
1020 | { .irq = -1 }, | |
844a3b63 | 1021 | }; |
70034d38 | 1022 | |
844a3b63 PW |
1023 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
1024 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
1025 | }; |
1026 | ||
844a3b63 PW |
1027 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
1028 | .name = "gpio6", | |
1029 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1030 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1031 | .main_clk = "gpio6_ick", | |
1032 | .opt_clks = gpio6_opt_clks, | |
1033 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1034 | .prcm = { |
1035 | .omap2 = { | |
1036 | .prcm_reg_id = 1, | |
844a3b63 PW |
1037 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1038 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1039 | .idlest_reg_id = 1, |
844a3b63 | 1040 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1041 | }, |
1042 | }, | |
844a3b63 PW |
1043 | .class = &omap3xxx_gpio_hwmod_class, |
1044 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1045 | }; |
1046 | ||
844a3b63 PW |
1047 | /* dma attributes */ |
1048 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1049 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1050 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1051 | .lch_count = 32, | |
ce722d26 TG |
1052 | }; |
1053 | ||
844a3b63 PW |
1054 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1055 | .rev_offs = 0x0000, | |
1056 | .sysc_offs = 0x002c, | |
1057 | .syss_offs = 0x0028, | |
1058 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1059 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1060 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1061 | SYSS_HAS_RESET_STATUS), | |
1062 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1063 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1064 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1065 | }; |
1066 | ||
844a3b63 PW |
1067 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1068 | .name = "dma", | |
1069 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1070 | }; |
1071 | ||
844a3b63 PW |
1072 | /* dma_system */ |
1073 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1074 | .name = "dma", | |
1075 | .class = &omap3xxx_dma_hwmod_class, | |
1076 | .mpu_irqs = omap2_dma_system_irqs, | |
1077 | .main_clk = "core_l3_ick", | |
1078 | .prcm = { | |
ce722d26 | 1079 | .omap2 = { |
844a3b63 PW |
1080 | .module_offs = CORE_MOD, |
1081 | .prcm_reg_id = 1, | |
1082 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1083 | .idlest_reg_id = 1, | |
1084 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1085 | }, |
1086 | }, | |
844a3b63 PW |
1087 | .dev_attr = &dma_dev_attr, |
1088 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1089 | }; |
1090 | ||
844a3b63 PW |
1091 | /* |
1092 | * 'mcbsp' class | |
1093 | * multi channel buffered serial port controller | |
1094 | */ | |
1095 | ||
1096 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1097 | .sysc_offs = 0x008c, | |
1098 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1099 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1100 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1101 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1102 | .clockact = 0x2, | |
70034d38 VC |
1103 | }; |
1104 | ||
844a3b63 PW |
1105 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1106 | .name = "mcbsp", | |
1107 | .sysc = &omap3xxx_mcbsp_sysc, | |
1108 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1109 | }; |
1110 | ||
7039154b PU |
1111 | /* McBSP functional clock mapping */ |
1112 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1113 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1114 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1115 | }; | |
1116 | ||
1117 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1118 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1119 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1120 | }; | |
1121 | ||
844a3b63 PW |
1122 | /* mcbsp1 */ |
1123 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
7d7e1eba TL |
1124 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
1125 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, | |
1126 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
1127 | { .irq = -1 }, | |
844a3b63 | 1128 | }; |
6b667f88 | 1129 | |
844a3b63 PW |
1130 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1131 | .name = "mcbsp1", | |
1132 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1133 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1134 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1135 | .main_clk = "mcbsp1_fck", | |
1136 | .prcm = { | |
1137 | .omap2 = { | |
1138 | .prcm_reg_id = 1, | |
1139 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1140 | .module_offs = CORE_MOD, | |
1141 | .idlest_reg_id = 1, | |
1142 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1143 | }, | |
1144 | }, | |
7039154b PU |
1145 | .opt_clks = mcbsp15_opt_clks, |
1146 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1147 | }; |
1148 | ||
844a3b63 PW |
1149 | /* mcbsp2 */ |
1150 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
7d7e1eba TL |
1151 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
1152 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, | |
1153 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
1154 | { .irq = -1 }, | |
70034d38 VC |
1155 | }; |
1156 | ||
844a3b63 PW |
1157 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1158 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1159 | }; |
1160 | ||
844a3b63 PW |
1161 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1162 | .name = "mcbsp2", | |
1163 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1164 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1165 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1166 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1167 | .prcm = { |
1168 | .omap2 = { | |
1169 | .prcm_reg_id = 1, | |
844a3b63 PW |
1170 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1171 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1172 | .idlest_reg_id = 1, |
844a3b63 | 1173 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1174 | }, |
1175 | }, | |
7039154b PU |
1176 | .opt_clks = mcbsp234_opt_clks, |
1177 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1178 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1179 | }; |
1180 | ||
844a3b63 PW |
1181 | /* mcbsp3 */ |
1182 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
7d7e1eba TL |
1183 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
1184 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, | |
1185 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
1186 | { .irq = -1 }, | |
844a3b63 PW |
1187 | }; |
1188 | ||
1189 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1190 | .sidetone = "mcbsp3_sidetone", | |
1191 | }; | |
1192 | ||
1193 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1194 | .name = "mcbsp3", | |
1195 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1196 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1197 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1198 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1199 | .prcm = { |
1200 | .omap2 = { | |
1201 | .prcm_reg_id = 1, | |
844a3b63 PW |
1202 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1203 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1204 | .idlest_reg_id = 1, |
844a3b63 | 1205 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1206 | }, |
1207 | }, | |
7039154b PU |
1208 | .opt_clks = mcbsp234_opt_clks, |
1209 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1210 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1211 | }; |
1212 | ||
844a3b63 PW |
1213 | /* mcbsp4 */ |
1214 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
7d7e1eba TL |
1215 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
1216 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, | |
1217 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
1218 | { .irq = -1 }, | |
844a3b63 PW |
1219 | }; |
1220 | ||
1221 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1222 | { .name = "rx", .dma_req = 20 }, | |
1223 | { .name = "tx", .dma_req = 19 }, | |
1224 | { .dma_req = -1 } | |
1225 | }; | |
1226 | ||
1227 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1228 | .name = "mcbsp4", | |
1229 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1230 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1231 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1232 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1233 | .prcm = { |
1234 | .omap2 = { | |
1235 | .prcm_reg_id = 1, | |
844a3b63 PW |
1236 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1237 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1238 | .idlest_reg_id = 1, |
844a3b63 | 1239 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1240 | }, |
1241 | }, | |
7039154b PU |
1242 | .opt_clks = mcbsp234_opt_clks, |
1243 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1244 | }; |
1245 | ||
844a3b63 PW |
1246 | /* mcbsp5 */ |
1247 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
7d7e1eba TL |
1248 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
1249 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, | |
1250 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
1251 | { .irq = -1 }, | |
844a3b63 PW |
1252 | }; |
1253 | ||
1254 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1255 | { .name = "rx", .dma_req = 22 }, | |
1256 | { .name = "tx", .dma_req = 21 }, | |
1257 | { .dma_req = -1 } | |
1258 | }; | |
1259 | ||
1260 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1261 | .name = "mcbsp5", | |
1262 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1263 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1264 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1265 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1266 | .prcm = { |
1267 | .omap2 = { | |
046465b7 | 1268 | .prcm_reg_id = 1, |
844a3b63 PW |
1269 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1270 | .module_offs = CORE_MOD, | |
70034d38 | 1271 | .idlest_reg_id = 1, |
844a3b63 | 1272 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1273 | }, |
1274 | }, | |
7039154b PU |
1275 | .opt_clks = mcbsp15_opt_clks, |
1276 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1277 | }; |
1278 | ||
844a3b63 PW |
1279 | /* 'mcbsp sidetone' class */ |
1280 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1281 | .sysc_offs = 0x0010, | |
1282 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1283 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1284 | }; | |
046465b7 | 1285 | |
844a3b63 PW |
1286 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1287 | .name = "mcbsp_sidetone", | |
1288 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1289 | }; |
1290 | ||
844a3b63 PW |
1291 | /* mcbsp2_sidetone */ |
1292 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
7d7e1eba TL |
1293 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
1294 | { .irq = -1 }, | |
70034d38 VC |
1295 | }; |
1296 | ||
844a3b63 PW |
1297 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1298 | .name = "mcbsp2_sidetone", | |
1299 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1300 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1301 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1302 | .prcm = { |
1303 | .omap2 = { | |
046465b7 | 1304 | .prcm_reg_id = 1, |
844a3b63 PW |
1305 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1306 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1307 | .idlest_reg_id = 1, |
844a3b63 | 1308 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1309 | }, |
1310 | }, | |
4bf90f65 KM |
1311 | }; |
1312 | ||
844a3b63 PW |
1313 | /* mcbsp3_sidetone */ |
1314 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
7d7e1eba TL |
1315 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
1316 | { .irq = -1 }, | |
4bf90f65 KM |
1317 | }; |
1318 | ||
844a3b63 PW |
1319 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1320 | .name = "mcbsp3_sidetone", | |
1321 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1322 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1323 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1324 | .prcm = { |
4bf90f65 | 1325 | .omap2 = { |
4bf90f65 | 1326 | .prcm_reg_id = 1, |
844a3b63 PW |
1327 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1328 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1329 | .idlest_reg_id = 1, |
844a3b63 | 1330 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1331 | }, |
1332 | }, | |
4bf90f65 KM |
1333 | }; |
1334 | ||
844a3b63 PW |
1335 | /* SR common */ |
1336 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1337 | .clkact_shift = 20, | |
1338 | }; | |
4bf90f65 | 1339 | |
844a3b63 PW |
1340 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1341 | .sysc_offs = 0x24, | |
1342 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1343 | .clockact = CLOCKACT_TEST_ICLK, | |
1344 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1345 | }; |
1346 | ||
844a3b63 PW |
1347 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1348 | .name = "smartreflex", | |
1349 | .sysc = &omap34xx_sr_sysc, | |
1350 | .rev = 1, | |
e04d9e1e SG |
1351 | }; |
1352 | ||
844a3b63 PW |
1353 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1354 | .sidle_shift = 24, | |
1355 | .enwkup_shift = 26, | |
1356 | }; | |
e04d9e1e | 1357 | |
844a3b63 PW |
1358 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1359 | .sysc_offs = 0x38, | |
1360 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1361 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1362 | SYSC_NO_CACHE), | |
1363 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1364 | }; | |
1365 | ||
1366 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1367 | .name = "smartreflex", | |
1368 | .sysc = &omap36xx_sr_sysc, | |
1369 | .rev = 2, | |
1370 | }; | |
1371 | ||
1372 | /* SR1 */ | |
1373 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1374 | .sensor_voltdm_name = "mpu_iva", | |
1375 | }; | |
1376 | ||
1377 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
7d7e1eba TL |
1378 | { .irq = 18 + OMAP_INTC_START, }, |
1379 | { .irq = -1 }, | |
844a3b63 PW |
1380 | }; |
1381 | ||
1382 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1383 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1384 | .class = &omap34xx_smartreflex_hwmod_class, |
1385 | .main_clk = "sr1_fck", | |
1386 | .prcm = { | |
e04d9e1e | 1387 | .omap2 = { |
844a3b63 PW |
1388 | .prcm_reg_id = 1, |
1389 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1390 | .module_offs = WKUP_MOD, | |
1391 | .idlest_reg_id = 1, | |
1392 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1393 | }, | |
e04d9e1e | 1394 | }, |
844a3b63 PW |
1395 | .dev_attr = &sr1_dev_attr, |
1396 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1397 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1398 | }; |
1399 | ||
844a3b63 | 1400 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1401 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1402 | .class = &omap36xx_smartreflex_hwmod_class, |
1403 | .main_clk = "sr1_fck", | |
1404 | .prcm = { | |
e04d9e1e | 1405 | .omap2 = { |
844a3b63 PW |
1406 | .prcm_reg_id = 1, |
1407 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1408 | .module_offs = WKUP_MOD, | |
1409 | .idlest_reg_id = 1, | |
1410 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1411 | }, | |
e04d9e1e | 1412 | }, |
844a3b63 PW |
1413 | .dev_attr = &sr1_dev_attr, |
1414 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1415 | }; |
1416 | ||
844a3b63 PW |
1417 | /* SR2 */ |
1418 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1419 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1420 | }; |
1421 | ||
844a3b63 | 1422 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
7d7e1eba TL |
1423 | { .irq = 19 + OMAP_INTC_START, }, |
1424 | { .irq = -1 }, | |
844a3b63 PW |
1425 | }; |
1426 | ||
1427 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1428 | .name = "smartreflex_core", |
844a3b63 PW |
1429 | .class = &omap34xx_smartreflex_hwmod_class, |
1430 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1431 | .prcm = { |
1432 | .omap2 = { | |
1433 | .prcm_reg_id = 1, | |
844a3b63 PW |
1434 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1435 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1436 | .idlest_reg_id = 1, |
844a3b63 | 1437 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1438 | }, |
1439 | }, | |
844a3b63 PW |
1440 | .dev_attr = &sr2_dev_attr, |
1441 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1442 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1443 | }; |
1444 | ||
844a3b63 | 1445 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1446 | .name = "smartreflex_core", |
844a3b63 PW |
1447 | .class = &omap36xx_smartreflex_hwmod_class, |
1448 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1449 | .prcm = { |
1450 | .omap2 = { | |
1451 | .prcm_reg_id = 1, | |
844a3b63 PW |
1452 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1453 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1454 | .idlest_reg_id = 1, |
844a3b63 | 1455 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1456 | }, |
1457 | }, | |
844a3b63 PW |
1458 | .dev_attr = &sr2_dev_attr, |
1459 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1460 | }; |
1461 | ||
1ac6d46e | 1462 | /* |
844a3b63 PW |
1463 | * 'mailbox' class |
1464 | * mailbox module allowing communication between the on-chip processors | |
1465 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1466 | */ |
1467 | ||
844a3b63 PW |
1468 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1469 | .rev_offs = 0x000, | |
1470 | .sysc_offs = 0x010, | |
1471 | .syss_offs = 0x014, | |
1472 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1473 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1474 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1475 | .sysc_fields = &omap_hwmod_sysc_type1, |
1476 | }; | |
1477 | ||
844a3b63 PW |
1478 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1479 | .name = "mailbox", | |
1480 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1481 | }; |
1482 | ||
844a3b63 | 1483 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
7d7e1eba TL |
1484 | { .irq = 26 + OMAP_INTC_START, }, |
1485 | { .irq = -1 }, | |
e04d9e1e SG |
1486 | }; |
1487 | ||
844a3b63 PW |
1488 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1489 | .name = "mailbox", | |
1490 | .class = &omap3xxx_mailbox_hwmod_class, | |
1491 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1492 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1493 | .prcm = { |
1494 | .omap2 = { | |
1495 | .prcm_reg_id = 1, | |
844a3b63 PW |
1496 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1497 | .module_offs = CORE_MOD, | |
1498 | .idlest_reg_id = 1, | |
1499 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1500 | }, |
1501 | }, | |
e04d9e1e SG |
1502 | }; |
1503 | ||
1504 | /* | |
844a3b63 PW |
1505 | * 'mcspi' class |
1506 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1507 | * bus | |
e04d9e1e SG |
1508 | */ |
1509 | ||
844a3b63 PW |
1510 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1511 | .rev_offs = 0x0000, | |
1512 | .sysc_offs = 0x0010, | |
1513 | .syss_offs = 0x0014, | |
1514 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1515 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1516 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1517 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1518 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1519 | }; |
1520 | ||
844a3b63 PW |
1521 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1522 | .name = "mcspi", | |
1523 | .sysc = &omap34xx_mcspi_sysc, | |
1524 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1525 | }; |
1526 | ||
844a3b63 PW |
1527 | /* mcspi1 */ |
1528 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1529 | .num_chipselect = 4, | |
e04d9e1e SG |
1530 | }; |
1531 | ||
844a3b63 PW |
1532 | static struct omap_hwmod omap34xx_mcspi1 = { |
1533 | .name = "mcspi1", | |
1534 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1535 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1536 | .main_clk = "mcspi1_fck", | |
1537 | .prcm = { | |
e04d9e1e | 1538 | .omap2 = { |
844a3b63 PW |
1539 | .module_offs = CORE_MOD, |
1540 | .prcm_reg_id = 1, | |
1541 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1542 | .idlest_reg_id = 1, | |
1543 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1544 | }, | |
e04d9e1e | 1545 | }, |
844a3b63 PW |
1546 | .class = &omap34xx_mcspi_class, |
1547 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1548 | }; |
1549 | ||
844a3b63 PW |
1550 | /* mcspi2 */ |
1551 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1552 | .num_chipselect = 2, | |
6c3d7e34 TV |
1553 | }; |
1554 | ||
844a3b63 PW |
1555 | static struct omap_hwmod omap34xx_mcspi2 = { |
1556 | .name = "mcspi2", | |
1557 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1558 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1559 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1560 | .prcm = { |
1561 | .omap2 = { | |
844a3b63 | 1562 | .module_offs = CORE_MOD, |
e04d9e1e | 1563 | .prcm_reg_id = 1, |
844a3b63 PW |
1564 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1565 | .idlest_reg_id = 1, | |
1566 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1567 | }, |
1568 | }, | |
844a3b63 PW |
1569 | .class = &omap34xx_mcspi_class, |
1570 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1571 | }; |
1572 | ||
844a3b63 PW |
1573 | /* mcspi3 */ |
1574 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
1575 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
1576 | { .irq = -1 }, | |
844a3b63 PW |
1577 | }; |
1578 | ||
1579 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1580 | { .name = "tx0", .dma_req = 15 }, | |
1581 | { .name = "rx0", .dma_req = 16 }, | |
1582 | { .name = "tx1", .dma_req = 23 }, | |
1583 | { .name = "rx1", .dma_req = 24 }, | |
1584 | { .dma_req = -1 } | |
e04d9e1e SG |
1585 | }; |
1586 | ||
844a3b63 PW |
1587 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1588 | .num_chipselect = 2, | |
6c3d7e34 TV |
1589 | }; |
1590 | ||
844a3b63 PW |
1591 | static struct omap_hwmod omap34xx_mcspi3 = { |
1592 | .name = "mcspi3", | |
1593 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1594 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1595 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1596 | .prcm = { |
1597 | .omap2 = { | |
844a3b63 | 1598 | .module_offs = CORE_MOD, |
e04d9e1e | 1599 | .prcm_reg_id = 1, |
844a3b63 PW |
1600 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1601 | .idlest_reg_id = 1, | |
1602 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1603 | }, |
1604 | }, | |
844a3b63 PW |
1605 | .class = &omap34xx_mcspi_class, |
1606 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1607 | }; |
1608 | ||
844a3b63 PW |
1609 | /* mcspi4 */ |
1610 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
7d7e1eba TL |
1611 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
1612 | { .irq = -1 }, | |
e04d9e1e SG |
1613 | }; |
1614 | ||
844a3b63 PW |
1615 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1616 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1617 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1618 | { .dma_req = -1 } | |
6c3d7e34 TV |
1619 | }; |
1620 | ||
844a3b63 PW |
1621 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1622 | .num_chipselect = 1, | |
1623 | }; | |
1624 | ||
1625 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1626 | .name = "mcspi4", | |
1627 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1628 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1629 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1630 | .prcm = { |
1631 | .omap2 = { | |
844a3b63 | 1632 | .module_offs = CORE_MOD, |
e04d9e1e | 1633 | .prcm_reg_id = 1, |
844a3b63 PW |
1634 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1635 | .idlest_reg_id = 1, | |
1636 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1637 | }, |
1638 | }, | |
844a3b63 PW |
1639 | .class = &omap34xx_mcspi_class, |
1640 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1641 | }; |
1642 | ||
844a3b63 PW |
1643 | /* usbhsotg */ |
1644 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1645 | .rev_offs = 0x0400, | |
1646 | .sysc_offs = 0x0404, | |
1647 | .syss_offs = 0x0408, | |
1648 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1649 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1650 | SYSC_HAS_AUTOIDLE), | |
1651 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1652 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1653 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1654 | }; | |
4fe20e97 | 1655 | |
844a3b63 PW |
1656 | static struct omap_hwmod_class usbotg_class = { |
1657 | .name = "usbotg", | |
1658 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1659 | }; |
1660 | ||
844a3b63 PW |
1661 | /* usb_otg_hs */ |
1662 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1663 | ||
7d7e1eba TL |
1664 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
1665 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
1666 | { .irq = -1 }, | |
844a3b63 PW |
1667 | }; |
1668 | ||
1669 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1670 | .name = "usb_otg_hs", | |
1671 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1672 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1673 | .prcm = { |
1674 | .omap2 = { | |
4fe20e97 | 1675 | .prcm_reg_id = 1, |
844a3b63 PW |
1676 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1677 | .module_offs = CORE_MOD, | |
4fe20e97 | 1678 | .idlest_reg_id = 1, |
844a3b63 PW |
1679 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1680 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1681 | }, |
1682 | }, | |
844a3b63 PW |
1683 | .class = &usbotg_class, |
1684 | ||
1685 | /* | |
1686 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1687 | * broken when autoidle is enabled | |
1688 | * workaround is to disable the autoidle bit at module level. | |
1689 | */ | |
1690 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1691 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1692 | }; |
1693 | ||
844a3b63 PW |
1694 | /* usb_otg_hs */ |
1695 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
7d7e1eba TL |
1696 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
1697 | { .irq = -1 }, | |
4fe20e97 RN |
1698 | }; |
1699 | ||
844a3b63 PW |
1700 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1701 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1702 | }; |
1703 | ||
1704 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1705 | .name = "am35x_otg_hs", | |
1706 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1707 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1708 | .class = &am35xx_usbotg_class, |
89ea2583 | 1709 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1710 | }; |
1711 | ||
844a3b63 PW |
1712 | /* MMC/SD/SDIO common */ |
1713 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1714 | .rev_offs = 0x1fc, | |
1715 | .sysc_offs = 0x10, | |
1716 | .syss_offs = 0x14, | |
1717 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1718 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1719 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1720 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1721 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1722 | }; | |
4fe20e97 | 1723 | |
844a3b63 PW |
1724 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1725 | .name = "mmc", | |
1726 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1727 | }; |
1728 | ||
844a3b63 PW |
1729 | /* MMC/SD/SDIO1 */ |
1730 | ||
1731 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
7d7e1eba TL |
1732 | { .irq = 83 + OMAP_INTC_START, }, |
1733 | { .irq = -1 }, | |
4fe20e97 RN |
1734 | }; |
1735 | ||
844a3b63 PW |
1736 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1737 | { .name = "tx", .dma_req = 61, }, | |
1738 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1739 | { .dma_req = -1 } |
4fe20e97 RN |
1740 | }; |
1741 | ||
844a3b63 PW |
1742 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1743 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1744 | }; | |
1745 | ||
1746 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1747 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1748 | }; | |
1749 | ||
1750 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1751 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1752 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1753 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1754 | }; | |
1755 | ||
1756 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1757 | .name = "mmc1", | |
1758 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1759 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1760 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1761 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1762 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1763 | .prcm = { |
1764 | .omap2 = { | |
1765 | .module_offs = CORE_MOD, | |
1766 | .prcm_reg_id = 1, | |
844a3b63 | 1767 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1768 | .idlest_reg_id = 1, |
844a3b63 | 1769 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1770 | }, |
1771 | }, | |
844a3b63 PW |
1772 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1773 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1774 | }; |
1775 | ||
844a3b63 PW |
1776 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1777 | .name = "mmc1", | |
1778 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1779 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1780 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1781 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1782 | .main_clk = "mmchs1_fck", | |
1783 | .prcm = { | |
1784 | .omap2 = { | |
1785 | .module_offs = CORE_MOD, | |
1786 | .prcm_reg_id = 1, | |
1787 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1788 | .idlest_reg_id = 1, | |
1789 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1790 | }, | |
70034d38 | 1791 | }, |
844a3b63 PW |
1792 | .dev_attr = &mmc1_dev_attr, |
1793 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1794 | }; |
1795 | ||
844a3b63 | 1796 | /* MMC/SD/SDIO2 */ |
70034d38 | 1797 | |
844a3b63 | 1798 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
1799 | { .irq = 86 + OMAP_INTC_START, }, |
1800 | { .irq = -1 }, | |
70034d38 VC |
1801 | }; |
1802 | ||
844a3b63 PW |
1803 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1804 | { .name = "tx", .dma_req = 47, }, | |
1805 | { .name = "rx", .dma_req = 48, }, | |
1806 | { .dma_req = -1 } | |
70034d38 VC |
1807 | }; |
1808 | ||
844a3b63 PW |
1809 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1810 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1811 | }; |
1812 | ||
844a3b63 PW |
1813 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1814 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1815 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1816 | }; |
1817 | ||
844a3b63 PW |
1818 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1819 | .name = "mmc2", | |
1820 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1821 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1822 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1823 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1824 | .main_clk = "mmchs2_fck", | |
1825 | .prcm = { | |
1826 | .omap2 = { | |
1827 | .module_offs = CORE_MOD, | |
1828 | .prcm_reg_id = 1, | |
1829 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1830 | .idlest_reg_id = 1, | |
1831 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1832 | }, | |
70034d38 | 1833 | }, |
844a3b63 PW |
1834 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1835 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1836 | }; |
1837 | ||
844a3b63 PW |
1838 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1839 | .name = "mmc2", | |
1840 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1841 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1842 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1843 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1844 | .main_clk = "mmchs2_fck", | |
1845 | .prcm = { | |
1846 | .omap2 = { | |
1847 | .module_offs = CORE_MOD, | |
1848 | .prcm_reg_id = 1, | |
1849 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1850 | .idlest_reg_id = 1, | |
1851 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1852 | }, | |
1853 | }, | |
1854 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1855 | }; |
1856 | ||
844a3b63 PW |
1857 | /* MMC/SD/SDIO3 */ |
1858 | ||
1859 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
7d7e1eba TL |
1860 | { .irq = 94 + OMAP_INTC_START, }, |
1861 | { .irq = -1 }, | |
70034d38 VC |
1862 | }; |
1863 | ||
844a3b63 PW |
1864 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1865 | { .name = "tx", .dma_req = 77, }, | |
1866 | { .name = "rx", .dma_req = 78, }, | |
1867 | { .dma_req = -1 } | |
70034d38 VC |
1868 | }; |
1869 | ||
844a3b63 PW |
1870 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1871 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1872 | }; |
1873 | ||
844a3b63 PW |
1874 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1875 | .name = "mmc3", | |
1876 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1877 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1878 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1879 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1880 | .main_clk = "mmchs3_fck", | |
1881 | .prcm = { | |
1882 | .omap2 = { | |
1883 | .prcm_reg_id = 1, | |
1884 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1885 | .idlest_reg_id = 1, | |
1886 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1887 | }, | |
1888 | }, | |
1889 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1890 | }; |
1891 | ||
1892 | /* | |
844a3b63 PW |
1893 | * 'usb_host_hs' class |
1894 | * high-speed multi-port usb host controller | |
70034d38 VC |
1895 | */ |
1896 | ||
844a3b63 | 1897 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1898 | .rev_offs = 0x0000, |
1899 | .sysc_offs = 0x0010, | |
1900 | .syss_offs = 0x0014, | |
844a3b63 PW |
1901 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1902 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1903 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1904 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1905 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1906 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1907 | }; |
1908 | ||
844a3b63 PW |
1909 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1910 | .name = "usb_host_hs", | |
1911 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1912 | }; |
1913 | ||
844a3b63 PW |
1914 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1915 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1916 | }; |
1917 | ||
844a3b63 | 1918 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
7d7e1eba TL |
1919 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
1920 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, | |
1921 | { .irq = -1 }, | |
70034d38 VC |
1922 | }; |
1923 | ||
844a3b63 PW |
1924 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1925 | .name = "usb_host_hs", | |
1926 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1927 | .clkdm_name = "l3_init_clkdm", | |
1928 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1929 | .main_clk = "usbhost_48m_fck", | |
1930 | .prcm = { | |
70034d38 | 1931 | .omap2 = { |
844a3b63 | 1932 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1933 | .prcm_reg_id = 1, |
844a3b63 | 1934 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1935 | .idlest_reg_id = 1, |
844a3b63 PW |
1936 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1937 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1938 | }, |
1939 | }, | |
844a3b63 PW |
1940 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1941 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1942 | |
844a3b63 PW |
1943 | /* |
1944 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1945 | * id: i660 | |
1946 | * | |
1947 | * Description: | |
1948 | * In the following configuration : | |
1949 | * - USBHOST module is set to smart-idle mode | |
1950 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1951 | * happens when the system is going to a low power mode : all ports | |
1952 | * have been suspended, the master part of the USBHOST module has | |
1953 | * entered the standby state, and SW has cut the functional clocks) | |
1954 | * - an USBHOST interrupt occurs before the module is able to answer | |
1955 | * idle_ack, typically a remote wakeup IRQ. | |
1956 | * Then the USB HOST module will enter a deadlock situation where it | |
1957 | * is no more accessible nor functional. | |
1958 | * | |
1959 | * Workaround: | |
1960 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1961 | */ | |
1962 | ||
1963 | /* | |
1964 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1965 | * Id: i571 | |
1966 | * | |
1967 | * Description: | |
1968 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1969 | * ready to enter the standby state (i.e. all ports are suspended and | |
1970 | * all attached devices are in suspend mode), then it can wrongly assert | |
1971 | * the Mstandby signal too early while there are still some residual OCP | |
1972 | * transactions ongoing. If this condition occurs, the internal state | |
1973 | * machine may go to an undefined state and the USB link may be stuck | |
1974 | * upon the next resume. | |
1975 | * | |
1976 | * Workaround: | |
1977 | * Don't use smart standby; use only force standby, | |
1978 | * hence HWMOD_SWSUP_MSTANDBY | |
1979 | */ | |
1980 | ||
1981 | /* | |
1982 | * During system boot; If the hwmod framework resets the module | |
1983 | * the module will have smart idle settings; which can lead to deadlock | |
1984 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1985 | * Use HWMOD_INIT_NO_RESET. | |
1986 | */ | |
70034d38 | 1987 | |
844a3b63 PW |
1988 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1989 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1990 | }; |
1991 | ||
844a3b63 PW |
1992 | /* |
1993 | * 'usb_tll_hs' class | |
1994 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1995 | */ | |
1996 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1997 | .rev_offs = 0x0000, | |
1998 | .sysc_offs = 0x0010, | |
1999 | .syss_offs = 0x0014, | |
2000 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2001 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2002 | SYSC_HAS_AUTOIDLE), | |
2003 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2004 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
2005 | }; |
2006 | ||
844a3b63 PW |
2007 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
2008 | .name = "usb_tll_hs", | |
2009 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
2010 | }; |
2011 | ||
844a3b63 | 2012 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
7d7e1eba TL |
2013 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
2014 | { .irq = -1 }, | |
70034d38 VC |
2015 | }; |
2016 | ||
844a3b63 PW |
2017 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
2018 | .name = "usb_tll_hs", | |
2019 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
2020 | .clkdm_name = "l3_init_clkdm", | |
2021 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
2022 | .main_clk = "usbtll_fck", | |
2023 | .prcm = { | |
70034d38 | 2024 | .omap2 = { |
844a3b63 PW |
2025 | .module_offs = CORE_MOD, |
2026 | .prcm_reg_id = 3, | |
2027 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
2028 | .idlest_reg_id = 3, | |
2029 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
2030 | }, |
2031 | }, | |
70034d38 VC |
2032 | }; |
2033 | ||
45a4bb06 PW |
2034 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
2035 | .name = "hdq1w", | |
2036 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
2037 | .main_clk = "hdq_fck", | |
2038 | .prcm = { | |
2039 | .omap2 = { | |
2040 | .module_offs = CORE_MOD, | |
2041 | .prcm_reg_id = 1, | |
2042 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
2043 | .idlest_reg_id = 1, | |
2044 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
2045 | }, | |
2046 | }, | |
2047 | .class = &omap2_hdq1w_class, | |
2048 | }; | |
2049 | ||
8f993a01 TK |
2050 | /* SAD2D */ |
2051 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
2052 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
2053 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
2054 | }; | |
2055 | ||
2056 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
2057 | .name = "sad2d", | |
2058 | }; | |
2059 | ||
2060 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
2061 | .name = "sad2d", | |
2062 | .rst_lines = omap3xxx_sad2d_resets, | |
2063 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
2064 | .main_clk = "sad2d_ick", | |
2065 | .prcm = { | |
2066 | .omap2 = { | |
2067 | .module_offs = CORE_MOD, | |
2068 | .prcm_reg_id = 1, | |
2069 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
2070 | .idlest_reg_id = 1, | |
2071 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
2072 | }, | |
2073 | }, | |
2074 | .class = &omap3xxx_sad2d_class, | |
2075 | }; | |
2076 | ||
c8d82ff6 VH |
2077 | /* |
2078 | * '32K sync counter' class | |
2079 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2080 | */ | |
2081 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2082 | .rev_offs = 0x0000, | |
2083 | .sysc_offs = 0x0004, | |
2084 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2085 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2086 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2087 | }; | |
2088 | ||
2089 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2090 | .name = "counter", | |
2091 | .sysc = &omap3xxx_counter_sysc, | |
2092 | }; | |
2093 | ||
2094 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2095 | .name = "counter_32k", | |
2096 | .class = &omap3xxx_counter_hwmod_class, | |
2097 | .clkdm_name = "wkup_clkdm", | |
2098 | .flags = HWMOD_SWSUP_SIDLE, | |
2099 | .main_clk = "wkup_32k_fck", | |
2100 | .prcm = { | |
2101 | .omap2 = { | |
2102 | .module_offs = WKUP_MOD, | |
2103 | .prcm_reg_id = 1, | |
2104 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2105 | .idlest_reg_id = 1, | |
2106 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2107 | }, | |
2108 | }, | |
2109 | }; | |
2110 | ||
49484a60 AM |
2111 | /* |
2112 | * 'gpmc' class | |
2113 | * general purpose memory controller | |
2114 | */ | |
2115 | ||
2116 | static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { | |
2117 | .rev_offs = 0x0000, | |
2118 | .sysc_offs = 0x0010, | |
2119 | .syss_offs = 0x0014, | |
2120 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2121 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2122 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2123 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2124 | }; | |
2125 | ||
2126 | static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { | |
2127 | .name = "gpmc", | |
2128 | .sysc = &omap3xxx_gpmc_sysc, | |
2129 | }; | |
2130 | ||
2131 | static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { | |
2132 | { .irq = 20 }, | |
2133 | { .irq = -1 } | |
2134 | }; | |
2135 | ||
2136 | static struct omap_hwmod omap3xxx_gpmc_hwmod = { | |
2137 | .name = "gpmc", | |
2138 | .class = &omap3xxx_gpmc_hwmod_class, | |
2139 | .clkdm_name = "core_l3_clkdm", | |
2140 | .mpu_irqs = omap3xxx_gpmc_irqs, | |
2141 | .main_clk = "gpmc_fck", | |
2142 | /* | |
2143 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP | |
2144 | * block. It is not being added due to any known bugs with | |
2145 | * resetting the GPMC IP block, but rather because any timings | |
2146 | * set by the bootloader are not being correctly programmed by | |
2147 | * the kernel from the board file or DT data. | |
2148 | * HWMOD_INIT_NO_RESET should be removed ASAP. | |
2149 | */ | |
2150 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | | |
2151 | HWMOD_NO_IDLEST), | |
2152 | }; | |
2153 | ||
844a3b63 PW |
2154 | /* |
2155 | * interfaces | |
2156 | */ | |
2157 | ||
2158 | /* L3 -> L4_CORE interface */ | |
2159 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2160 | .master = &omap3xxx_l3_main_hwmod, | |
2161 | .slave = &omap3xxx_l4_core_hwmod, | |
2162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2163 | }; |
2164 | ||
844a3b63 PW |
2165 | /* L3 -> L4_PER interface */ |
2166 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2167 | .master = &omap3xxx_l3_main_hwmod, | |
2168 | .slave = &omap3xxx_l4_per_hwmod, | |
2169 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2170 | }; |
2171 | ||
844a3b63 PW |
2172 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2173 | { | |
2174 | .pa_start = 0x68000000, | |
2175 | .pa_end = 0x6800ffff, | |
2176 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2177 | }, |
844a3b63 | 2178 | { } |
70034d38 VC |
2179 | }; |
2180 | ||
844a3b63 PW |
2181 | /* MPU -> L3 interface */ |
2182 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2183 | .master = &omap3xxx_mpu_hwmod, | |
2184 | .slave = &omap3xxx_l3_main_hwmod, | |
2185 | .addr = omap3xxx_l3_main_addrs, | |
2186 | .user = OCP_USER_MPU, | |
70034d38 VC |
2187 | }; |
2188 | ||
844a3b63 PW |
2189 | /* DSS -> l3 */ |
2190 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2191 | .master = &omap3430es1_dss_core_hwmod, | |
2192 | .slave = &omap3xxx_l3_main_hwmod, | |
2193 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2194 | }; |
2195 | ||
844a3b63 PW |
2196 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2197 | .master = &omap3xxx_dss_core_hwmod, | |
2198 | .slave = &omap3xxx_l3_main_hwmod, | |
2199 | .fw = { | |
70034d38 | 2200 | .omap2 = { |
844a3b63 PW |
2201 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2202 | .flags = OMAP_FIREWALL_L3, | |
2203 | } | |
70034d38 | 2204 | }, |
844a3b63 | 2205 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2206 | }; |
2207 | ||
844a3b63 PW |
2208 | /* l3_core -> usbhsotg interface */ |
2209 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2210 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2211 | .slave = &omap3xxx_l3_main_hwmod, |
2212 | .clk = "core_l3_ick", | |
844a3b63 | 2213 | .user = OCP_USER_MPU, |
01438ab6 MK |
2214 | }; |
2215 | ||
844a3b63 PW |
2216 | /* l3_core -> am35xx_usbhsotg interface */ |
2217 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2218 | .master = &am35xx_usbhsotg_hwmod, | |
2219 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2220 | .clk = "hsotgusb_ick", |
844a3b63 | 2221 | .user = OCP_USER_MPU, |
01438ab6 | 2222 | }; |
89ea2583 | 2223 | |
8f993a01 TK |
2224 | /* l3_core -> sad2d interface */ |
2225 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
2226 | .master = &omap3xxx_sad2d_hwmod, | |
2227 | .slave = &omap3xxx_l3_main_hwmod, | |
2228 | .clk = "core_l3_ick", | |
2229 | .user = OCP_USER_MPU, | |
2230 | }; | |
2231 | ||
844a3b63 PW |
2232 | /* L4_CORE -> L4_WKUP interface */ |
2233 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2234 | .master = &omap3xxx_l4_core_hwmod, | |
2235 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2237 | }; |
2238 | ||
844a3b63 PW |
2239 | /* L4 CORE -> MMC1 interface */ |
2240 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2241 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2242 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2243 | .clk = "mmchs1_ick", | |
2244 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2245 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2246 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2247 | }; |
2248 | ||
844a3b63 PW |
2249 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2250 | .master = &omap3xxx_l4_core_hwmod, | |
2251 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2252 | .clk = "mmchs1_ick", | |
2253 | .addr = omap2430_mmc1_addr_space, | |
2254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2255 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2256 | }; |
2257 | ||
844a3b63 PW |
2258 | /* L4 CORE -> MMC2 interface */ |
2259 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2260 | .master = &omap3xxx_l4_core_hwmod, | |
2261 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2262 | .clk = "mmchs2_ick", | |
2263 | .addr = omap2430_mmc2_addr_space, | |
2264 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2265 | .flags = OMAP_FIREWALL_L4 | |
2266 | }; | |
70034d38 | 2267 | |
844a3b63 PW |
2268 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2269 | .master = &omap3xxx_l4_core_hwmod, | |
2270 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2271 | .clk = "mmchs2_ick", | |
2272 | .addr = omap2430_mmc2_addr_space, | |
2273 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2274 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2275 | }; |
2276 | ||
844a3b63 PW |
2277 | /* L4 CORE -> MMC3 interface */ |
2278 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2279 | { | |
2280 | .pa_start = 0x480ad000, | |
2281 | .pa_end = 0x480ad1ff, | |
2282 | .flags = ADDR_TYPE_RT, | |
2283 | }, | |
2284 | { } | |
70034d38 VC |
2285 | }; |
2286 | ||
844a3b63 PW |
2287 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2288 | .master = &omap3xxx_l4_core_hwmod, | |
2289 | .slave = &omap3xxx_mmc3_hwmod, | |
2290 | .clk = "mmchs3_ick", | |
2291 | .addr = omap3xxx_mmc3_addr_space, | |
2292 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2293 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2294 | }; |
2295 | ||
844a3b63 PW |
2296 | /* L4 CORE -> UART1 interface */ |
2297 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2298 | { |
844a3b63 PW |
2299 | .pa_start = OMAP3_UART1_BASE, |
2300 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2301 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2302 | }, |
78183f3f | 2303 | { } |
70034d38 VC |
2304 | }; |
2305 | ||
844a3b63 | 2306 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2307 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2308 | .slave = &omap3xxx_uart1_hwmod, |
2309 | .clk = "uart1_ick", | |
2310 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2311 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2312 | }; |
2313 | ||
844a3b63 PW |
2314 | /* L4 CORE -> UART2 interface */ |
2315 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2316 | { | |
2317 | .pa_start = OMAP3_UART2_BASE, | |
2318 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2319 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2320 | }, |
844a3b63 | 2321 | { } |
70034d38 VC |
2322 | }; |
2323 | ||
844a3b63 PW |
2324 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2325 | .master = &omap3xxx_l4_core_hwmod, | |
2326 | .slave = &omap3xxx_uart2_hwmod, | |
2327 | .clk = "uart2_ick", | |
2328 | .addr = omap3xxx_uart2_addr_space, | |
2329 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2330 | }; |
2331 | ||
844a3b63 PW |
2332 | /* L4 PER -> UART3 interface */ |
2333 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2334 | { |
844a3b63 PW |
2335 | .pa_start = OMAP3_UART3_BASE, |
2336 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2337 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2338 | }, |
78183f3f | 2339 | { } |
70034d38 VC |
2340 | }; |
2341 | ||
844a3b63 | 2342 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2343 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2344 | .slave = &omap3xxx_uart3_hwmod, |
2345 | .clk = "uart3_ick", | |
2346 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2347 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2348 | }; |
2349 | ||
844a3b63 PW |
2350 | /* L4 PER -> UART4 interface */ |
2351 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2352 | { | |
2353 | .pa_start = OMAP3_UART4_BASE, | |
2354 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2355 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2356 | }, |
844a3b63 | 2357 | { } |
70034d38 VC |
2358 | }; |
2359 | ||
844a3b63 PW |
2360 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2361 | .master = &omap3xxx_l4_per_hwmod, | |
2362 | .slave = &omap36xx_uart4_hwmod, | |
2363 | .clk = "uart4_ick", | |
2364 | .addr = omap36xx_uart4_addr_space, | |
2365 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2366 | }; |
2367 | ||
844a3b63 PW |
2368 | /* AM35xx: L4 CORE -> UART4 interface */ |
2369 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2370 | { |
844a3b63 PW |
2371 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2372 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2373 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2374 | }, |
bf765237 | 2375 | { } |
70034d38 VC |
2376 | }; |
2377 | ||
844a3b63 PW |
2378 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2379 | .master = &omap3xxx_l4_core_hwmod, | |
2380 | .slave = &am35xx_uart4_hwmod, | |
2381 | .clk = "uart4_ick", | |
2382 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2383 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2384 | }; | |
2385 | ||
844a3b63 PW |
2386 | /* L4 CORE -> I2C1 interface */ |
2387 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2388 | .master = &omap3xxx_l4_core_hwmod, | |
2389 | .slave = &omap3xxx_i2c1_hwmod, | |
2390 | .clk = "i2c1_ick", | |
2391 | .addr = omap2_i2c1_addr_space, | |
2392 | .fw = { | |
2393 | .omap2 = { | |
2394 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2395 | .l4_prot_group = 7, | |
2396 | .flags = OMAP_FIREWALL_L4, | |
2397 | } | |
2398 | }, | |
2399 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2400 | }; |
2401 | ||
844a3b63 PW |
2402 | /* L4 CORE -> I2C2 interface */ |
2403 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2404 | .master = &omap3xxx_l4_core_hwmod, | |
2405 | .slave = &omap3xxx_i2c2_hwmod, | |
2406 | .clk = "i2c2_ick", | |
2407 | .addr = omap2_i2c2_addr_space, | |
2408 | .fw = { | |
70034d38 | 2409 | .omap2 = { |
844a3b63 PW |
2410 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2411 | .l4_prot_group = 7, | |
2412 | .flags = OMAP_FIREWALL_L4, | |
2413 | } | |
70034d38 | 2414 | }, |
844a3b63 | 2415 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2416 | }; |
2417 | ||
844a3b63 PW |
2418 | /* L4 CORE -> I2C3 interface */ |
2419 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2420 | { | |
2421 | .pa_start = 0x48060000, | |
2422 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2423 | .flags = ADDR_TYPE_RT, | |
2424 | }, | |
2425 | { } | |
70034d38 VC |
2426 | }; |
2427 | ||
844a3b63 PW |
2428 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2429 | .master = &omap3xxx_l4_core_hwmod, | |
2430 | .slave = &omap3xxx_i2c3_hwmod, | |
2431 | .clk = "i2c3_ick", | |
2432 | .addr = omap3xxx_i2c3_addr_space, | |
2433 | .fw = { | |
2434 | .omap2 = { | |
2435 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2436 | .l4_prot_group = 7, | |
2437 | .flags = OMAP_FIREWALL_L4, | |
2438 | } | |
2439 | }, | |
2440 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2441 | }; |
2442 | ||
844a3b63 PW |
2443 | /* L4 CORE -> SR1 interface */ |
2444 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2445 | { |
844a3b63 PW |
2446 | .pa_start = OMAP34XX_SR1_BASE, |
2447 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2448 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2449 | }, |
78183f3f | 2450 | { } |
70034d38 VC |
2451 | }; |
2452 | ||
844a3b63 PW |
2453 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2454 | .master = &omap3xxx_l4_core_hwmod, | |
2455 | .slave = &omap34xx_sr1_hwmod, | |
2456 | .clk = "sr_l4_ick", | |
2457 | .addr = omap3_sr1_addr_space, | |
2458 | .user = OCP_USER_MPU, | |
70034d38 VC |
2459 | }; |
2460 | ||
844a3b63 PW |
2461 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2462 | .master = &omap3xxx_l4_core_hwmod, | |
2463 | .slave = &omap36xx_sr1_hwmod, | |
2464 | .clk = "sr_l4_ick", | |
2465 | .addr = omap3_sr1_addr_space, | |
2466 | .user = OCP_USER_MPU, | |
2467 | }; | |
2468 | ||
2469 | /* L4 CORE -> SR1 interface */ | |
2470 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2471 | { | |
2472 | .pa_start = OMAP34XX_SR2_BASE, | |
2473 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2474 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2475 | }, |
844a3b63 | 2476 | { } |
70034d38 VC |
2477 | }; |
2478 | ||
844a3b63 PW |
2479 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2480 | .master = &omap3xxx_l4_core_hwmod, | |
2481 | .slave = &omap34xx_sr2_hwmod, | |
2482 | .clk = "sr_l4_ick", | |
2483 | .addr = omap3_sr2_addr_space, | |
2484 | .user = OCP_USER_MPU, | |
70034d38 VC |
2485 | }; |
2486 | ||
844a3b63 PW |
2487 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2488 | .master = &omap3xxx_l4_core_hwmod, | |
2489 | .slave = &omap36xx_sr2_hwmod, | |
2490 | .clk = "sr_l4_ick", | |
2491 | .addr = omap3_sr2_addr_space, | |
2492 | .user = OCP_USER_MPU, | |
70034d38 VC |
2493 | }; |
2494 | ||
844a3b63 | 2495 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2496 | { |
844a3b63 PW |
2497 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2498 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2499 | .flags = ADDR_TYPE_RT |
2500 | }, | |
78183f3f | 2501 | { } |
70034d38 VC |
2502 | }; |
2503 | ||
844a3b63 PW |
2504 | /* l4_core -> usbhsotg */ |
2505 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2506 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2507 | .slave = &omap3xxx_usbhsotg_hwmod, |
2508 | .clk = "l4_ick", | |
2509 | .addr = omap3xxx_usbhsotg_addrs, | |
2510 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2511 | }; |
2512 | ||
844a3b63 PW |
2513 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2514 | { | |
2515 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2516 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2517 | .flags = ADDR_TYPE_RT | |
70034d38 | 2518 | }, |
844a3b63 | 2519 | { } |
70034d38 VC |
2520 | }; |
2521 | ||
844a3b63 PW |
2522 | /* l4_core -> usbhsotg */ |
2523 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2524 | .master = &omap3xxx_l4_core_hwmod, | |
2525 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2526 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2527 | .addr = am35xx_usbhsotg_addrs, |
2528 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2529 | }; |
2530 | ||
844a3b63 PW |
2531 | /* L4_WKUP -> L4_SEC interface */ |
2532 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2533 | .master = &omap3xxx_l4_wkup_hwmod, | |
2534 | .slave = &omap3xxx_l4_sec_hwmod, | |
2535 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2536 | }; |
2537 | ||
844a3b63 PW |
2538 | /* IVA2 <- L3 interface */ |
2539 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2540 | .master = &omap3xxx_l3_main_hwmod, | |
2541 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2542 | .clk = "core_l3_ick", |
844a3b63 | 2543 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2544 | }; |
2545 | ||
844a3b63 | 2546 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2547 | { |
844a3b63 PW |
2548 | .pa_start = 0x48318000, |
2549 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2550 | .flags = ADDR_TYPE_RT |
2551 | }, | |
78183f3f | 2552 | { } |
01438ab6 MK |
2553 | }; |
2554 | ||
844a3b63 PW |
2555 | /* l4_wkup -> timer1 */ |
2556 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2557 | .master = &omap3xxx_l4_wkup_hwmod, | |
2558 | .slave = &omap3xxx_timer1_hwmod, | |
2559 | .clk = "gpt1_ick", | |
2560 | .addr = omap3xxx_timer1_addrs, | |
2561 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2562 | }; |
2563 | ||
844a3b63 PW |
2564 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2565 | { | |
2566 | .pa_start = 0x49032000, | |
2567 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2568 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2569 | }, |
844a3b63 | 2570 | { } |
01438ab6 MK |
2571 | }; |
2572 | ||
844a3b63 PW |
2573 | /* l4_per -> timer2 */ |
2574 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2575 | .master = &omap3xxx_l4_per_hwmod, | |
2576 | .slave = &omap3xxx_timer2_hwmod, | |
2577 | .clk = "gpt2_ick", | |
2578 | .addr = omap3xxx_timer2_addrs, | |
2579 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2580 | }; |
2581 | ||
844a3b63 | 2582 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2583 | { |
844a3b63 PW |
2584 | .pa_start = 0x49034000, |
2585 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2586 | .flags = ADDR_TYPE_RT |
2587 | }, | |
78183f3f | 2588 | { } |
01438ab6 MK |
2589 | }; |
2590 | ||
844a3b63 PW |
2591 | /* l4_per -> timer3 */ |
2592 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2593 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2594 | .slave = &omap3xxx_timer3_hwmod, |
2595 | .clk = "gpt3_ick", | |
2596 | .addr = omap3xxx_timer3_addrs, | |
2597 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2598 | }; |
2599 | ||
844a3b63 PW |
2600 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2601 | { | |
2602 | .pa_start = 0x49036000, | |
2603 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2604 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2605 | }, |
844a3b63 | 2606 | { } |
01438ab6 MK |
2607 | }; |
2608 | ||
844a3b63 PW |
2609 | /* l4_per -> timer4 */ |
2610 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2611 | .master = &omap3xxx_l4_per_hwmod, | |
2612 | .slave = &omap3xxx_timer4_hwmod, | |
2613 | .clk = "gpt4_ick", | |
2614 | .addr = omap3xxx_timer4_addrs, | |
2615 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2616 | }; |
2617 | ||
844a3b63 PW |
2618 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2619 | { | |
2620 | .pa_start = 0x49038000, | |
2621 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2622 | .flags = ADDR_TYPE_RT | |
2623 | }, | |
2624 | { } | |
d3442726 TG |
2625 | }; |
2626 | ||
844a3b63 PW |
2627 | /* l4_per -> timer5 */ |
2628 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2629 | .master = &omap3xxx_l4_per_hwmod, | |
2630 | .slave = &omap3xxx_timer5_hwmod, | |
2631 | .clk = "gpt5_ick", | |
2632 | .addr = omap3xxx_timer5_addrs, | |
2633 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2634 | }; |
2635 | ||
844a3b63 PW |
2636 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2637 | { | |
2638 | .pa_start = 0x4903A000, | |
2639 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2640 | .flags = ADDR_TYPE_RT | |
2641 | }, | |
2642 | { } | |
cea6b942 SG |
2643 | }; |
2644 | ||
844a3b63 PW |
2645 | /* l4_per -> timer6 */ |
2646 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2647 | .master = &omap3xxx_l4_per_hwmod, | |
2648 | .slave = &omap3xxx_timer6_hwmod, | |
2649 | .clk = "gpt6_ick", | |
2650 | .addr = omap3xxx_timer6_addrs, | |
2651 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2652 | }; |
2653 | ||
844a3b63 PW |
2654 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2655 | { | |
2656 | .pa_start = 0x4903C000, | |
2657 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2658 | .flags = ADDR_TYPE_RT | |
d3442726 | 2659 | }, |
844a3b63 | 2660 | { } |
d3442726 TG |
2661 | }; |
2662 | ||
844a3b63 PW |
2663 | /* l4_per -> timer7 */ |
2664 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2665 | .master = &omap3xxx_l4_per_hwmod, | |
2666 | .slave = &omap3xxx_timer7_hwmod, | |
2667 | .clk = "gpt7_ick", | |
2668 | .addr = omap3xxx_timer7_addrs, | |
2669 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2670 | }; |
2671 | ||
844a3b63 PW |
2672 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2673 | { | |
2674 | .pa_start = 0x4903E000, | |
2675 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2676 | .flags = ADDR_TYPE_RT | |
d3442726 | 2677 | }, |
844a3b63 | 2678 | { } |
d3442726 TG |
2679 | }; |
2680 | ||
844a3b63 PW |
2681 | /* l4_per -> timer8 */ |
2682 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2683 | .master = &omap3xxx_l4_per_hwmod, | |
2684 | .slave = &omap3xxx_timer8_hwmod, | |
2685 | .clk = "gpt8_ick", | |
2686 | .addr = omap3xxx_timer8_addrs, | |
2687 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2688 | }; |
2689 | ||
844a3b63 PW |
2690 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2691 | { | |
2692 | .pa_start = 0x49040000, | |
2693 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2694 | .flags = ADDR_TYPE_RT | |
2695 | }, | |
2696 | { } | |
2697 | }; | |
0f9dfdd3 | 2698 | |
844a3b63 PW |
2699 | /* l4_per -> timer9 */ |
2700 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2701 | .master = &omap3xxx_l4_per_hwmod, | |
2702 | .slave = &omap3xxx_timer9_hwmod, | |
2703 | .clk = "gpt9_ick", | |
2704 | .addr = omap3xxx_timer9_addrs, | |
2705 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2706 | }; |
2707 | ||
844a3b63 PW |
2708 | /* l4_core -> timer10 */ |
2709 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2710 | .master = &omap3xxx_l4_core_hwmod, | |
2711 | .slave = &omap3xxx_timer10_hwmod, | |
2712 | .clk = "gpt10_ick", | |
2713 | .addr = omap2_timer10_addrs, | |
2714 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2715 | }; |
2716 | ||
844a3b63 PW |
2717 | /* l4_core -> timer11 */ |
2718 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2719 | .master = &omap3xxx_l4_core_hwmod, | |
2720 | .slave = &omap3xxx_timer11_hwmod, | |
2721 | .clk = "gpt11_ick", | |
2722 | .addr = omap2_timer11_addrs, | |
2723 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2724 | }; |
2725 | ||
844a3b63 | 2726 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2727 | { |
844a3b63 PW |
2728 | .pa_start = 0x48304000, |
2729 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2730 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2731 | }, |
78183f3f | 2732 | { } |
0f9dfdd3 FC |
2733 | }; |
2734 | ||
844a3b63 PW |
2735 | /* l4_core -> timer12 */ |
2736 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2737 | .master = &omap3xxx_l4_sec_hwmod, | |
2738 | .slave = &omap3xxx_timer12_hwmod, | |
2739 | .clk = "gpt12_ick", | |
2740 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2741 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2742 | }; | |
2743 | ||
844a3b63 PW |
2744 | /* l4_wkup -> wd_timer2 */ |
2745 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2746 | { | |
2747 | .pa_start = 0x48314000, | |
2748 | .pa_end = 0x4831407f, | |
2749 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2750 | }, |
844a3b63 | 2751 | { } |
0f9dfdd3 FC |
2752 | }; |
2753 | ||
844a3b63 PW |
2754 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2755 | .master = &omap3xxx_l4_wkup_hwmod, | |
2756 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2757 | .clk = "wdt2_ick", | |
2758 | .addr = omap3xxx_wd_timer2_addrs, | |
2759 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2760 | }; | |
2761 | ||
2762 | /* l4_core -> dss */ | |
2763 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2764 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2765 | .slave = &omap3430es1_dss_core_hwmod, |
2766 | .clk = "dss_ick", | |
2767 | .addr = omap2_dss_addrs, | |
2768 | .fw = { | |
2769 | .omap2 = { | |
2770 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2771 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2772 | .flags = OMAP_FIREWALL_L4, | |
2773 | } | |
2774 | }, | |
0f616a4e C |
2775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2776 | }; | |
2777 | ||
844a3b63 | 2778 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2779 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2780 | .slave = &omap3xxx_dss_core_hwmod, |
2781 | .clk = "dss_ick", | |
2782 | .addr = omap2_dss_addrs, | |
2783 | .fw = { | |
2784 | .omap2 = { | |
2785 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2786 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2787 | .flags = OMAP_FIREWALL_L4, | |
2788 | } | |
2789 | }, | |
0f616a4e C |
2790 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2791 | }; | |
2792 | ||
844a3b63 PW |
2793 | /* l4_core -> dss_dispc */ |
2794 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2795 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2796 | .slave = &omap3xxx_dss_dispc_hwmod, |
2797 | .clk = "dss_ick", | |
2798 | .addr = omap2_dss_dispc_addrs, | |
2799 | .fw = { | |
2800 | .omap2 = { | |
2801 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2802 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2803 | .flags = OMAP_FIREWALL_L4, | |
2804 | } | |
2805 | }, | |
0f616a4e C |
2806 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2807 | }; | |
2808 | ||
844a3b63 | 2809 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2810 | { |
844a3b63 PW |
2811 | .pa_start = 0x4804FC00, |
2812 | .pa_end = 0x4804FFFF, | |
2813 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2814 | }, |
78183f3f | 2815 | { } |
0f616a4e C |
2816 | }; |
2817 | ||
844a3b63 PW |
2818 | /* l4_core -> dss_dsi1 */ |
2819 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2820 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2821 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2822 | .clk = "dss_ick", | |
2823 | .addr = omap3xxx_dss_dsi1_addrs, | |
2824 | .fw = { | |
2825 | .omap2 = { | |
2826 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2827 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2828 | .flags = OMAP_FIREWALL_L4, | |
2829 | } | |
2830 | }, | |
0f616a4e C |
2831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2832 | }; | |
2833 | ||
844a3b63 PW |
2834 | /* l4_core -> dss_rfbi */ |
2835 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2836 | .master = &omap3xxx_l4_core_hwmod, | |
2837 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2838 | .clk = "dss_ick", | |
2839 | .addr = omap2_dss_rfbi_addrs, | |
2840 | .fw = { | |
0f616a4e | 2841 | .omap2 = { |
844a3b63 PW |
2842 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2843 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2844 | .flags = OMAP_FIREWALL_L4, | |
2845 | } | |
0f616a4e | 2846 | }, |
844a3b63 | 2847 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2848 | }; |
2849 | ||
844a3b63 PW |
2850 | /* l4_core -> dss_venc */ |
2851 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2852 | .master = &omap3xxx_l4_core_hwmod, | |
2853 | .slave = &omap3xxx_dss_venc_hwmod, | |
2854 | .clk = "dss_ick", | |
2855 | .addr = omap2_dss_venc_addrs, | |
2856 | .fw = { | |
70034d38 | 2857 | .omap2 = { |
844a3b63 PW |
2858 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2859 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2860 | .flags = OMAP_FIREWALL_L4, | |
2861 | } | |
70034d38 | 2862 | }, |
844a3b63 PW |
2863 | .flags = OCPIF_SWSUP_IDLE, |
2864 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2865 | }; |
2866 | ||
844a3b63 PW |
2867 | /* l4_wkup -> gpio1 */ |
2868 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2869 | { | |
2870 | .pa_start = 0x48310000, | |
2871 | .pa_end = 0x483101ff, | |
2872 | .flags = ADDR_TYPE_RT | |
2873 | }, | |
2874 | { } | |
70034d38 VC |
2875 | }; |
2876 | ||
844a3b63 PW |
2877 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2878 | .master = &omap3xxx_l4_wkup_hwmod, | |
2879 | .slave = &omap3xxx_gpio1_hwmod, | |
2880 | .addr = omap3xxx_gpio1_addrs, | |
2881 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2882 | }; |
2883 | ||
844a3b63 PW |
2884 | /* l4_per -> gpio2 */ |
2885 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2886 | { | |
2887 | .pa_start = 0x49050000, | |
2888 | .pa_end = 0x490501ff, | |
2889 | .flags = ADDR_TYPE_RT | |
70034d38 | 2890 | }, |
844a3b63 | 2891 | { } |
70034d38 VC |
2892 | }; |
2893 | ||
844a3b63 PW |
2894 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2895 | .master = &omap3xxx_l4_per_hwmod, | |
2896 | .slave = &omap3xxx_gpio2_hwmod, | |
2897 | .addr = omap3xxx_gpio2_addrs, | |
2898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2899 | }; |
2900 | ||
844a3b63 PW |
2901 | /* l4_per -> gpio3 */ |
2902 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2903 | { | |
2904 | .pa_start = 0x49052000, | |
2905 | .pa_end = 0x490521ff, | |
2906 | .flags = ADDR_TYPE_RT | |
2907 | }, | |
2908 | { } | |
70034d38 VC |
2909 | }; |
2910 | ||
844a3b63 PW |
2911 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2912 | .master = &omap3xxx_l4_per_hwmod, | |
2913 | .slave = &omap3xxx_gpio3_hwmod, | |
2914 | .addr = omap3xxx_gpio3_addrs, | |
2915 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2916 | }; |
2917 | ||
5486474c PW |
2918 | /* |
2919 | * 'mmu' class | |
2920 | * The memory management unit performs virtual to physical address translation | |
2921 | * for its requestors. | |
2922 | */ | |
2923 | ||
2924 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2925 | .rev_offs = 0x000, | |
2926 | .sysc_offs = 0x010, | |
2927 | .syss_offs = 0x014, | |
2928 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2929 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2930 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2931 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2932 | }; | |
2933 | ||
2934 | static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { | |
2935 | .name = "mmu", | |
2936 | .sysc = &mmu_sysc, | |
2937 | }; | |
2938 | ||
2939 | /* mmu isp */ | |
2940 | ||
2941 | static struct omap_mmu_dev_attr mmu_isp_dev_attr = { | |
2942 | .da_start = 0x0, | |
2943 | .da_end = 0xfffff000, | |
2944 | .nr_tlb_entries = 8, | |
2945 | }; | |
2946 | ||
2947 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod; | |
2948 | static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { | |
2949 | { .irq = 24 }, | |
2950 | { .irq = -1 } | |
2951 | }; | |
2952 | ||
2953 | static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { | |
2954 | { | |
2955 | .pa_start = 0x480bd400, | |
2956 | .pa_end = 0x480bd47f, | |
2957 | .flags = ADDR_TYPE_RT, | |
2958 | }, | |
2959 | { } | |
2960 | }; | |
2961 | ||
2962 | /* l4_core -> mmu isp */ | |
2963 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { | |
2964 | .master = &omap3xxx_l4_core_hwmod, | |
2965 | .slave = &omap3xxx_mmu_isp_hwmod, | |
2966 | .addr = omap3xxx_mmu_isp_addrs, | |
2967 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2968 | }; | |
2969 | ||
2970 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |
2971 | .name = "mmu_isp", | |
2972 | .class = &omap3xxx_mmu_hwmod_class, | |
2973 | .mpu_irqs = omap3xxx_mmu_isp_irqs, | |
2974 | .main_clk = "cam_ick", | |
2975 | .dev_attr = &mmu_isp_dev_attr, | |
2976 | .flags = HWMOD_NO_IDLEST, | |
2977 | }; | |
2978 | ||
2979 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
2980 | ||
2981 | /* mmu iva */ | |
2982 | ||
2983 | static struct omap_mmu_dev_attr mmu_iva_dev_attr = { | |
2984 | .da_start = 0x11000000, | |
2985 | .da_end = 0xfffff000, | |
2986 | .nr_tlb_entries = 32, | |
2987 | }; | |
2988 | ||
2989 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod; | |
2990 | static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { | |
2991 | { .irq = 28 }, | |
2992 | { .irq = -1 } | |
2993 | }; | |
2994 | ||
2995 | static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { | |
2996 | { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, | |
2997 | }; | |
2998 | ||
2999 | static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { | |
3000 | { | |
3001 | .pa_start = 0x5d000000, | |
3002 | .pa_end = 0x5d00007f, | |
3003 | .flags = ADDR_TYPE_RT, | |
3004 | }, | |
3005 | { } | |
3006 | }; | |
3007 | ||
3008 | /* l3_main -> iva mmu */ | |
3009 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { | |
3010 | .master = &omap3xxx_l3_main_hwmod, | |
3011 | .slave = &omap3xxx_mmu_iva_hwmod, | |
3012 | .addr = omap3xxx_mmu_iva_addrs, | |
3013 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3014 | }; | |
3015 | ||
3016 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |
3017 | .name = "mmu_iva", | |
3018 | .class = &omap3xxx_mmu_hwmod_class, | |
3019 | .mpu_irqs = omap3xxx_mmu_iva_irqs, | |
3020 | .rst_lines = omap3xxx_mmu_iva_resets, | |
3021 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | |
3022 | .main_clk = "iva2_ck", | |
3023 | .prcm = { | |
3024 | .omap2 = { | |
3025 | .module_offs = OMAP3430_IVA2_MOD, | |
3026 | }, | |
3027 | }, | |
3028 | .dev_attr = &mmu_iva_dev_attr, | |
3029 | .flags = HWMOD_NO_IDLEST, | |
3030 | }; | |
3031 | ||
3032 | #endif | |
3033 | ||
844a3b63 PW |
3034 | /* l4_per -> gpio4 */ |
3035 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
3036 | { | |
3037 | .pa_start = 0x49054000, | |
3038 | .pa_end = 0x490541ff, | |
3039 | .flags = ADDR_TYPE_RT | |
70034d38 | 3040 | }, |
844a3b63 | 3041 | { } |
70034d38 VC |
3042 | }; |
3043 | ||
844a3b63 PW |
3044 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
3045 | .master = &omap3xxx_l4_per_hwmod, | |
3046 | .slave = &omap3xxx_gpio4_hwmod, | |
3047 | .addr = omap3xxx_gpio4_addrs, | |
3048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3049 | }; |
3050 | ||
844a3b63 PW |
3051 | /* l4_per -> gpio5 */ |
3052 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
3053 | { | |
3054 | .pa_start = 0x49056000, | |
3055 | .pa_end = 0x490561ff, | |
3056 | .flags = ADDR_TYPE_RT | |
3057 | }, | |
3058 | { } | |
01438ab6 MK |
3059 | }; |
3060 | ||
844a3b63 PW |
3061 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
3062 | .master = &omap3xxx_l4_per_hwmod, | |
3063 | .slave = &omap3xxx_gpio5_hwmod, | |
3064 | .addr = omap3xxx_gpio5_addrs, | |
3065 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3066 | }; |
3067 | ||
844a3b63 PW |
3068 | /* l4_per -> gpio6 */ |
3069 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
3070 | { | |
3071 | .pa_start = 0x49058000, | |
3072 | .pa_end = 0x490581ff, | |
3073 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3074 | }, |
844a3b63 | 3075 | { } |
01438ab6 MK |
3076 | }; |
3077 | ||
844a3b63 PW |
3078 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
3079 | .master = &omap3xxx_l4_per_hwmod, | |
3080 | .slave = &omap3xxx_gpio6_hwmod, | |
3081 | .addr = omap3xxx_gpio6_addrs, | |
3082 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3083 | }; |
3084 | ||
844a3b63 PW |
3085 | /* dma_system -> L3 */ |
3086 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
3087 | .master = &omap3xxx_dma_system_hwmod, | |
3088 | .slave = &omap3xxx_l3_main_hwmod, | |
3089 | .clk = "core_l3_ick", | |
3090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3091 | }; |
3092 | ||
844a3b63 PW |
3093 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
3094 | { | |
3095 | .pa_start = 0x48056000, | |
3096 | .pa_end = 0x48056fff, | |
3097 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3098 | }, |
844a3b63 | 3099 | { } |
01438ab6 MK |
3100 | }; |
3101 | ||
844a3b63 PW |
3102 | /* l4_cfg -> dma_system */ |
3103 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
3104 | .master = &omap3xxx_l4_core_hwmod, | |
3105 | .slave = &omap3xxx_dma_system_hwmod, | |
3106 | .clk = "core_l4_ick", | |
3107 | .addr = omap3xxx_dma_system_addrs, | |
3108 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3109 | }; |
3110 | ||
844a3b63 PW |
3111 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
3112 | { | |
3113 | .name = "mpu", | |
3114 | .pa_start = 0x48074000, | |
3115 | .pa_end = 0x480740ff, | |
3116 | .flags = ADDR_TYPE_RT | |
3117 | }, | |
3118 | { } | |
d3442726 TG |
3119 | }; |
3120 | ||
844a3b63 PW |
3121 | /* l4_core -> mcbsp1 */ |
3122 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
3123 | .master = &omap3xxx_l4_core_hwmod, | |
3124 | .slave = &omap3xxx_mcbsp1_hwmod, | |
3125 | .clk = "mcbsp1_ick", | |
3126 | .addr = omap3xxx_mcbsp1_addrs, | |
3127 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3128 | }; |
3129 | ||
844a3b63 PW |
3130 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
3131 | { | |
3132 | .name = "mpu", | |
3133 | .pa_start = 0x49022000, | |
3134 | .pa_end = 0x490220ff, | |
3135 | .flags = ADDR_TYPE_RT | |
3136 | }, | |
3137 | { } | |
d3442726 TG |
3138 | }; |
3139 | ||
844a3b63 PW |
3140 | /* l4_per -> mcbsp2 */ |
3141 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
3142 | .master = &omap3xxx_l4_per_hwmod, | |
3143 | .slave = &omap3xxx_mcbsp2_hwmod, | |
3144 | .clk = "mcbsp2_ick", | |
3145 | .addr = omap3xxx_mcbsp2_addrs, | |
3146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3147 | }; |
3148 | ||
844a3b63 PW |
3149 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
3150 | { | |
3151 | .name = "mpu", | |
3152 | .pa_start = 0x49024000, | |
3153 | .pa_end = 0x490240ff, | |
3154 | .flags = ADDR_TYPE_RT | |
3155 | }, | |
3156 | { } | |
d3442726 TG |
3157 | }; |
3158 | ||
844a3b63 PW |
3159 | /* l4_per -> mcbsp3 */ |
3160 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
3161 | .master = &omap3xxx_l4_per_hwmod, | |
3162 | .slave = &omap3xxx_mcbsp3_hwmod, | |
3163 | .clk = "mcbsp3_ick", | |
3164 | .addr = omap3xxx_mcbsp3_addrs, | |
3165 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
3166 | }; |
3167 | ||
844a3b63 PW |
3168 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
3169 | { | |
3170 | .name = "mpu", | |
3171 | .pa_start = 0x49026000, | |
3172 | .pa_end = 0x490260ff, | |
3173 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 3174 | }, |
844a3b63 | 3175 | { } |
a52e2ab6 PW |
3176 | }; |
3177 | ||
844a3b63 PW |
3178 | /* l4_per -> mcbsp4 */ |
3179 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
3180 | .master = &omap3xxx_l4_per_hwmod, | |
3181 | .slave = &omap3xxx_mcbsp4_hwmod, | |
3182 | .clk = "mcbsp4_ick", | |
3183 | .addr = omap3xxx_mcbsp4_addrs, | |
3184 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3185 | }; |
3186 | ||
844a3b63 PW |
3187 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
3188 | { | |
3189 | .name = "mpu", | |
3190 | .pa_start = 0x48096000, | |
3191 | .pa_end = 0x480960ff, | |
3192 | .flags = ADDR_TYPE_RT | |
3193 | }, | |
3194 | { } | |
3195 | }; | |
b163605e | 3196 | |
844a3b63 PW |
3197 | /* l4_core -> mcbsp5 */ |
3198 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
3199 | .master = &omap3xxx_l4_core_hwmod, | |
3200 | .slave = &omap3xxx_mcbsp5_hwmod, | |
3201 | .clk = "mcbsp5_ick", | |
3202 | .addr = omap3xxx_mcbsp5_addrs, | |
3203 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3204 | }; |
3205 | ||
844a3b63 PW |
3206 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
3207 | { | |
3208 | .name = "sidetone", | |
3209 | .pa_start = 0x49028000, | |
3210 | .pa_end = 0x490280ff, | |
3211 | .flags = ADDR_TYPE_RT | |
3212 | }, | |
3213 | { } | |
d3442726 TG |
3214 | }; |
3215 | ||
844a3b63 PW |
3216 | /* l4_per -> mcbsp2_sidetone */ |
3217 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
3218 | .master = &omap3xxx_l4_per_hwmod, | |
3219 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
3220 | .clk = "mcbsp2_ick", | |
3221 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
3222 | .user = OCP_USER_MPU, | |
b163605e PW |
3223 | }; |
3224 | ||
844a3b63 PW |
3225 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
3226 | { | |
3227 | .name = "sidetone", | |
3228 | .pa_start = 0x4902A000, | |
3229 | .pa_end = 0x4902A0ff, | |
3230 | .flags = ADDR_TYPE_RT | |
3231 | }, | |
3232 | { } | |
a52e2ab6 PW |
3233 | }; |
3234 | ||
844a3b63 PW |
3235 | /* l4_per -> mcbsp3_sidetone */ |
3236 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
3237 | .master = &omap3xxx_l4_per_hwmod, | |
3238 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
3239 | .clk = "mcbsp3_ick", | |
3240 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
3241 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
3242 | }; |
3243 | ||
844a3b63 PW |
3244 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
3245 | { | |
3246 | .pa_start = 0x48094000, | |
3247 | .pa_end = 0x480941ff, | |
3248 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3249 | }, |
844a3b63 | 3250 | { } |
d3442726 TG |
3251 | }; |
3252 | ||
844a3b63 PW |
3253 | /* l4_core -> mailbox */ |
3254 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3255 | .master = &omap3xxx_l4_core_hwmod, | |
3256 | .slave = &omap3xxx_mailbox_hwmod, | |
3257 | .addr = omap3xxx_mailbox_addrs, | |
3258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3259 | }; | |
b163605e | 3260 | |
844a3b63 PW |
3261 | /* l4 core -> mcspi1 interface */ |
3262 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3263 | .master = &omap3xxx_l4_core_hwmod, | |
3264 | .slave = &omap34xx_mcspi1, | |
3265 | .clk = "mcspi1_ick", | |
3266 | .addr = omap2_mcspi1_addr_space, | |
3267 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3268 | }; |
3269 | ||
844a3b63 PW |
3270 | /* l4 core -> mcspi2 interface */ |
3271 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3272 | .master = &omap3xxx_l4_core_hwmod, | |
3273 | .slave = &omap34xx_mcspi2, | |
3274 | .clk = "mcspi2_ick", | |
3275 | .addr = omap2_mcspi2_addr_space, | |
3276 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3277 | }; |
3278 | ||
844a3b63 PW |
3279 | /* l4 core -> mcspi3 interface */ |
3280 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3281 | .master = &omap3xxx_l4_core_hwmod, | |
3282 | .slave = &omap34xx_mcspi3, | |
3283 | .clk = "mcspi3_ick", | |
3284 | .addr = omap2430_mcspi3_addr_space, | |
3285 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3286 | }; |
3287 | ||
844a3b63 PW |
3288 | /* l4 core -> mcspi4 interface */ |
3289 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3290 | { | |
3291 | .pa_start = 0x480ba000, | |
3292 | .pa_end = 0x480ba0ff, | |
3293 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3294 | }, |
844a3b63 PW |
3295 | { } |
3296 | }; | |
3297 | ||
3298 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3299 | .master = &omap3xxx_l4_core_hwmod, | |
3300 | .slave = &omap34xx_mcspi4, | |
3301 | .clk = "mcspi4_ick", | |
3302 | .addr = omap34xx_mcspi4_addr_space, | |
3303 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3304 | }; |
3305 | ||
de231388 KM |
3306 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3307 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3308 | .slave = &omap3xxx_l3_main_hwmod, | |
3309 | .clk = "core_l3_ick", | |
3310 | .user = OCP_USER_MPU, | |
3311 | }; | |
3312 | ||
de231388 KM |
3313 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3314 | { | |
3315 | .name = "uhh", | |
3316 | .pa_start = 0x48064000, | |
3317 | .pa_end = 0x480643ff, | |
3318 | .flags = ADDR_TYPE_RT | |
3319 | }, | |
3320 | { | |
3321 | .name = "ohci", | |
3322 | .pa_start = 0x48064400, | |
3323 | .pa_end = 0x480647ff, | |
3324 | }, | |
3325 | { | |
3326 | .name = "ehci", | |
3327 | .pa_start = 0x48064800, | |
3328 | .pa_end = 0x48064cff, | |
3329 | }, | |
3330 | {} | |
3331 | }; | |
3332 | ||
3333 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3334 | .master = &omap3xxx_l4_core_hwmod, | |
3335 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3336 | .clk = "usbhost_ick", | |
3337 | .addr = omap3xxx_usb_host_hs_addrs, | |
3338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3339 | }; | |
3340 | ||
de231388 KM |
3341 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3342 | { | |
3343 | .name = "tll", | |
3344 | .pa_start = 0x48062000, | |
3345 | .pa_end = 0x48062fff, | |
3346 | .flags = ADDR_TYPE_RT | |
3347 | }, | |
3348 | {} | |
3349 | }; | |
3350 | ||
3351 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3352 | .master = &omap3xxx_l4_core_hwmod, | |
3353 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3354 | .clk = "usbtll_ick", | |
3355 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3356 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3357 | }; | |
3358 | ||
45a4bb06 PW |
3359 | /* l4_core -> hdq1w interface */ |
3360 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3361 | .master = &omap3xxx_l4_core_hwmod, | |
3362 | .slave = &omap3xxx_hdq1w_hwmod, | |
3363 | .clk = "hdq_ick", | |
3364 | .addr = omap2_hdq1w_addr_space, | |
3365 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3366 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3367 | }; | |
3368 | ||
c8d82ff6 VH |
3369 | /* l4_wkup -> 32ksync_counter */ |
3370 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3371 | { | |
3372 | .pa_start = 0x48320000, | |
3373 | .pa_end = 0x4832001f, | |
3374 | .flags = ADDR_TYPE_RT | |
3375 | }, | |
3376 | { } | |
3377 | }; | |
3378 | ||
49484a60 AM |
3379 | static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { |
3380 | { | |
3381 | .pa_start = 0x6e000000, | |
3382 | .pa_end = 0x6e000fff, | |
3383 | .flags = ADDR_TYPE_RT | |
3384 | }, | |
3385 | { } | |
3386 | }; | |
3387 | ||
c8d82ff6 VH |
3388 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { |
3389 | .master = &omap3xxx_l4_wkup_hwmod, | |
3390 | .slave = &omap3xxx_counter_32k_hwmod, | |
3391 | .clk = "omap_32ksync_ick", | |
3392 | .addr = omap3xxx_counter_32k_addrs, | |
3393 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3394 | }; | |
3395 | ||
31ba8808 MG |
3396 | /* am35xx has Davinci MDIO & EMAC */ |
3397 | static struct omap_hwmod_class am35xx_mdio_class = { | |
3398 | .name = "davinci_mdio", | |
3399 | }; | |
3400 | ||
3401 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
3402 | .name = "davinci_mdio", | |
3403 | .class = &am35xx_mdio_class, | |
3404 | .flags = HWMOD_NO_IDLEST, | |
3405 | }; | |
3406 | ||
3407 | /* | |
3408 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3409 | * but this will probably require some additional hwmod core support, | |
3410 | * so is left as a future to-do item. | |
3411 | */ | |
3412 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
3413 | .master = &am35xx_mdio_hwmod, | |
3414 | .slave = &omap3xxx_l3_main_hwmod, | |
3415 | .clk = "emac_fck", | |
3416 | .user = OCP_USER_MPU, | |
3417 | }; | |
3418 | ||
3419 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | |
3420 | { | |
3421 | .pa_start = AM35XX_IPSS_MDIO_BASE, | |
3422 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | |
3423 | .flags = ADDR_TYPE_RT, | |
3424 | }, | |
3425 | { } | |
3426 | }; | |
3427 | ||
3428 | /* l4_core -> davinci mdio */ | |
3429 | /* | |
3430 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3431 | * but this will probably require some additional hwmod core support, | |
3432 | * so is left as a future to-do item. | |
3433 | */ | |
3434 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
3435 | .master = &omap3xxx_l4_core_hwmod, | |
3436 | .slave = &am35xx_mdio_hwmod, | |
3437 | .clk = "emac_fck", | |
3438 | .addr = am35xx_mdio_addrs, | |
3439 | .user = OCP_USER_MPU, | |
3440 | }; | |
3441 | ||
3442 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | |
7d7e1eba TL |
3443 | { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, |
3444 | { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, | |
3445 | { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, | |
3446 | { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, | |
3447 | { .irq = -1 }, | |
31ba8808 MG |
3448 | }; |
3449 | ||
3450 | static struct omap_hwmod_class am35xx_emac_class = { | |
3451 | .name = "davinci_emac", | |
3452 | }; | |
3453 | ||
3454 | static struct omap_hwmod am35xx_emac_hwmod = { | |
3455 | .name = "davinci_emac", | |
3456 | .mpu_irqs = am35xx_emac_mpu_irqs, | |
3457 | .class = &am35xx_emac_class, | |
3458 | .flags = HWMOD_NO_IDLEST, | |
3459 | }; | |
3460 | ||
3461 | /* l3_core -> davinci emac interface */ | |
3462 | /* | |
3463 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3464 | * but this will probably require some additional hwmod core support, | |
3465 | * so is left as a future to-do item. | |
3466 | */ | |
3467 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
3468 | .master = &am35xx_emac_hwmod, | |
3469 | .slave = &omap3xxx_l3_main_hwmod, | |
3470 | .clk = "emac_ick", | |
3471 | .user = OCP_USER_MPU, | |
3472 | }; | |
3473 | ||
3474 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | |
3475 | { | |
3476 | .pa_start = AM35XX_IPSS_EMAC_BASE, | |
3477 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | |
3478 | .flags = ADDR_TYPE_RT, | |
3479 | }, | |
3480 | { } | |
3481 | }; | |
3482 | ||
3483 | /* l4_core -> davinci emac */ | |
3484 | /* | |
3485 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3486 | * but this will probably require some additional hwmod core support, | |
3487 | * so is left as a future to-do item. | |
3488 | */ | |
3489 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
3490 | .master = &omap3xxx_l4_core_hwmod, | |
3491 | .slave = &am35xx_emac_hwmod, | |
3492 | .clk = "emac_ick", | |
3493 | .addr = am35xx_emac_addrs, | |
3494 | .user = OCP_USER_MPU, | |
3495 | }; | |
3496 | ||
49484a60 AM |
3497 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { |
3498 | .master = &omap3xxx_l3_main_hwmod, | |
3499 | .slave = &omap3xxx_gpmc_hwmod, | |
3500 | .clk = "core_l3_ick", | |
3501 | .addr = omap3xxx_gpmc_addrs, | |
3502 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3503 | }; | |
3504 | ||
0a78c5c5 PW |
3505 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3506 | &omap3xxx_l3_main__l4_core, | |
3507 | &omap3xxx_l3_main__l4_per, | |
3508 | &omap3xxx_mpu__l3_main, | |
3509 | &omap3xxx_l4_core__l4_wkup, | |
3510 | &omap3xxx_l4_core__mmc3, | |
3511 | &omap3_l4_core__uart1, | |
3512 | &omap3_l4_core__uart2, | |
3513 | &omap3_l4_per__uart3, | |
3514 | &omap3_l4_core__i2c1, | |
3515 | &omap3_l4_core__i2c2, | |
3516 | &omap3_l4_core__i2c3, | |
3517 | &omap3xxx_l4_wkup__l4_sec, | |
3518 | &omap3xxx_l4_wkup__timer1, | |
3519 | &omap3xxx_l4_per__timer2, | |
3520 | &omap3xxx_l4_per__timer3, | |
3521 | &omap3xxx_l4_per__timer4, | |
3522 | &omap3xxx_l4_per__timer5, | |
3523 | &omap3xxx_l4_per__timer6, | |
3524 | &omap3xxx_l4_per__timer7, | |
3525 | &omap3xxx_l4_per__timer8, | |
3526 | &omap3xxx_l4_per__timer9, | |
3527 | &omap3xxx_l4_core__timer10, | |
3528 | &omap3xxx_l4_core__timer11, | |
3529 | &omap3xxx_l4_wkup__wd_timer2, | |
3530 | &omap3xxx_l4_wkup__gpio1, | |
3531 | &omap3xxx_l4_per__gpio2, | |
3532 | &omap3xxx_l4_per__gpio3, | |
3533 | &omap3xxx_l4_per__gpio4, | |
3534 | &omap3xxx_l4_per__gpio5, | |
3535 | &omap3xxx_l4_per__gpio6, | |
3536 | &omap3xxx_dma_system__l3, | |
3537 | &omap3xxx_l4_core__dma_system, | |
3538 | &omap3xxx_l4_core__mcbsp1, | |
3539 | &omap3xxx_l4_per__mcbsp2, | |
3540 | &omap3xxx_l4_per__mcbsp3, | |
3541 | &omap3xxx_l4_per__mcbsp4, | |
3542 | &omap3xxx_l4_core__mcbsp5, | |
3543 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3544 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3545 | &omap34xx_l4_core__mcspi1, | |
3546 | &omap34xx_l4_core__mcspi2, | |
3547 | &omap34xx_l4_core__mcspi3, | |
3548 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3549 | &omap3xxx_l4_wkup__counter_32k, |
49484a60 | 3550 | &omap3xxx_l3_main__gpmc, |
d6504acd PW |
3551 | NULL, |
3552 | }; | |
3553 | ||
0a78c5c5 PW |
3554 | /* GP-only hwmod links */ |
3555 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3556 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3557 | NULL |
3558 | }; | |
3559 | ||
0a78c5c5 PW |
3560 | /* 3430ES1-only hwmod links */ |
3561 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3562 | &omap3430es1_dss__l3, | |
3563 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3564 | NULL |
3565 | }; | |
3566 | ||
0a78c5c5 PW |
3567 | /* 3430ES2+-only hwmod links */ |
3568 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3569 | &omap3xxx_dss__l3, | |
3570 | &omap3xxx_l4_core__dss, | |
3571 | &omap3xxx_usbhsotg__l3, | |
3572 | &omap3xxx_l4_core__usbhsotg, | |
3573 | &omap3xxx_usb_host_hs__l3_main_2, | |
3574 | &omap3xxx_l4_core__usb_host_hs, | |
3575 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3576 | NULL |
3577 | }; | |
870ea2b8 | 3578 | |
0a78c5c5 PW |
3579 | /* <= 3430ES3-only hwmod links */ |
3580 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3581 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3582 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3583 | NULL |
3584 | }; | |
3585 | ||
0a78c5c5 PW |
3586 | /* 3430ES3+-only hwmod links */ |
3587 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3588 | &omap3xxx_l4_core__es3plus_mmc1, | |
3589 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3590 | NULL |
3591 | }; | |
3592 | ||
0a78c5c5 PW |
3593 | /* 34xx-only hwmod links (all ES revisions) */ |
3594 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3595 | &omap3xxx_l3__iva, | |
3596 | &omap34xx_l4_core__sr1, | |
3597 | &omap34xx_l4_core__sr2, | |
3598 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3599 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3600 | &omap3xxx_sad2d__l3, |
5486474c PW |
3601 | &omap3xxx_l4_core__mmu_isp, |
3602 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3603 | &omap3xxx_l3_main__mmu_iva, | |
3604 | #endif | |
d6504acd PW |
3605 | NULL |
3606 | }; | |
273ff8c3 | 3607 | |
0a78c5c5 PW |
3608 | /* 36xx-only hwmod links (all ES revisions) */ |
3609 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3610 | &omap3xxx_l3__iva, | |
3611 | &omap36xx_l4_per__uart4, | |
3612 | &omap3xxx_dss__l3, | |
3613 | &omap3xxx_l4_core__dss, | |
3614 | &omap36xx_l4_core__sr1, | |
3615 | &omap36xx_l4_core__sr2, | |
3616 | &omap3xxx_usbhsotg__l3, | |
3617 | &omap3xxx_l4_core__usbhsotg, | |
3618 | &omap3xxx_l4_core__mailbox, | |
3619 | &omap3xxx_usb_host_hs__l3_main_2, | |
3620 | &omap3xxx_l4_core__usb_host_hs, | |
3621 | &omap3xxx_l4_core__usb_tll_hs, | |
3622 | &omap3xxx_l4_core__es3plus_mmc1, | |
3623 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3624 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3625 | &omap3xxx_sad2d__l3, |
5486474c PW |
3626 | &omap3xxx_l4_core__mmu_isp, |
3627 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3628 | &omap3xxx_l3_main__mmu_iva, | |
3629 | #endif | |
d6504acd PW |
3630 | NULL |
3631 | }; | |
3632 | ||
0a78c5c5 PW |
3633 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3634 | &omap3xxx_dss__l3, | |
3635 | &omap3xxx_l4_core__dss, | |
3636 | &am35xx_usbhsotg__l3, | |
3637 | &am35xx_l4_core__usbhsotg, | |
3638 | &am35xx_l4_core__uart4, | |
3639 | &omap3xxx_usb_host_hs__l3_main_2, | |
3640 | &omap3xxx_l4_core__usb_host_hs, | |
3641 | &omap3xxx_l4_core__usb_tll_hs, | |
3642 | &omap3xxx_l4_core__es3plus_mmc1, | |
3643 | &omap3xxx_l4_core__es3plus_mmc2, | |
31ba8808 MG |
3644 | &am35xx_mdio__l3, |
3645 | &am35xx_l4_core__mdio, | |
3646 | &am35xx_emac__l3, | |
3647 | &am35xx_l4_core__emac, | |
d6504acd | 3648 | NULL |
7359154e PW |
3649 | }; |
3650 | ||
0a78c5c5 PW |
3651 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3652 | &omap3xxx_l4_core__dss_dispc, | |
3653 | &omap3xxx_l4_core__dss_dsi1, | |
3654 | &omap3xxx_l4_core__dss_rfbi, | |
3655 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3656 | NULL |
3657 | }; | |
3658 | ||
7359154e PW |
3659 | int __init omap3xxx_hwmod_init(void) |
3660 | { | |
d6504acd | 3661 | int r; |
0a78c5c5 | 3662 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3663 | unsigned int rev; |
3664 | ||
9ebfd285 KH |
3665 | omap_hwmod_init(); |
3666 | ||
0a78c5c5 PW |
3667 | /* Register hwmod links common to all OMAP3 */ |
3668 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3669 | if (r < 0) |
d6504acd PW |
3670 | return r; |
3671 | ||
0a78c5c5 | 3672 | /* Register GP-only hwmod links. */ |
91a36bdb | 3673 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3674 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3675 | if (r < 0) |
3676 | return r; | |
3677 | } | |
3678 | ||
d6504acd PW |
3679 | rev = omap_rev(); |
3680 | ||
3681 | /* | |
0a78c5c5 | 3682 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3683 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3684 | * All possible revisions should be included in this conditional. | |
3685 | */ | |
3686 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3687 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3688 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3689 | h = omap34xx_hwmod_ocp_ifs; |
68a88b98 | 3690 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3691 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3692 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3693 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3694 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3695 | } else { |
3696 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3697 | return -EINVAL; | |
3698 | }; | |
3699 | ||
0a78c5c5 | 3700 | r = omap_hwmod_register_links(h); |
ace90216 | 3701 | if (r < 0) |
d6504acd PW |
3702 | return r; |
3703 | ||
3704 | /* | |
0a78c5c5 | 3705 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3706 | * particular family of silicon (e.g., 34xx ES1.0) |
3707 | */ | |
3708 | h = NULL; | |
3709 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3710 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3711 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3712 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3713 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3714 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3715 | }; |
3716 | ||
a52e2ab6 | 3717 | if (h) { |
0a78c5c5 | 3718 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3719 | if (r < 0) |
3720 | return r; | |
3721 | } | |
3722 | ||
3723 | h = NULL; | |
3724 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3725 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3726 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3727 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3728 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3729 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3730 | }; |
3731 | ||
d6504acd | 3732 | if (h) |
0a78c5c5 | 3733 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3734 | if (r < 0) |
3735 | return r; | |
3736 | ||
3737 | /* | |
3738 | * DSS code presumes that dss_core hwmod is handled first, | |
3739 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3740 | * DSS hwmod links last to ensure that dss_core is already |
3741 | * registered. Otherwise some change things may happen, for | |
3742 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3743 | * in bootloader DISPC will be reset with outputs enabled | |
3744 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3745 | * long-term fix to this is to ensure hwmods are set up in | |
3746 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3747 | */ |
0a78c5c5 | 3748 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3749 | |
3750 | return r; | |
7359154e | 3751 | } |