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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
b86aeafc | 17 | #include <linux/power/smartreflex.h> |
4b25408f | 18 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 19 | |
7359154e | 20 | #include <plat/omap_hwmod.h> |
7359154e | 21 | #include <plat/dma.h> |
046465b7 | 22 | #include <plat/serial.h> |
79e3cb22 | 23 | #include "l3_3xxx.h" |
957988c7 | 24 | #include "l4_3xxx.h" |
4fe20e97 | 25 | #include <plat/i2c.h> |
6ab8946f | 26 | #include <plat/mmc.h> |
2203747c AB |
27 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
28 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
ce722d26 | 29 | #include <plat/dmtimer.h> |
5486474c | 30 | #include <plat/iommu.h> |
7359154e | 31 | |
4f9ed545 | 32 | #include "am35xx.h" |
7d7e1eba | 33 | |
dbc04161 | 34 | #include "soc.h" |
43b40992 | 35 | #include "omap_hwmod_common_data.h" |
7359154e | 36 | #include "prm-regbits-34xx.h" |
6b667f88 | 37 | #include "cm-regbits-34xx.h" |
ff2516fb | 38 | #include "wd_timer.h" |
7359154e PW |
39 | |
40 | /* | |
41 | * OMAP3xxx hardware module integration data | |
42 | * | |
844a3b63 | 43 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
44 | * TI hardware database or other technical documentation. Data that |
45 | * is driver-specific or driver-kernel integration-specific belongs | |
46 | * elsewhere. | |
47 | */ | |
48 | ||
844a3b63 PW |
49 | /* |
50 | * IP blocks | |
51 | */ | |
7359154e | 52 | |
844a3b63 | 53 | /* L3 */ |
4bb194dc | 54 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
7d7e1eba TL |
55 | { .irq = 9 + OMAP_INTC_START, }, |
56 | { .irq = 10 + OMAP_INTC_START, }, | |
57 | { .irq = -1 }, | |
4bb194dc | 58 | }; |
59 | ||
4a7cf90a | 60 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 61 | .name = "l3_main", |
43b40992 | 62 | .class = &l3_hwmod_class, |
0d619a89 | 63 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 64 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
65 | }; |
66 | ||
844a3b63 PW |
67 | /* L4 CORE */ |
68 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
69 | .name = "l4_core", | |
70 | .class = &l4_hwmod_class, | |
71 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 72 | }; |
7359154e | 73 | |
844a3b63 PW |
74 | /* L4 PER */ |
75 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
76 | .name = "l4_per", | |
77 | .class = &l4_hwmod_class, | |
78 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 79 | }; |
844a3b63 PW |
80 | |
81 | /* L4 WKUP */ | |
82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
83 | .name = "l4_wkup", | |
84 | .class = &l4_hwmod_class, | |
85 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
86 | }; |
87 | ||
844a3b63 PW |
88 | /* L4 SEC */ |
89 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
90 | .name = "l4_sec", | |
91 | .class = &l4_hwmod_class, | |
92 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
93 | }; |
94 | ||
844a3b63 | 95 | /* MPU */ |
ee75d95c | 96 | static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { |
3dc3401c | 97 | { .name = "pmu", .irq = 3 + OMAP_INTC_START }, |
ee75d95c JH |
98 | { .irq = -1 } |
99 | }; | |
100 | ||
844a3b63 PW |
101 | static struct omap_hwmod omap3xxx_mpu_hwmod = { |
102 | .name = "mpu", | |
ee75d95c | 103 | .mpu_irqs = omap3xxx_mpu_irqs, |
844a3b63 PW |
104 | .class = &mpu_hwmod_class, |
105 | .main_clk = "arm_fck", | |
b163605e PW |
106 | }; |
107 | ||
844a3b63 | 108 | /* IVA2 (IVA2) */ |
f42c5496 | 109 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
ed733619 TK |
110 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
111 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
112 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
113 | }; |
114 | ||
844a3b63 PW |
115 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
116 | .name = "iva", | |
117 | .class = &iva_hwmod_class, | |
f42c5496 PW |
118 | .clkdm_name = "iva2_clkdm", |
119 | .rst_lines = omap3xxx_iva_resets, | |
120 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
121 | .main_clk = "iva2_ck", | |
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122 | .prcm = { |
123 | .omap2 = { | |
124 | .module_offs = OMAP3430_IVA2_MOD, | |
125 | .prcm_reg_id = 1, | |
126 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
127 | .idlest_reg_id = 1, | |
128 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
129 | } | |
130 | }, | |
4a9efb62 PW |
131 | }; |
132 | ||
c7dad45f JH |
133 | /* |
134 | * 'debugss' class | |
135 | * debug and emulation sub system | |
136 | */ | |
137 | ||
138 | static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { | |
139 | .name = "debugss", | |
140 | }; | |
141 | ||
142 | /* debugss */ | |
143 | static struct omap_hwmod omap3xxx_debugss_hwmod = { | |
144 | .name = "debugss", | |
145 | .class = &omap3xxx_debugss_hwmod_class, | |
146 | .clkdm_name = "emu_clkdm", | |
147 | .main_clk = "emu_src_ck", | |
148 | .flags = HWMOD_NO_IDLEST, | |
149 | }; | |
150 | ||
844a3b63 PW |
151 | /* timer class */ |
152 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
153 | .rev_offs = 0x0000, | |
154 | .sysc_offs = 0x0010, | |
155 | .syss_offs = 0x0014, | |
156 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
157 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
158 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
159 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
160 | .sysc_fields = &omap_hwmod_sysc_type1, | |
b163605e PW |
161 | }; |
162 | ||
844a3b63 PW |
163 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
164 | .name = "timer", | |
165 | .sysc = &omap3xxx_timer_1ms_sysc, | |
b163605e PW |
166 | }; |
167 | ||
844a3b63 PW |
168 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
169 | .rev_offs = 0x0000, | |
170 | .sysc_offs = 0x0010, | |
171 | .syss_offs = 0x0014, | |
172 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
173 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
174 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
175 | .sysc_fields = &omap_hwmod_sysc_type1, | |
b163605e PW |
176 | }; |
177 | ||
844a3b63 PW |
178 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
179 | .name = "timer", | |
180 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
181 | }; |
182 | ||
844a3b63 PW |
183 | /* secure timers dev attribute */ |
184 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 185 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
186 | }; |
187 | ||
844a3b63 PW |
188 | /* always-on timers dev attribute */ |
189 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
190 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
191 | }; |
192 | ||
844a3b63 PW |
193 | /* pwm timers dev attribute */ |
194 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
195 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
196 | }; |
197 | ||
5c3e4ec4 JH |
198 | /* timers with DSP interrupt dev attribute */ |
199 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
200 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
201 | }; | |
202 | ||
203 | /* pwm timers with DSP interrupt dev attribute */ | |
204 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
205 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
206 | }; | |
207 | ||
844a3b63 PW |
208 | /* timer1 */ |
209 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
210 | .name = "timer1", | |
211 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
212 | .main_clk = "gpt1_fck", | |
213 | .prcm = { | |
214 | .omap2 = { | |
215 | .prcm_reg_id = 1, | |
216 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
217 | .module_offs = WKUP_MOD, | |
218 | .idlest_reg_id = 1, | |
219 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
220 | }, | |
046465b7 | 221 | }, |
844a3b63 PW |
222 | .dev_attr = &capability_alwon_dev_attr, |
223 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
224 | }; |
225 | ||
844a3b63 PW |
226 | /* timer2 */ |
227 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
228 | .name = "timer2", | |
229 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
230 | .main_clk = "gpt2_fck", | |
231 | .prcm = { | |
232 | .omap2 = { | |
233 | .prcm_reg_id = 1, | |
234 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
235 | .module_offs = OMAP3430_PER_MOD, | |
236 | .idlest_reg_id = 1, | |
237 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
238 | }, | |
239 | }, | |
844a3b63 | 240 | .class = &omap3xxx_timer_1ms_hwmod_class, |
046465b7 KH |
241 | }; |
242 | ||
844a3b63 PW |
243 | /* timer3 */ |
244 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
245 | .name = "timer3", | |
246 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
247 | .main_clk = "gpt3_fck", | |
248 | .prcm = { | |
249 | .omap2 = { | |
250 | .prcm_reg_id = 1, | |
251 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
252 | .module_offs = OMAP3430_PER_MOD, | |
253 | .idlest_reg_id = 1, | |
254 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
255 | }, | |
256 | }, | |
844a3b63 | 257 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
258 | }; |
259 | ||
844a3b63 PW |
260 | /* timer4 */ |
261 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
262 | .name = "timer4", | |
263 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
264 | .main_clk = "gpt4_fck", | |
265 | .prcm = { | |
266 | .omap2 = { | |
267 | .prcm_reg_id = 1, | |
268 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
269 | .module_offs = OMAP3430_PER_MOD, | |
270 | .idlest_reg_id = 1, | |
271 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
272 | }, | |
273 | }, | |
844a3b63 | 274 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
275 | }; |
276 | ||
844a3b63 PW |
277 | /* timer5 */ |
278 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
279 | .name = "timer5", | |
280 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
281 | .main_clk = "gpt5_fck", | |
282 | .prcm = { | |
283 | .omap2 = { | |
284 | .prcm_reg_id = 1, | |
285 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
286 | .module_offs = OMAP3430_PER_MOD, | |
287 | .idlest_reg_id = 1, | |
288 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
289 | }, | |
4bf90f65 | 290 | }, |
5c3e4ec4 | 291 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 292 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
293 | }; |
294 | ||
844a3b63 PW |
295 | /* timer6 */ |
296 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
297 | .name = "timer6", | |
298 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
299 | .main_clk = "gpt6_fck", | |
300 | .prcm = { | |
301 | .omap2 = { | |
302 | .prcm_reg_id = 1, | |
303 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
304 | .module_offs = OMAP3430_PER_MOD, | |
305 | .idlest_reg_id = 1, | |
306 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
307 | }, | |
308 | }, | |
5c3e4ec4 | 309 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 310 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
311 | }; |
312 | ||
844a3b63 PW |
313 | /* timer7 */ |
314 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
315 | .name = "timer7", | |
316 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
317 | .main_clk = "gpt7_fck", | |
318 | .prcm = { | |
4fe20e97 | 319 | .omap2 = { |
844a3b63 PW |
320 | .prcm_reg_id = 1, |
321 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
322 | .module_offs = OMAP3430_PER_MOD, | |
323 | .idlest_reg_id = 1, | |
324 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
325 | }, | |
4fe20e97 | 326 | }, |
5c3e4ec4 | 327 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 328 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
329 | }; |
330 | ||
844a3b63 PW |
331 | /* timer8 */ |
332 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
333 | .name = "timer8", | |
334 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
335 | .main_clk = "gpt8_fck", | |
336 | .prcm = { | |
4fe20e97 | 337 | .omap2 = { |
844a3b63 PW |
338 | .prcm_reg_id = 1, |
339 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
340 | .module_offs = OMAP3430_PER_MOD, | |
341 | .idlest_reg_id = 1, | |
342 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
343 | }, | |
4fe20e97 | 344 | }, |
5c3e4ec4 | 345 | .dev_attr = &capability_dsp_pwm_dev_attr, |
844a3b63 | 346 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
347 | }; |
348 | ||
844a3b63 PW |
349 | /* timer9 */ |
350 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
351 | .name = "timer9", | |
352 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
353 | .main_clk = "gpt9_fck", | |
354 | .prcm = { | |
355 | .omap2 = { | |
356 | .prcm_reg_id = 1, | |
357 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
358 | .module_offs = OMAP3430_PER_MOD, | |
359 | .idlest_reg_id = 1, | |
360 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
361 | }, | |
4fe20e97 | 362 | }, |
844a3b63 PW |
363 | .dev_attr = &capability_pwm_dev_attr, |
364 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
365 | }; |
366 | ||
844a3b63 PW |
367 | /* timer10 */ |
368 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
369 | .name = "timer10", | |
370 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
371 | .main_clk = "gpt10_fck", | |
372 | .prcm = { | |
4fe20e97 | 373 | .omap2 = { |
844a3b63 PW |
374 | .prcm_reg_id = 1, |
375 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
376 | .module_offs = CORE_MOD, | |
377 | .idlest_reg_id = 1, | |
378 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
379 | }, | |
4fe20e97 | 380 | }, |
844a3b63 PW |
381 | .dev_attr = &capability_pwm_dev_attr, |
382 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
383 | }; |
384 | ||
844a3b63 PW |
385 | /* timer11 */ |
386 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
387 | .name = "timer11", | |
388 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
389 | .main_clk = "gpt11_fck", | |
390 | .prcm = { | |
391 | .omap2 = { | |
392 | .prcm_reg_id = 1, | |
393 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
394 | .module_offs = CORE_MOD, | |
395 | .idlest_reg_id = 1, | |
396 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
397 | }, | |
398 | }, | |
399 | .dev_attr = &capability_pwm_dev_attr, | |
400 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
401 | }; |
402 | ||
844a3b63 PW |
403 | /* timer12 */ |
404 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
7d7e1eba TL |
405 | { .irq = 95 + OMAP_INTC_START, }, |
406 | { .irq = -1 }, | |
d62bc78a NM |
407 | }; |
408 | ||
844a3b63 PW |
409 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
410 | .name = "timer12", | |
411 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
412 | .main_clk = "gpt12_fck", | |
413 | .prcm = { | |
414 | .omap2 = { | |
415 | .prcm_reg_id = 1, | |
416 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
417 | .module_offs = WKUP_MOD, | |
418 | .idlest_reg_id = 1, | |
419 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
420 | }, | |
d3442726 | 421 | }, |
844a3b63 PW |
422 | .dev_attr = &capability_secure_dev_attr, |
423 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
424 | }; |
425 | ||
844a3b63 PW |
426 | /* |
427 | * 'wd_timer' class | |
428 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
429 | * overflow condition | |
430 | */ | |
431 | ||
432 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
433 | .rev_offs = 0x0000, | |
434 | .sysc_offs = 0x0010, | |
435 | .syss_offs = 0x0014, | |
436 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
437 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
438 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
439 | SYSS_HAS_RESET_STATUS), | |
440 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
441 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
442 | }; |
443 | ||
844a3b63 PW |
444 | /* I2C common */ |
445 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
446 | .rev_offs = 0x00, | |
447 | .sysc_offs = 0x20, | |
448 | .syss_offs = 0x10, | |
449 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
450 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
451 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
452 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
453 | .clockact = CLOCKACT_TEST_ICLK, | |
454 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
455 | }; |
456 | ||
844a3b63 PW |
457 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
458 | .name = "wd_timer", | |
459 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
460 | .pre_shutdown = &omap2_wd_timer_disable, |
461 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
462 | }; |
463 | ||
844a3b63 PW |
464 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
465 | .name = "wd_timer2", | |
466 | .class = &omap3xxx_wd_timer_hwmod_class, | |
467 | .main_clk = "wdt2_fck", | |
468 | .prcm = { | |
469 | .omap2 = { | |
470 | .prcm_reg_id = 1, | |
471 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
472 | .module_offs = WKUP_MOD, | |
473 | .idlest_reg_id = 1, | |
474 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
475 | }, | |
476 | }, | |
477 | /* | |
478 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
479 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
480 | */ | |
481 | .flags = HWMOD_SWSUP_SIDLE, | |
482 | }; | |
870ea2b8 | 483 | |
844a3b63 PW |
484 | /* UART1 */ |
485 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
486 | .name = "uart1", | |
487 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
488 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
489 | .main_clk = "uart1_fck", | |
490 | .prcm = { | |
491 | .omap2 = { | |
492 | .module_offs = CORE_MOD, | |
493 | .prcm_reg_id = 1, | |
494 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
495 | .idlest_reg_id = 1, | |
496 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
497 | }, | |
870ea2b8 | 498 | }, |
844a3b63 | 499 | .class = &omap2_uart_class, |
870ea2b8 HH |
500 | }; |
501 | ||
844a3b63 PW |
502 | /* UART2 */ |
503 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
504 | .name = "uart2", | |
505 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
506 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
507 | .main_clk = "uart2_fck", | |
508 | .prcm = { | |
509 | .omap2 = { | |
510 | .module_offs = CORE_MOD, | |
511 | .prcm_reg_id = 1, | |
512 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
513 | .idlest_reg_id = 1, | |
514 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
515 | }, | |
516 | }, | |
517 | .class = &omap2_uart_class, | |
870ea2b8 HH |
518 | }; |
519 | ||
844a3b63 PW |
520 | /* UART3 */ |
521 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
522 | .name = "uart3", | |
523 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
524 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
525 | .main_clk = "uart3_fck", | |
526 | .prcm = { | |
527 | .omap2 = { | |
528 | .module_offs = OMAP3430_PER_MOD, | |
529 | .prcm_reg_id = 1, | |
530 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
531 | .idlest_reg_id = 1, | |
532 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
533 | }, | |
273ff8c3 | 534 | }, |
844a3b63 | 535 | .class = &omap2_uart_class, |
273ff8c3 HH |
536 | }; |
537 | ||
844a3b63 PW |
538 | /* UART4 */ |
539 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
7d7e1eba TL |
540 | { .irq = 80 + OMAP_INTC_START, }, |
541 | { .irq = -1 }, | |
273ff8c3 HH |
542 | }; |
543 | ||
844a3b63 PW |
544 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
545 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
546 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
547 | { .dma_req = -1 } | |
7359154e PW |
548 | }; |
549 | ||
844a3b63 PW |
550 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
551 | .name = "uart4", | |
552 | .mpu_irqs = uart4_mpu_irqs, | |
553 | .sdma_reqs = uart4_sdma_reqs, | |
554 | .main_clk = "uart4_fck", | |
555 | .prcm = { | |
556 | .omap2 = { | |
557 | .module_offs = OMAP3430_PER_MOD, | |
558 | .prcm_reg_id = 1, | |
559 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
560 | .idlest_reg_id = 1, | |
561 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
562 | }, | |
563 | }, | |
564 | .class = &omap2_uart_class, | |
7359154e PW |
565 | }; |
566 | ||
844a3b63 | 567 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
7d7e1eba TL |
568 | { .irq = 84 + OMAP_INTC_START, }, |
569 | { .irq = -1 }, | |
43085705 PW |
570 | }; |
571 | ||
844a3b63 PW |
572 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
573 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
574 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
bf765237 | 575 | { .dma_req = -1 } |
7359154e PW |
576 | }; |
577 | ||
82ee620d PW |
578 | /* |
579 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
580 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
581 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
582 | * should not be needed. The functional clock structure of the AM35xx | |
583 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
584 | * of uart1/2_fck is for the UART4. Any clarification from either | |
585 | * empirical testing or the AM3505/3517 hardware designers would be | |
586 | * most welcome. | |
587 | */ | |
588 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
589 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
590 | }; | |
591 | ||
844a3b63 PW |
592 | static struct omap_hwmod am35xx_uart4_hwmod = { |
593 | .name = "uart4", | |
594 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
595 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
596 | .main_clk = "uart4_fck", | |
597 | .prcm = { | |
598 | .omap2 = { | |
599 | .module_offs = CORE_MOD, | |
600 | .prcm_reg_id = 1, | |
bf765237 | 601 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 602 | .idlest_reg_id = 1, |
bf765237 | 603 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
604 | }, |
605 | }, | |
82ee620d PW |
606 | .opt_clks = am35xx_uart4_opt_clks, |
607 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
608 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
609 | .class = &omap2_uart_class, |
610 | }; | |
611 | ||
612 | static struct omap_hwmod_class i2c_class = { | |
613 | .name = "i2c", | |
614 | .sysc = &i2c_sysc, | |
615 | .rev = OMAP_I2C_IP_VERSION_1, | |
616 | .reset = &omap_i2c_reset, | |
617 | }; | |
618 | ||
619 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
620 | { .name = "dispc", .dma_req = 5 }, | |
621 | { .name = "dsi1", .dma_req = 74 }, | |
622 | { .dma_req = -1 } | |
43085705 PW |
623 | }; |
624 | ||
844a3b63 PW |
625 | /* dss */ |
626 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
627 | /* | |
628 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
629 | * driver does not use these clocks. | |
630 | */ | |
631 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
632 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
633 | /* required only on OMAP3430 */ | |
634 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
635 | }; |
636 | ||
844a3b63 PW |
637 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
638 | .name = "dss_core", | |
639 | .class = &omap2_dss_hwmod_class, | |
640 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
641 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
642 | .prcm = { | |
643 | .omap2 = { | |
644 | .prcm_reg_id = 1, | |
645 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
646 | .module_offs = OMAP3430_DSS_MOD, | |
647 | .idlest_reg_id = 1, | |
648 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
649 | }, | |
650 | }, | |
651 | .opt_clks = dss_opt_clks, | |
652 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
653 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
654 | }; | |
540064bf | 655 | |
844a3b63 PW |
656 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
657 | .name = "dss_core", | |
658 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
659 | .class = &omap2_dss_hwmod_class, | |
660 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
661 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
662 | .prcm = { | |
663 | .omap2 = { | |
664 | .prcm_reg_id = 1, | |
665 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
666 | .module_offs = OMAP3430_DSS_MOD, | |
667 | .idlest_reg_id = 1, | |
668 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
669 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
670 | }, | |
671 | }, | |
672 | .opt_clks = dss_opt_clks, | |
673 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
674 | }; |
675 | ||
540064bf | 676 | /* |
844a3b63 PW |
677 | * 'dispc' class |
678 | * display controller | |
540064bf KH |
679 | */ |
680 | ||
844a3b63 | 681 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
682 | .rev_offs = 0x0000, |
683 | .sysc_offs = 0x0010, | |
684 | .syss_offs = 0x0014, | |
844a3b63 PW |
685 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
686 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
687 | SYSC_HAS_ENAWAKEUP), | |
688 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
689 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 690 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
691 | }; |
692 | ||
844a3b63 PW |
693 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
694 | .name = "dispc", | |
695 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
696 | }; |
697 | ||
844a3b63 PW |
698 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
699 | .name = "dss_dispc", | |
700 | .class = &omap3_dispc_hwmod_class, | |
701 | .mpu_irqs = omap2_dispc_irqs, | |
702 | .main_clk = "dss1_alwon_fck", | |
703 | .prcm = { | |
704 | .omap2 = { | |
705 | .prcm_reg_id = 1, | |
706 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
707 | .module_offs = OMAP3430_DSS_MOD, | |
708 | }, | |
709 | }, | |
710 | .flags = HWMOD_NO_IDLEST, | |
711 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
712 | }; |
713 | ||
844a3b63 PW |
714 | /* |
715 | * 'dsi' class | |
716 | * display serial interface controller | |
717 | */ | |
4fe20e97 | 718 | |
844a3b63 PW |
719 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
720 | .name = "dsi", | |
c345c8b0 TKD |
721 | }; |
722 | ||
844a3b63 | 723 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
7d7e1eba TL |
724 | { .irq = 25 + OMAP_INTC_START, }, |
725 | { .irq = -1 }, | |
c345c8b0 TKD |
726 | }; |
727 | ||
844a3b63 PW |
728 | /* dss_dsi1 */ |
729 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
730 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
731 | }; |
732 | ||
844a3b63 PW |
733 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
734 | .name = "dss_dsi1", | |
735 | .class = &omap3xxx_dsi_hwmod_class, | |
736 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
737 | .main_clk = "dss1_alwon_fck", | |
738 | .prcm = { | |
739 | .omap2 = { | |
740 | .prcm_reg_id = 1, | |
741 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
742 | .module_offs = OMAP3430_DSS_MOD, | |
743 | }, | |
ce722d26 | 744 | }, |
844a3b63 PW |
745 | .opt_clks = dss_dsi1_opt_clks, |
746 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
747 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
748 | }; |
749 | ||
844a3b63 PW |
750 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
751 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
752 | }; |
753 | ||
844a3b63 PW |
754 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
755 | .name = "dss_rfbi", | |
756 | .class = &omap2_rfbi_hwmod_class, | |
757 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
758 | .prcm = { |
759 | .omap2 = { | |
760 | .prcm_reg_id = 1, | |
844a3b63 PW |
761 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
762 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
763 | }, |
764 | }, | |
844a3b63 PW |
765 | .opt_clks = dss_rfbi_opt_clks, |
766 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
767 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
768 | }; |
769 | ||
844a3b63 PW |
770 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
771 | /* required only on OMAP3430 */ | |
772 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
773 | }; |
774 | ||
844a3b63 PW |
775 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
776 | .name = "dss_venc", | |
777 | .class = &omap2_venc_hwmod_class, | |
778 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
779 | .prcm = { |
780 | .omap2 = { | |
046465b7 | 781 | .prcm_reg_id = 1, |
844a3b63 PW |
782 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
783 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
784 | }, |
785 | }, | |
844a3b63 PW |
786 | .opt_clks = dss_venc_opt_clks, |
787 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
788 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
789 | }; |
790 | ||
844a3b63 PW |
791 | /* I2C1 */ |
792 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
793 | .fifo_depth = 8, /* bytes */ | |
794 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
795 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
796 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
797 | }; |
798 | ||
844a3b63 PW |
799 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
800 | .name = "i2c1", | |
801 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
802 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
803 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
804 | .main_clk = "i2c1_fck", | |
046465b7 KH |
805 | .prcm = { |
806 | .omap2 = { | |
844a3b63 | 807 | .module_offs = CORE_MOD, |
046465b7 | 808 | .prcm_reg_id = 1, |
844a3b63 | 809 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 810 | .idlest_reg_id = 1, |
844a3b63 | 811 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
812 | }, |
813 | }, | |
844a3b63 PW |
814 | .class = &i2c_class, |
815 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
816 | }; |
817 | ||
844a3b63 PW |
818 | /* I2C2 */ |
819 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
820 | .fifo_depth = 8, /* bytes */ | |
821 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
822 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
823 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
824 | }; |
825 | ||
844a3b63 PW |
826 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
827 | .name = "i2c2", | |
828 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
829 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
830 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
831 | .main_clk = "i2c2_fck", | |
046465b7 KH |
832 | .prcm = { |
833 | .omap2 = { | |
844a3b63 | 834 | .module_offs = CORE_MOD, |
046465b7 | 835 | .prcm_reg_id = 1, |
844a3b63 | 836 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 837 | .idlest_reg_id = 1, |
844a3b63 | 838 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
839 | }, |
840 | }, | |
844a3b63 PW |
841 | .class = &i2c_class, |
842 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
843 | }; |
844 | ||
844a3b63 PW |
845 | /* I2C3 */ |
846 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
847 | .fifo_depth = 64, /* bytes */ | |
848 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
849 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
850 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
851 | }; | |
046465b7 | 852 | |
844a3b63 | 853 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
7d7e1eba TL |
854 | { .irq = 61 + OMAP_INTC_START, }, |
855 | { .irq = -1 }, | |
046465b7 KH |
856 | }; |
857 | ||
844a3b63 PW |
858 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
859 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
860 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
861 | { .dma_req = -1 } | |
046465b7 KH |
862 | }; |
863 | ||
844a3b63 PW |
864 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
865 | .name = "i2c3", | |
866 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
867 | .mpu_irqs = i2c3_mpu_irqs, | |
868 | .sdma_reqs = i2c3_sdma_reqs, | |
869 | .main_clk = "i2c3_fck", | |
046465b7 KH |
870 | .prcm = { |
871 | .omap2 = { | |
844a3b63 | 872 | .module_offs = CORE_MOD, |
046465b7 | 873 | .prcm_reg_id = 1, |
844a3b63 | 874 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 875 | .idlest_reg_id = 1, |
844a3b63 | 876 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
877 | }, |
878 | }, | |
844a3b63 PW |
879 | .class = &i2c_class, |
880 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
881 | }; |
882 | ||
844a3b63 PW |
883 | /* |
884 | * 'gpio' class | |
885 | * general purpose io module | |
886 | */ | |
4fe20e97 | 887 | |
844a3b63 PW |
888 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
889 | .rev_offs = 0x0000, | |
890 | .sysc_offs = 0x0010, | |
891 | .syss_offs = 0x0014, | |
892 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
893 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
894 | SYSS_HAS_RESET_STATUS), | |
895 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
896 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
897 | }; |
898 | ||
844a3b63 PW |
899 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
900 | .name = "gpio", | |
901 | .sysc = &omap3xxx_gpio_sysc, | |
902 | .rev = 1, | |
4fe20e97 RN |
903 | }; |
904 | ||
844a3b63 PW |
905 | /* gpio_dev_attr */ |
906 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
907 | .bank_width = 32, | |
908 | .dbck_flag = true, | |
909 | }; | |
910 | ||
911 | /* gpio1 */ | |
912 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
913 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
914 | }; | |
915 | ||
916 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
917 | .name = "gpio1", | |
918 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
919 | .mpu_irqs = omap2_gpio1_irqs, | |
920 | .main_clk = "gpio1_ick", | |
921 | .opt_clks = gpio1_opt_clks, | |
922 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
923 | .prcm = { |
924 | .omap2 = { | |
4fe20e97 | 925 | .prcm_reg_id = 1, |
844a3b63 PW |
926 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
927 | .module_offs = WKUP_MOD, | |
4fe20e97 | 928 | .idlest_reg_id = 1, |
844a3b63 | 929 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
930 | }, |
931 | }, | |
844a3b63 PW |
932 | .class = &omap3xxx_gpio_hwmod_class, |
933 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
934 | }; |
935 | ||
844a3b63 PW |
936 | /* gpio2 */ |
937 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
938 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
939 | }; |
940 | ||
844a3b63 PW |
941 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
942 | .name = "gpio2", | |
943 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
944 | .mpu_irqs = omap2_gpio2_irqs, | |
945 | .main_clk = "gpio2_ick", | |
946 | .opt_clks = gpio2_opt_clks, | |
947 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
948 | .prcm = { |
949 | .omap2 = { | |
4fe20e97 | 950 | .prcm_reg_id = 1, |
844a3b63 | 951 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 952 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 953 | .idlest_reg_id = 1, |
844a3b63 | 954 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
955 | }, |
956 | }, | |
844a3b63 PW |
957 | .class = &omap3xxx_gpio_hwmod_class, |
958 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
959 | }; |
960 | ||
844a3b63 PW |
961 | /* gpio3 */ |
962 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
963 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
964 | }; |
965 | ||
844a3b63 PW |
966 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
967 | .name = "gpio3", | |
968 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
969 | .mpu_irqs = omap2_gpio3_irqs, | |
970 | .main_clk = "gpio3_ick", | |
971 | .opt_clks = gpio3_opt_clks, | |
972 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
973 | .prcm = { |
974 | .omap2 = { | |
4fe20e97 | 975 | .prcm_reg_id = 1, |
844a3b63 | 976 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 977 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 978 | .idlest_reg_id = 1, |
844a3b63 | 979 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
980 | }, |
981 | }, | |
844a3b63 PW |
982 | .class = &omap3xxx_gpio_hwmod_class, |
983 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
984 | }; |
985 | ||
844a3b63 PW |
986 | /* gpio4 */ |
987 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
988 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
989 | }; |
990 | ||
844a3b63 PW |
991 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
992 | .name = "gpio4", | |
993 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
994 | .mpu_irqs = omap2_gpio4_irqs, | |
995 | .main_clk = "gpio4_ick", | |
996 | .opt_clks = gpio4_opt_clks, | |
997 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
998 | .prcm = { |
999 | .omap2 = { | |
1000 | .prcm_reg_id = 1, | |
844a3b63 | 1001 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
1002 | .module_offs = OMAP3430_PER_MOD, |
1003 | .idlest_reg_id = 1, | |
844a3b63 | 1004 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 1005 | }, |
70034d38 | 1006 | }, |
844a3b63 PW |
1007 | .class = &omap3xxx_gpio_hwmod_class, |
1008 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1009 | }; |
1010 | ||
844a3b63 PW |
1011 | /* gpio5 */ |
1012 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
7d7e1eba TL |
1013 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
1014 | { .irq = -1 }, | |
844a3b63 | 1015 | }; |
70034d38 | 1016 | |
844a3b63 PW |
1017 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1018 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
1019 | }; |
1020 | ||
844a3b63 PW |
1021 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
1022 | .name = "gpio5", | |
1023 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1024 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
1025 | .main_clk = "gpio5_ick", | |
1026 | .opt_clks = gpio5_opt_clks, | |
1027 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
1028 | .prcm = { |
1029 | .omap2 = { | |
1030 | .prcm_reg_id = 1, | |
844a3b63 PW |
1031 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
1032 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1033 | .idlest_reg_id = 1, |
844a3b63 | 1034 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 1035 | }, |
70034d38 | 1036 | }, |
844a3b63 PW |
1037 | .class = &omap3xxx_gpio_hwmod_class, |
1038 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1039 | }; |
1040 | ||
844a3b63 PW |
1041 | /* gpio6 */ |
1042 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
7d7e1eba TL |
1043 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
1044 | { .irq = -1 }, | |
844a3b63 | 1045 | }; |
70034d38 | 1046 | |
844a3b63 PW |
1047 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
1048 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
1049 | }; |
1050 | ||
844a3b63 PW |
1051 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
1052 | .name = "gpio6", | |
1053 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1054 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1055 | .main_clk = "gpio6_ick", | |
1056 | .opt_clks = gpio6_opt_clks, | |
1057 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1058 | .prcm = { |
1059 | .omap2 = { | |
1060 | .prcm_reg_id = 1, | |
844a3b63 PW |
1061 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1062 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1063 | .idlest_reg_id = 1, |
844a3b63 | 1064 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1065 | }, |
1066 | }, | |
844a3b63 PW |
1067 | .class = &omap3xxx_gpio_hwmod_class, |
1068 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1069 | }; |
1070 | ||
844a3b63 PW |
1071 | /* dma attributes */ |
1072 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1073 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1074 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1075 | .lch_count = 32, | |
ce722d26 TG |
1076 | }; |
1077 | ||
844a3b63 PW |
1078 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1079 | .rev_offs = 0x0000, | |
1080 | .sysc_offs = 0x002c, | |
1081 | .syss_offs = 0x0028, | |
1082 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1083 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1084 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1085 | SYSS_HAS_RESET_STATUS), | |
1086 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1087 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1088 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1089 | }; |
1090 | ||
844a3b63 PW |
1091 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1092 | .name = "dma", | |
1093 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1094 | }; |
1095 | ||
844a3b63 PW |
1096 | /* dma_system */ |
1097 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1098 | .name = "dma", | |
1099 | .class = &omap3xxx_dma_hwmod_class, | |
1100 | .mpu_irqs = omap2_dma_system_irqs, | |
1101 | .main_clk = "core_l3_ick", | |
1102 | .prcm = { | |
ce722d26 | 1103 | .omap2 = { |
844a3b63 PW |
1104 | .module_offs = CORE_MOD, |
1105 | .prcm_reg_id = 1, | |
1106 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1107 | .idlest_reg_id = 1, | |
1108 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1109 | }, |
1110 | }, | |
844a3b63 PW |
1111 | .dev_attr = &dma_dev_attr, |
1112 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1113 | }; |
1114 | ||
844a3b63 PW |
1115 | /* |
1116 | * 'mcbsp' class | |
1117 | * multi channel buffered serial port controller | |
1118 | */ | |
1119 | ||
1120 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1121 | .sysc_offs = 0x008c, | |
1122 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1123 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1124 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1125 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1126 | .clockact = 0x2, | |
70034d38 VC |
1127 | }; |
1128 | ||
844a3b63 PW |
1129 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1130 | .name = "mcbsp", | |
1131 | .sysc = &omap3xxx_mcbsp_sysc, | |
1132 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1133 | }; |
1134 | ||
7039154b PU |
1135 | /* McBSP functional clock mapping */ |
1136 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1137 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1138 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1139 | }; | |
1140 | ||
1141 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1142 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1143 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1144 | }; | |
1145 | ||
844a3b63 PW |
1146 | /* mcbsp1 */ |
1147 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
7d7e1eba TL |
1148 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
1149 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, | |
1150 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
1151 | { .irq = -1 }, | |
844a3b63 | 1152 | }; |
6b667f88 | 1153 | |
844a3b63 PW |
1154 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1155 | .name = "mcbsp1", | |
1156 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1157 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1158 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1159 | .main_clk = "mcbsp1_fck", | |
1160 | .prcm = { | |
1161 | .omap2 = { | |
1162 | .prcm_reg_id = 1, | |
1163 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1164 | .module_offs = CORE_MOD, | |
1165 | .idlest_reg_id = 1, | |
1166 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1167 | }, | |
1168 | }, | |
7039154b PU |
1169 | .opt_clks = mcbsp15_opt_clks, |
1170 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1171 | }; |
1172 | ||
844a3b63 PW |
1173 | /* mcbsp2 */ |
1174 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
7d7e1eba TL |
1175 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
1176 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, | |
1177 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
1178 | { .irq = -1 }, | |
70034d38 VC |
1179 | }; |
1180 | ||
844a3b63 PW |
1181 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1182 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1183 | }; |
1184 | ||
844a3b63 PW |
1185 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1186 | .name = "mcbsp2", | |
1187 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1188 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1189 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1190 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1191 | .prcm = { |
1192 | .omap2 = { | |
1193 | .prcm_reg_id = 1, | |
844a3b63 PW |
1194 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1195 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1196 | .idlest_reg_id = 1, |
844a3b63 | 1197 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1198 | }, |
1199 | }, | |
7039154b PU |
1200 | .opt_clks = mcbsp234_opt_clks, |
1201 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1202 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1203 | }; |
1204 | ||
844a3b63 PW |
1205 | /* mcbsp3 */ |
1206 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
7d7e1eba TL |
1207 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
1208 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, | |
1209 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
1210 | { .irq = -1 }, | |
844a3b63 PW |
1211 | }; |
1212 | ||
1213 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1214 | .sidetone = "mcbsp3_sidetone", | |
1215 | }; | |
1216 | ||
1217 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1218 | .name = "mcbsp3", | |
1219 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1220 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1221 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1222 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1223 | .prcm = { |
1224 | .omap2 = { | |
1225 | .prcm_reg_id = 1, | |
844a3b63 PW |
1226 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1227 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1228 | .idlest_reg_id = 1, |
844a3b63 | 1229 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1230 | }, |
1231 | }, | |
7039154b PU |
1232 | .opt_clks = mcbsp234_opt_clks, |
1233 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1234 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1235 | }; |
1236 | ||
844a3b63 PW |
1237 | /* mcbsp4 */ |
1238 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
7d7e1eba TL |
1239 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
1240 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, | |
1241 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
1242 | { .irq = -1 }, | |
844a3b63 PW |
1243 | }; |
1244 | ||
1245 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1246 | { .name = "rx", .dma_req = 20 }, | |
1247 | { .name = "tx", .dma_req = 19 }, | |
1248 | { .dma_req = -1 } | |
1249 | }; | |
1250 | ||
1251 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1252 | .name = "mcbsp4", | |
1253 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1254 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1255 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1256 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1257 | .prcm = { |
1258 | .omap2 = { | |
1259 | .prcm_reg_id = 1, | |
844a3b63 PW |
1260 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1261 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1262 | .idlest_reg_id = 1, |
844a3b63 | 1263 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1264 | }, |
1265 | }, | |
7039154b PU |
1266 | .opt_clks = mcbsp234_opt_clks, |
1267 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1268 | }; |
1269 | ||
844a3b63 PW |
1270 | /* mcbsp5 */ |
1271 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
7d7e1eba TL |
1272 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
1273 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, | |
1274 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
1275 | { .irq = -1 }, | |
844a3b63 PW |
1276 | }; |
1277 | ||
1278 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1279 | { .name = "rx", .dma_req = 22 }, | |
1280 | { .name = "tx", .dma_req = 21 }, | |
1281 | { .dma_req = -1 } | |
1282 | }; | |
1283 | ||
1284 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1285 | .name = "mcbsp5", | |
1286 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1287 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1288 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1289 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1290 | .prcm = { |
1291 | .omap2 = { | |
046465b7 | 1292 | .prcm_reg_id = 1, |
844a3b63 PW |
1293 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1294 | .module_offs = CORE_MOD, | |
70034d38 | 1295 | .idlest_reg_id = 1, |
844a3b63 | 1296 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1297 | }, |
1298 | }, | |
7039154b PU |
1299 | .opt_clks = mcbsp15_opt_clks, |
1300 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1301 | }; |
1302 | ||
844a3b63 PW |
1303 | /* 'mcbsp sidetone' class */ |
1304 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1305 | .sysc_offs = 0x0010, | |
1306 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1307 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1308 | }; | |
046465b7 | 1309 | |
844a3b63 PW |
1310 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1311 | .name = "mcbsp_sidetone", | |
1312 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1313 | }; |
1314 | ||
844a3b63 PW |
1315 | /* mcbsp2_sidetone */ |
1316 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
7d7e1eba TL |
1317 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
1318 | { .irq = -1 }, | |
70034d38 VC |
1319 | }; |
1320 | ||
844a3b63 PW |
1321 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1322 | .name = "mcbsp2_sidetone", | |
1323 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1324 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1325 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1326 | .prcm = { |
1327 | .omap2 = { | |
046465b7 | 1328 | .prcm_reg_id = 1, |
844a3b63 PW |
1329 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1330 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1331 | .idlest_reg_id = 1, |
844a3b63 | 1332 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1333 | }, |
1334 | }, | |
4bf90f65 KM |
1335 | }; |
1336 | ||
844a3b63 PW |
1337 | /* mcbsp3_sidetone */ |
1338 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
7d7e1eba TL |
1339 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
1340 | { .irq = -1 }, | |
4bf90f65 KM |
1341 | }; |
1342 | ||
844a3b63 PW |
1343 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1344 | .name = "mcbsp3_sidetone", | |
1345 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1346 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1347 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1348 | .prcm = { |
4bf90f65 | 1349 | .omap2 = { |
4bf90f65 | 1350 | .prcm_reg_id = 1, |
844a3b63 PW |
1351 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1352 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1353 | .idlest_reg_id = 1, |
844a3b63 | 1354 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1355 | }, |
1356 | }, | |
4bf90f65 KM |
1357 | }; |
1358 | ||
844a3b63 PW |
1359 | /* SR common */ |
1360 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1361 | .clkact_shift = 20, | |
1362 | }; | |
4bf90f65 | 1363 | |
844a3b63 PW |
1364 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1365 | .sysc_offs = 0x24, | |
1366 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1367 | .clockact = CLOCKACT_TEST_ICLK, | |
1368 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1369 | }; |
1370 | ||
844a3b63 PW |
1371 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1372 | .name = "smartreflex", | |
1373 | .sysc = &omap34xx_sr_sysc, | |
1374 | .rev = 1, | |
e04d9e1e SG |
1375 | }; |
1376 | ||
844a3b63 PW |
1377 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1378 | .sidle_shift = 24, | |
1379 | .enwkup_shift = 26, | |
1380 | }; | |
e04d9e1e | 1381 | |
844a3b63 PW |
1382 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1383 | .sysc_offs = 0x38, | |
1384 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1385 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1386 | SYSC_NO_CACHE), | |
1387 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1388 | }; | |
1389 | ||
1390 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1391 | .name = "smartreflex", | |
1392 | .sysc = &omap36xx_sr_sysc, | |
1393 | .rev = 2, | |
1394 | }; | |
1395 | ||
1396 | /* SR1 */ | |
1397 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1398 | .sensor_voltdm_name = "mpu_iva", | |
1399 | }; | |
1400 | ||
1401 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
7d7e1eba TL |
1402 | { .irq = 18 + OMAP_INTC_START, }, |
1403 | { .irq = -1 }, | |
844a3b63 PW |
1404 | }; |
1405 | ||
1406 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1407 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1408 | .class = &omap34xx_smartreflex_hwmod_class, |
1409 | .main_clk = "sr1_fck", | |
1410 | .prcm = { | |
e04d9e1e | 1411 | .omap2 = { |
844a3b63 PW |
1412 | .prcm_reg_id = 1, |
1413 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1414 | .module_offs = WKUP_MOD, | |
1415 | .idlest_reg_id = 1, | |
1416 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1417 | }, | |
e04d9e1e | 1418 | }, |
844a3b63 PW |
1419 | .dev_attr = &sr1_dev_attr, |
1420 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1421 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1422 | }; |
1423 | ||
844a3b63 | 1424 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1425 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1426 | .class = &omap36xx_smartreflex_hwmod_class, |
1427 | .main_clk = "sr1_fck", | |
1428 | .prcm = { | |
e04d9e1e | 1429 | .omap2 = { |
844a3b63 PW |
1430 | .prcm_reg_id = 1, |
1431 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1432 | .module_offs = WKUP_MOD, | |
1433 | .idlest_reg_id = 1, | |
1434 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1435 | }, | |
e04d9e1e | 1436 | }, |
844a3b63 PW |
1437 | .dev_attr = &sr1_dev_attr, |
1438 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1439 | }; |
1440 | ||
844a3b63 PW |
1441 | /* SR2 */ |
1442 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1443 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1444 | }; |
1445 | ||
844a3b63 | 1446 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
7d7e1eba TL |
1447 | { .irq = 19 + OMAP_INTC_START, }, |
1448 | { .irq = -1 }, | |
844a3b63 PW |
1449 | }; |
1450 | ||
1451 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1452 | .name = "smartreflex_core", |
844a3b63 PW |
1453 | .class = &omap34xx_smartreflex_hwmod_class, |
1454 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1455 | .prcm = { |
1456 | .omap2 = { | |
1457 | .prcm_reg_id = 1, | |
844a3b63 PW |
1458 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1459 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1460 | .idlest_reg_id = 1, |
844a3b63 | 1461 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1462 | }, |
1463 | }, | |
844a3b63 PW |
1464 | .dev_attr = &sr2_dev_attr, |
1465 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1466 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1467 | }; |
1468 | ||
844a3b63 | 1469 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1470 | .name = "smartreflex_core", |
844a3b63 PW |
1471 | .class = &omap36xx_smartreflex_hwmod_class, |
1472 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1473 | .prcm = { |
1474 | .omap2 = { | |
1475 | .prcm_reg_id = 1, | |
844a3b63 PW |
1476 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1477 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1478 | .idlest_reg_id = 1, |
844a3b63 | 1479 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1480 | }, |
1481 | }, | |
844a3b63 PW |
1482 | .dev_attr = &sr2_dev_attr, |
1483 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1484 | }; |
1485 | ||
1ac6d46e | 1486 | /* |
844a3b63 PW |
1487 | * 'mailbox' class |
1488 | * mailbox module allowing communication between the on-chip processors | |
1489 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1490 | */ |
1491 | ||
844a3b63 PW |
1492 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1493 | .rev_offs = 0x000, | |
1494 | .sysc_offs = 0x010, | |
1495 | .syss_offs = 0x014, | |
1496 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1497 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1498 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1499 | .sysc_fields = &omap_hwmod_sysc_type1, |
1500 | }; | |
1501 | ||
844a3b63 PW |
1502 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1503 | .name = "mailbox", | |
1504 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1505 | }; |
1506 | ||
844a3b63 | 1507 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
7d7e1eba TL |
1508 | { .irq = 26 + OMAP_INTC_START, }, |
1509 | { .irq = -1 }, | |
e04d9e1e SG |
1510 | }; |
1511 | ||
844a3b63 PW |
1512 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1513 | .name = "mailbox", | |
1514 | .class = &omap3xxx_mailbox_hwmod_class, | |
1515 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1516 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1517 | .prcm = { |
1518 | .omap2 = { | |
1519 | .prcm_reg_id = 1, | |
844a3b63 PW |
1520 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1521 | .module_offs = CORE_MOD, | |
1522 | .idlest_reg_id = 1, | |
1523 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1524 | }, |
1525 | }, | |
e04d9e1e SG |
1526 | }; |
1527 | ||
1528 | /* | |
844a3b63 PW |
1529 | * 'mcspi' class |
1530 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1531 | * bus | |
e04d9e1e SG |
1532 | */ |
1533 | ||
844a3b63 PW |
1534 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1535 | .rev_offs = 0x0000, | |
1536 | .sysc_offs = 0x0010, | |
1537 | .syss_offs = 0x0014, | |
1538 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1539 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1540 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1541 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1542 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1543 | }; |
1544 | ||
844a3b63 PW |
1545 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1546 | .name = "mcspi", | |
1547 | .sysc = &omap34xx_mcspi_sysc, | |
1548 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1549 | }; |
1550 | ||
844a3b63 PW |
1551 | /* mcspi1 */ |
1552 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1553 | .num_chipselect = 4, | |
e04d9e1e SG |
1554 | }; |
1555 | ||
844a3b63 PW |
1556 | static struct omap_hwmod omap34xx_mcspi1 = { |
1557 | .name = "mcspi1", | |
1558 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1559 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1560 | .main_clk = "mcspi1_fck", | |
1561 | .prcm = { | |
e04d9e1e | 1562 | .omap2 = { |
844a3b63 PW |
1563 | .module_offs = CORE_MOD, |
1564 | .prcm_reg_id = 1, | |
1565 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1566 | .idlest_reg_id = 1, | |
1567 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1568 | }, | |
e04d9e1e | 1569 | }, |
844a3b63 PW |
1570 | .class = &omap34xx_mcspi_class, |
1571 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1572 | }; |
1573 | ||
844a3b63 PW |
1574 | /* mcspi2 */ |
1575 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1576 | .num_chipselect = 2, | |
6c3d7e34 TV |
1577 | }; |
1578 | ||
844a3b63 PW |
1579 | static struct omap_hwmod omap34xx_mcspi2 = { |
1580 | .name = "mcspi2", | |
1581 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1582 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1583 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1584 | .prcm = { |
1585 | .omap2 = { | |
844a3b63 | 1586 | .module_offs = CORE_MOD, |
e04d9e1e | 1587 | .prcm_reg_id = 1, |
844a3b63 PW |
1588 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1589 | .idlest_reg_id = 1, | |
1590 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1591 | }, |
1592 | }, | |
844a3b63 PW |
1593 | .class = &omap34xx_mcspi_class, |
1594 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1595 | }; |
1596 | ||
844a3b63 PW |
1597 | /* mcspi3 */ |
1598 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
1599 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
1600 | { .irq = -1 }, | |
844a3b63 PW |
1601 | }; |
1602 | ||
1603 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1604 | { .name = "tx0", .dma_req = 15 }, | |
1605 | { .name = "rx0", .dma_req = 16 }, | |
1606 | { .name = "tx1", .dma_req = 23 }, | |
1607 | { .name = "rx1", .dma_req = 24 }, | |
1608 | { .dma_req = -1 } | |
e04d9e1e SG |
1609 | }; |
1610 | ||
844a3b63 PW |
1611 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1612 | .num_chipselect = 2, | |
6c3d7e34 TV |
1613 | }; |
1614 | ||
844a3b63 PW |
1615 | static struct omap_hwmod omap34xx_mcspi3 = { |
1616 | .name = "mcspi3", | |
1617 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1618 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1619 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1620 | .prcm = { |
1621 | .omap2 = { | |
844a3b63 | 1622 | .module_offs = CORE_MOD, |
e04d9e1e | 1623 | .prcm_reg_id = 1, |
844a3b63 PW |
1624 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1625 | .idlest_reg_id = 1, | |
1626 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1627 | }, |
1628 | }, | |
844a3b63 PW |
1629 | .class = &omap34xx_mcspi_class, |
1630 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1631 | }; |
1632 | ||
844a3b63 PW |
1633 | /* mcspi4 */ |
1634 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
7d7e1eba TL |
1635 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
1636 | { .irq = -1 }, | |
e04d9e1e SG |
1637 | }; |
1638 | ||
844a3b63 PW |
1639 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1640 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1641 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1642 | { .dma_req = -1 } | |
6c3d7e34 TV |
1643 | }; |
1644 | ||
844a3b63 PW |
1645 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1646 | .num_chipselect = 1, | |
1647 | }; | |
1648 | ||
1649 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1650 | .name = "mcspi4", | |
1651 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1652 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1653 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1654 | .prcm = { |
1655 | .omap2 = { | |
844a3b63 | 1656 | .module_offs = CORE_MOD, |
e04d9e1e | 1657 | .prcm_reg_id = 1, |
844a3b63 PW |
1658 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1659 | .idlest_reg_id = 1, | |
1660 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1661 | }, |
1662 | }, | |
844a3b63 PW |
1663 | .class = &omap34xx_mcspi_class, |
1664 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1665 | }; |
1666 | ||
844a3b63 PW |
1667 | /* usbhsotg */ |
1668 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1669 | .rev_offs = 0x0400, | |
1670 | .sysc_offs = 0x0404, | |
1671 | .syss_offs = 0x0408, | |
1672 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1673 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1674 | SYSC_HAS_AUTOIDLE), | |
1675 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1676 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1677 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1678 | }; | |
4fe20e97 | 1679 | |
844a3b63 PW |
1680 | static struct omap_hwmod_class usbotg_class = { |
1681 | .name = "usbotg", | |
1682 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1683 | }; |
1684 | ||
844a3b63 PW |
1685 | /* usb_otg_hs */ |
1686 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1687 | ||
7d7e1eba TL |
1688 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
1689 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
1690 | { .irq = -1 }, | |
844a3b63 PW |
1691 | }; |
1692 | ||
1693 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1694 | .name = "usb_otg_hs", | |
1695 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1696 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1697 | .prcm = { |
1698 | .omap2 = { | |
4fe20e97 | 1699 | .prcm_reg_id = 1, |
844a3b63 PW |
1700 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1701 | .module_offs = CORE_MOD, | |
4fe20e97 | 1702 | .idlest_reg_id = 1, |
844a3b63 PW |
1703 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1704 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1705 | }, |
1706 | }, | |
844a3b63 PW |
1707 | .class = &usbotg_class, |
1708 | ||
1709 | /* | |
1710 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1711 | * broken when autoidle is enabled | |
1712 | * workaround is to disable the autoidle bit at module level. | |
1713 | */ | |
1714 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1715 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1716 | }; |
1717 | ||
844a3b63 PW |
1718 | /* usb_otg_hs */ |
1719 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
7d7e1eba TL |
1720 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
1721 | { .irq = -1 }, | |
4fe20e97 RN |
1722 | }; |
1723 | ||
844a3b63 PW |
1724 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1725 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1726 | }; |
1727 | ||
1728 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1729 | .name = "am35x_otg_hs", | |
1730 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1731 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1732 | .class = &am35xx_usbotg_class, |
89ea2583 | 1733 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1734 | }; |
1735 | ||
844a3b63 PW |
1736 | /* MMC/SD/SDIO common */ |
1737 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1738 | .rev_offs = 0x1fc, | |
1739 | .sysc_offs = 0x10, | |
1740 | .syss_offs = 0x14, | |
1741 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1742 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1743 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1744 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1745 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1746 | }; | |
4fe20e97 | 1747 | |
844a3b63 PW |
1748 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1749 | .name = "mmc", | |
1750 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1751 | }; |
1752 | ||
844a3b63 PW |
1753 | /* MMC/SD/SDIO1 */ |
1754 | ||
1755 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
7d7e1eba TL |
1756 | { .irq = 83 + OMAP_INTC_START, }, |
1757 | { .irq = -1 }, | |
4fe20e97 RN |
1758 | }; |
1759 | ||
844a3b63 PW |
1760 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1761 | { .name = "tx", .dma_req = 61, }, | |
1762 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1763 | { .dma_req = -1 } |
4fe20e97 RN |
1764 | }; |
1765 | ||
844a3b63 PW |
1766 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1767 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1768 | }; | |
1769 | ||
1770 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1771 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1772 | }; | |
1773 | ||
1774 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1775 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1776 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1777 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1778 | }; | |
1779 | ||
1780 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1781 | .name = "mmc1", | |
1782 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1783 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1784 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1785 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1786 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1787 | .prcm = { |
1788 | .omap2 = { | |
1789 | .module_offs = CORE_MOD, | |
1790 | .prcm_reg_id = 1, | |
844a3b63 | 1791 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1792 | .idlest_reg_id = 1, |
844a3b63 | 1793 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1794 | }, |
1795 | }, | |
844a3b63 PW |
1796 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1797 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1798 | }; |
1799 | ||
844a3b63 PW |
1800 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1801 | .name = "mmc1", | |
1802 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1803 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1804 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1805 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1806 | .main_clk = "mmchs1_fck", | |
1807 | .prcm = { | |
1808 | .omap2 = { | |
1809 | .module_offs = CORE_MOD, | |
1810 | .prcm_reg_id = 1, | |
1811 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1812 | .idlest_reg_id = 1, | |
1813 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1814 | }, | |
70034d38 | 1815 | }, |
844a3b63 PW |
1816 | .dev_attr = &mmc1_dev_attr, |
1817 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1818 | }; |
1819 | ||
844a3b63 | 1820 | /* MMC/SD/SDIO2 */ |
70034d38 | 1821 | |
844a3b63 | 1822 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
1823 | { .irq = 86 + OMAP_INTC_START, }, |
1824 | { .irq = -1 }, | |
70034d38 VC |
1825 | }; |
1826 | ||
844a3b63 PW |
1827 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1828 | { .name = "tx", .dma_req = 47, }, | |
1829 | { .name = "rx", .dma_req = 48, }, | |
1830 | { .dma_req = -1 } | |
70034d38 VC |
1831 | }; |
1832 | ||
844a3b63 PW |
1833 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1834 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1835 | }; |
1836 | ||
844a3b63 PW |
1837 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1838 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1839 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1840 | }; |
1841 | ||
844a3b63 PW |
1842 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1843 | .name = "mmc2", | |
1844 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1845 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1846 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1847 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1848 | .main_clk = "mmchs2_fck", | |
1849 | .prcm = { | |
1850 | .omap2 = { | |
1851 | .module_offs = CORE_MOD, | |
1852 | .prcm_reg_id = 1, | |
1853 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1854 | .idlest_reg_id = 1, | |
1855 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1856 | }, | |
70034d38 | 1857 | }, |
844a3b63 PW |
1858 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1859 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1860 | }; |
1861 | ||
844a3b63 PW |
1862 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1863 | .name = "mmc2", | |
1864 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1865 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1866 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1867 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1868 | .main_clk = "mmchs2_fck", | |
1869 | .prcm = { | |
1870 | .omap2 = { | |
1871 | .module_offs = CORE_MOD, | |
1872 | .prcm_reg_id = 1, | |
1873 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1874 | .idlest_reg_id = 1, | |
1875 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1876 | }, | |
1877 | }, | |
1878 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1879 | }; |
1880 | ||
844a3b63 PW |
1881 | /* MMC/SD/SDIO3 */ |
1882 | ||
1883 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
7d7e1eba TL |
1884 | { .irq = 94 + OMAP_INTC_START, }, |
1885 | { .irq = -1 }, | |
70034d38 VC |
1886 | }; |
1887 | ||
844a3b63 PW |
1888 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1889 | { .name = "tx", .dma_req = 77, }, | |
1890 | { .name = "rx", .dma_req = 78, }, | |
1891 | { .dma_req = -1 } | |
70034d38 VC |
1892 | }; |
1893 | ||
844a3b63 PW |
1894 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1895 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1896 | }; |
1897 | ||
844a3b63 PW |
1898 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1899 | .name = "mmc3", | |
1900 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1901 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1902 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1903 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1904 | .main_clk = "mmchs3_fck", | |
1905 | .prcm = { | |
1906 | .omap2 = { | |
1907 | .prcm_reg_id = 1, | |
1908 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1909 | .idlest_reg_id = 1, | |
1910 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1911 | }, | |
1912 | }, | |
1913 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1914 | }; |
1915 | ||
1916 | /* | |
844a3b63 PW |
1917 | * 'usb_host_hs' class |
1918 | * high-speed multi-port usb host controller | |
70034d38 VC |
1919 | */ |
1920 | ||
844a3b63 | 1921 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1922 | .rev_offs = 0x0000, |
1923 | .sysc_offs = 0x0010, | |
1924 | .syss_offs = 0x0014, | |
844a3b63 PW |
1925 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1926 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1927 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1928 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1929 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1930 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1931 | }; |
1932 | ||
844a3b63 PW |
1933 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1934 | .name = "usb_host_hs", | |
1935 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1936 | }; |
1937 | ||
844a3b63 PW |
1938 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1939 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1940 | }; |
1941 | ||
844a3b63 | 1942 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
7d7e1eba TL |
1943 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
1944 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, | |
1945 | { .irq = -1 }, | |
70034d38 VC |
1946 | }; |
1947 | ||
844a3b63 PW |
1948 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1949 | .name = "usb_host_hs", | |
1950 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1951 | .clkdm_name = "l3_init_clkdm", | |
1952 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1953 | .main_clk = "usbhost_48m_fck", | |
1954 | .prcm = { | |
70034d38 | 1955 | .omap2 = { |
844a3b63 | 1956 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1957 | .prcm_reg_id = 1, |
844a3b63 | 1958 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1959 | .idlest_reg_id = 1, |
844a3b63 PW |
1960 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1961 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1962 | }, |
1963 | }, | |
844a3b63 PW |
1964 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1965 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1966 | |
844a3b63 PW |
1967 | /* |
1968 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1969 | * id: i660 | |
1970 | * | |
1971 | * Description: | |
1972 | * In the following configuration : | |
1973 | * - USBHOST module is set to smart-idle mode | |
1974 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1975 | * happens when the system is going to a low power mode : all ports | |
1976 | * have been suspended, the master part of the USBHOST module has | |
1977 | * entered the standby state, and SW has cut the functional clocks) | |
1978 | * - an USBHOST interrupt occurs before the module is able to answer | |
1979 | * idle_ack, typically a remote wakeup IRQ. | |
1980 | * Then the USB HOST module will enter a deadlock situation where it | |
1981 | * is no more accessible nor functional. | |
1982 | * | |
1983 | * Workaround: | |
1984 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1985 | */ | |
1986 | ||
1987 | /* | |
1988 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1989 | * Id: i571 | |
1990 | * | |
1991 | * Description: | |
1992 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1993 | * ready to enter the standby state (i.e. all ports are suspended and | |
1994 | * all attached devices are in suspend mode), then it can wrongly assert | |
1995 | * the Mstandby signal too early while there are still some residual OCP | |
1996 | * transactions ongoing. If this condition occurs, the internal state | |
1997 | * machine may go to an undefined state and the USB link may be stuck | |
1998 | * upon the next resume. | |
1999 | * | |
2000 | * Workaround: | |
2001 | * Don't use smart standby; use only force standby, | |
2002 | * hence HWMOD_SWSUP_MSTANDBY | |
2003 | */ | |
2004 | ||
2005 | /* | |
2006 | * During system boot; If the hwmod framework resets the module | |
2007 | * the module will have smart idle settings; which can lead to deadlock | |
2008 | * (above Errata Id:i660); so, dont reset the module during boot; | |
2009 | * Use HWMOD_INIT_NO_RESET. | |
2010 | */ | |
70034d38 | 2011 | |
844a3b63 PW |
2012 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
2013 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
2014 | }; |
2015 | ||
844a3b63 PW |
2016 | /* |
2017 | * 'usb_tll_hs' class | |
2018 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
2019 | */ | |
2020 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
2021 | .rev_offs = 0x0000, | |
2022 | .sysc_offs = 0x0010, | |
2023 | .syss_offs = 0x0014, | |
2024 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2025 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2026 | SYSC_HAS_AUTOIDLE), | |
2027 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2028 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
2029 | }; |
2030 | ||
844a3b63 PW |
2031 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
2032 | .name = "usb_tll_hs", | |
2033 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
2034 | }; |
2035 | ||
844a3b63 | 2036 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
7d7e1eba TL |
2037 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
2038 | { .irq = -1 }, | |
70034d38 VC |
2039 | }; |
2040 | ||
844a3b63 PW |
2041 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
2042 | .name = "usb_tll_hs", | |
2043 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
2044 | .clkdm_name = "l3_init_clkdm", | |
2045 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
2046 | .main_clk = "usbtll_fck", | |
2047 | .prcm = { | |
70034d38 | 2048 | .omap2 = { |
844a3b63 PW |
2049 | .module_offs = CORE_MOD, |
2050 | .prcm_reg_id = 3, | |
2051 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
2052 | .idlest_reg_id = 3, | |
2053 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
2054 | }, |
2055 | }, | |
70034d38 VC |
2056 | }; |
2057 | ||
45a4bb06 PW |
2058 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
2059 | .name = "hdq1w", | |
2060 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
2061 | .main_clk = "hdq_fck", | |
2062 | .prcm = { | |
2063 | .omap2 = { | |
2064 | .module_offs = CORE_MOD, | |
2065 | .prcm_reg_id = 1, | |
2066 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
2067 | .idlest_reg_id = 1, | |
2068 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
2069 | }, | |
2070 | }, | |
2071 | .class = &omap2_hdq1w_class, | |
2072 | }; | |
2073 | ||
8f993a01 TK |
2074 | /* SAD2D */ |
2075 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
2076 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
2077 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
2078 | }; | |
2079 | ||
2080 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
2081 | .name = "sad2d", | |
2082 | }; | |
2083 | ||
2084 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
2085 | .name = "sad2d", | |
2086 | .rst_lines = omap3xxx_sad2d_resets, | |
2087 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
2088 | .main_clk = "sad2d_ick", | |
2089 | .prcm = { | |
2090 | .omap2 = { | |
2091 | .module_offs = CORE_MOD, | |
2092 | .prcm_reg_id = 1, | |
2093 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
2094 | .idlest_reg_id = 1, | |
2095 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
2096 | }, | |
2097 | }, | |
2098 | .class = &omap3xxx_sad2d_class, | |
2099 | }; | |
2100 | ||
c8d82ff6 VH |
2101 | /* |
2102 | * '32K sync counter' class | |
2103 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2104 | */ | |
2105 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2106 | .rev_offs = 0x0000, | |
2107 | .sysc_offs = 0x0004, | |
2108 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2109 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2110 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2111 | }; | |
2112 | ||
2113 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2114 | .name = "counter", | |
2115 | .sysc = &omap3xxx_counter_sysc, | |
2116 | }; | |
2117 | ||
2118 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2119 | .name = "counter_32k", | |
2120 | .class = &omap3xxx_counter_hwmod_class, | |
2121 | .clkdm_name = "wkup_clkdm", | |
2122 | .flags = HWMOD_SWSUP_SIDLE, | |
2123 | .main_clk = "wkup_32k_fck", | |
2124 | .prcm = { | |
2125 | .omap2 = { | |
2126 | .module_offs = WKUP_MOD, | |
2127 | .prcm_reg_id = 1, | |
2128 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2129 | .idlest_reg_id = 1, | |
2130 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2131 | }, | |
2132 | }, | |
2133 | }; | |
2134 | ||
49484a60 AM |
2135 | /* |
2136 | * 'gpmc' class | |
2137 | * general purpose memory controller | |
2138 | */ | |
2139 | ||
2140 | static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { | |
2141 | .rev_offs = 0x0000, | |
2142 | .sysc_offs = 0x0010, | |
2143 | .syss_offs = 0x0014, | |
2144 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2145 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2146 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2147 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2148 | }; | |
2149 | ||
2150 | static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { | |
2151 | .name = "gpmc", | |
2152 | .sysc = &omap3xxx_gpmc_sysc, | |
2153 | }; | |
2154 | ||
2155 | static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { | |
2156 | { .irq = 20 }, | |
2157 | { .irq = -1 } | |
2158 | }; | |
2159 | ||
2160 | static struct omap_hwmod omap3xxx_gpmc_hwmod = { | |
2161 | .name = "gpmc", | |
2162 | .class = &omap3xxx_gpmc_hwmod_class, | |
2163 | .clkdm_name = "core_l3_clkdm", | |
2164 | .mpu_irqs = omap3xxx_gpmc_irqs, | |
2165 | .main_clk = "gpmc_fck", | |
2166 | /* | |
2167 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP | |
2168 | * block. It is not being added due to any known bugs with | |
2169 | * resetting the GPMC IP block, but rather because any timings | |
2170 | * set by the bootloader are not being correctly programmed by | |
2171 | * the kernel from the board file or DT data. | |
2172 | * HWMOD_INIT_NO_RESET should be removed ASAP. | |
2173 | */ | |
2174 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | | |
2175 | HWMOD_NO_IDLEST), | |
2176 | }; | |
2177 | ||
844a3b63 PW |
2178 | /* |
2179 | * interfaces | |
2180 | */ | |
2181 | ||
2182 | /* L3 -> L4_CORE interface */ | |
2183 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2184 | .master = &omap3xxx_l3_main_hwmod, | |
2185 | .slave = &omap3xxx_l4_core_hwmod, | |
2186 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2187 | }; |
2188 | ||
844a3b63 PW |
2189 | /* L3 -> L4_PER interface */ |
2190 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2191 | .master = &omap3xxx_l3_main_hwmod, | |
2192 | .slave = &omap3xxx_l4_per_hwmod, | |
2193 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2194 | }; |
2195 | ||
844a3b63 PW |
2196 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2197 | { | |
2198 | .pa_start = 0x68000000, | |
2199 | .pa_end = 0x6800ffff, | |
2200 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2201 | }, |
844a3b63 | 2202 | { } |
70034d38 VC |
2203 | }; |
2204 | ||
844a3b63 PW |
2205 | /* MPU -> L3 interface */ |
2206 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2207 | .master = &omap3xxx_mpu_hwmod, | |
2208 | .slave = &omap3xxx_l3_main_hwmod, | |
2209 | .addr = omap3xxx_l3_main_addrs, | |
2210 | .user = OCP_USER_MPU, | |
70034d38 VC |
2211 | }; |
2212 | ||
c7dad45f JH |
2213 | static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { |
2214 | { | |
2215 | .pa_start = 0x54000000, | |
2216 | .pa_end = 0x547fffff, | |
2217 | .flags = ADDR_TYPE_RT, | |
2218 | }, | |
2219 | { } | |
2220 | }; | |
2221 | ||
2222 | /* l3 -> debugss */ | |
2223 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { | |
2224 | .master = &omap3xxx_l3_main_hwmod, | |
2225 | .slave = &omap3xxx_debugss_hwmod, | |
76a5d9bf | 2226 | .addr = omap3xxx_l4_emu_addrs, |
c7dad45f JH |
2227 | .user = OCP_USER_MPU, |
2228 | }; | |
2229 | ||
844a3b63 PW |
2230 | /* DSS -> l3 */ |
2231 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2232 | .master = &omap3430es1_dss_core_hwmod, | |
2233 | .slave = &omap3xxx_l3_main_hwmod, | |
2234 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2235 | }; |
2236 | ||
844a3b63 PW |
2237 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2238 | .master = &omap3xxx_dss_core_hwmod, | |
2239 | .slave = &omap3xxx_l3_main_hwmod, | |
2240 | .fw = { | |
70034d38 | 2241 | .omap2 = { |
844a3b63 PW |
2242 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2243 | .flags = OMAP_FIREWALL_L3, | |
2244 | } | |
70034d38 | 2245 | }, |
844a3b63 | 2246 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2247 | }; |
2248 | ||
844a3b63 PW |
2249 | /* l3_core -> usbhsotg interface */ |
2250 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2251 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2252 | .slave = &omap3xxx_l3_main_hwmod, |
2253 | .clk = "core_l3_ick", | |
844a3b63 | 2254 | .user = OCP_USER_MPU, |
01438ab6 MK |
2255 | }; |
2256 | ||
844a3b63 PW |
2257 | /* l3_core -> am35xx_usbhsotg interface */ |
2258 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2259 | .master = &am35xx_usbhsotg_hwmod, | |
2260 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2261 | .clk = "hsotgusb_ick", |
844a3b63 | 2262 | .user = OCP_USER_MPU, |
01438ab6 | 2263 | }; |
89ea2583 | 2264 | |
8f993a01 TK |
2265 | /* l3_core -> sad2d interface */ |
2266 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
2267 | .master = &omap3xxx_sad2d_hwmod, | |
2268 | .slave = &omap3xxx_l3_main_hwmod, | |
2269 | .clk = "core_l3_ick", | |
2270 | .user = OCP_USER_MPU, | |
2271 | }; | |
2272 | ||
844a3b63 PW |
2273 | /* L4_CORE -> L4_WKUP interface */ |
2274 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2275 | .master = &omap3xxx_l4_core_hwmod, | |
2276 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2277 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2278 | }; |
2279 | ||
844a3b63 PW |
2280 | /* L4 CORE -> MMC1 interface */ |
2281 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2282 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2283 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2284 | .clk = "mmchs1_ick", | |
2285 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2286 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2287 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2288 | }; |
2289 | ||
844a3b63 PW |
2290 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2291 | .master = &omap3xxx_l4_core_hwmod, | |
2292 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2293 | .clk = "mmchs1_ick", | |
2294 | .addr = omap2430_mmc1_addr_space, | |
2295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2296 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2297 | }; |
2298 | ||
844a3b63 PW |
2299 | /* L4 CORE -> MMC2 interface */ |
2300 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2301 | .master = &omap3xxx_l4_core_hwmod, | |
2302 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2303 | .clk = "mmchs2_ick", | |
2304 | .addr = omap2430_mmc2_addr_space, | |
2305 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2306 | .flags = OMAP_FIREWALL_L4 | |
2307 | }; | |
70034d38 | 2308 | |
844a3b63 PW |
2309 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2310 | .master = &omap3xxx_l4_core_hwmod, | |
2311 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2312 | .clk = "mmchs2_ick", | |
2313 | .addr = omap2430_mmc2_addr_space, | |
2314 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2315 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2316 | }; |
2317 | ||
844a3b63 PW |
2318 | /* L4 CORE -> MMC3 interface */ |
2319 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2320 | { | |
2321 | .pa_start = 0x480ad000, | |
2322 | .pa_end = 0x480ad1ff, | |
2323 | .flags = ADDR_TYPE_RT, | |
2324 | }, | |
2325 | { } | |
70034d38 VC |
2326 | }; |
2327 | ||
844a3b63 PW |
2328 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2329 | .master = &omap3xxx_l4_core_hwmod, | |
2330 | .slave = &omap3xxx_mmc3_hwmod, | |
2331 | .clk = "mmchs3_ick", | |
2332 | .addr = omap3xxx_mmc3_addr_space, | |
2333 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2334 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2335 | }; |
2336 | ||
844a3b63 PW |
2337 | /* L4 CORE -> UART1 interface */ |
2338 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2339 | { |
844a3b63 PW |
2340 | .pa_start = OMAP3_UART1_BASE, |
2341 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2342 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2343 | }, |
78183f3f | 2344 | { } |
70034d38 VC |
2345 | }; |
2346 | ||
844a3b63 | 2347 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2348 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2349 | .slave = &omap3xxx_uart1_hwmod, |
2350 | .clk = "uart1_ick", | |
2351 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2352 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2353 | }; |
2354 | ||
844a3b63 PW |
2355 | /* L4 CORE -> UART2 interface */ |
2356 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2357 | { | |
2358 | .pa_start = OMAP3_UART2_BASE, | |
2359 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2360 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2361 | }, |
844a3b63 | 2362 | { } |
70034d38 VC |
2363 | }; |
2364 | ||
844a3b63 PW |
2365 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2366 | .master = &omap3xxx_l4_core_hwmod, | |
2367 | .slave = &omap3xxx_uart2_hwmod, | |
2368 | .clk = "uart2_ick", | |
2369 | .addr = omap3xxx_uart2_addr_space, | |
2370 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2371 | }; |
2372 | ||
844a3b63 PW |
2373 | /* L4 PER -> UART3 interface */ |
2374 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2375 | { |
844a3b63 PW |
2376 | .pa_start = OMAP3_UART3_BASE, |
2377 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2378 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2379 | }, |
78183f3f | 2380 | { } |
70034d38 VC |
2381 | }; |
2382 | ||
844a3b63 | 2383 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2384 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2385 | .slave = &omap3xxx_uart3_hwmod, |
2386 | .clk = "uart3_ick", | |
2387 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2388 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2389 | }; |
2390 | ||
844a3b63 PW |
2391 | /* L4 PER -> UART4 interface */ |
2392 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2393 | { | |
2394 | .pa_start = OMAP3_UART4_BASE, | |
2395 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2396 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2397 | }, |
844a3b63 | 2398 | { } |
70034d38 VC |
2399 | }; |
2400 | ||
844a3b63 PW |
2401 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2402 | .master = &omap3xxx_l4_per_hwmod, | |
2403 | .slave = &omap36xx_uart4_hwmod, | |
2404 | .clk = "uart4_ick", | |
2405 | .addr = omap36xx_uart4_addr_space, | |
2406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2407 | }; |
2408 | ||
844a3b63 PW |
2409 | /* AM35xx: L4 CORE -> UART4 interface */ |
2410 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2411 | { |
844a3b63 PW |
2412 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2413 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2414 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2415 | }, |
bf765237 | 2416 | { } |
70034d38 VC |
2417 | }; |
2418 | ||
844a3b63 PW |
2419 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2420 | .master = &omap3xxx_l4_core_hwmod, | |
2421 | .slave = &am35xx_uart4_hwmod, | |
2422 | .clk = "uart4_ick", | |
2423 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2424 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2425 | }; | |
2426 | ||
844a3b63 PW |
2427 | /* L4 CORE -> I2C1 interface */ |
2428 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2429 | .master = &omap3xxx_l4_core_hwmod, | |
2430 | .slave = &omap3xxx_i2c1_hwmod, | |
2431 | .clk = "i2c1_ick", | |
2432 | .addr = omap2_i2c1_addr_space, | |
2433 | .fw = { | |
2434 | .omap2 = { | |
2435 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2436 | .l4_prot_group = 7, | |
2437 | .flags = OMAP_FIREWALL_L4, | |
2438 | } | |
2439 | }, | |
2440 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2441 | }; |
2442 | ||
844a3b63 PW |
2443 | /* L4 CORE -> I2C2 interface */ |
2444 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2445 | .master = &omap3xxx_l4_core_hwmod, | |
2446 | .slave = &omap3xxx_i2c2_hwmod, | |
2447 | .clk = "i2c2_ick", | |
2448 | .addr = omap2_i2c2_addr_space, | |
2449 | .fw = { | |
70034d38 | 2450 | .omap2 = { |
844a3b63 PW |
2451 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2452 | .l4_prot_group = 7, | |
2453 | .flags = OMAP_FIREWALL_L4, | |
2454 | } | |
70034d38 | 2455 | }, |
844a3b63 | 2456 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2457 | }; |
2458 | ||
844a3b63 PW |
2459 | /* L4 CORE -> I2C3 interface */ |
2460 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2461 | { | |
2462 | .pa_start = 0x48060000, | |
2463 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2464 | .flags = ADDR_TYPE_RT, | |
2465 | }, | |
2466 | { } | |
70034d38 VC |
2467 | }; |
2468 | ||
844a3b63 PW |
2469 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2470 | .master = &omap3xxx_l4_core_hwmod, | |
2471 | .slave = &omap3xxx_i2c3_hwmod, | |
2472 | .clk = "i2c3_ick", | |
2473 | .addr = omap3xxx_i2c3_addr_space, | |
2474 | .fw = { | |
2475 | .omap2 = { | |
2476 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2477 | .l4_prot_group = 7, | |
2478 | .flags = OMAP_FIREWALL_L4, | |
2479 | } | |
2480 | }, | |
2481 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2482 | }; |
2483 | ||
844a3b63 PW |
2484 | /* L4 CORE -> SR1 interface */ |
2485 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2486 | { |
844a3b63 PW |
2487 | .pa_start = OMAP34XX_SR1_BASE, |
2488 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2489 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2490 | }, |
78183f3f | 2491 | { } |
70034d38 VC |
2492 | }; |
2493 | ||
844a3b63 PW |
2494 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2495 | .master = &omap3xxx_l4_core_hwmod, | |
2496 | .slave = &omap34xx_sr1_hwmod, | |
2497 | .clk = "sr_l4_ick", | |
2498 | .addr = omap3_sr1_addr_space, | |
2499 | .user = OCP_USER_MPU, | |
70034d38 VC |
2500 | }; |
2501 | ||
844a3b63 PW |
2502 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2503 | .master = &omap3xxx_l4_core_hwmod, | |
2504 | .slave = &omap36xx_sr1_hwmod, | |
2505 | .clk = "sr_l4_ick", | |
2506 | .addr = omap3_sr1_addr_space, | |
2507 | .user = OCP_USER_MPU, | |
2508 | }; | |
2509 | ||
2510 | /* L4 CORE -> SR1 interface */ | |
2511 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2512 | { | |
2513 | .pa_start = OMAP34XX_SR2_BASE, | |
2514 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2515 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2516 | }, |
844a3b63 | 2517 | { } |
70034d38 VC |
2518 | }; |
2519 | ||
844a3b63 PW |
2520 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2521 | .master = &omap3xxx_l4_core_hwmod, | |
2522 | .slave = &omap34xx_sr2_hwmod, | |
2523 | .clk = "sr_l4_ick", | |
2524 | .addr = omap3_sr2_addr_space, | |
2525 | .user = OCP_USER_MPU, | |
70034d38 VC |
2526 | }; |
2527 | ||
844a3b63 PW |
2528 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2529 | .master = &omap3xxx_l4_core_hwmod, | |
2530 | .slave = &omap36xx_sr2_hwmod, | |
2531 | .clk = "sr_l4_ick", | |
2532 | .addr = omap3_sr2_addr_space, | |
2533 | .user = OCP_USER_MPU, | |
70034d38 VC |
2534 | }; |
2535 | ||
844a3b63 | 2536 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2537 | { |
844a3b63 PW |
2538 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2539 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2540 | .flags = ADDR_TYPE_RT |
2541 | }, | |
78183f3f | 2542 | { } |
70034d38 VC |
2543 | }; |
2544 | ||
844a3b63 PW |
2545 | /* l4_core -> usbhsotg */ |
2546 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2547 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2548 | .slave = &omap3xxx_usbhsotg_hwmod, |
2549 | .clk = "l4_ick", | |
2550 | .addr = omap3xxx_usbhsotg_addrs, | |
2551 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2552 | }; |
2553 | ||
844a3b63 PW |
2554 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2555 | { | |
2556 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2557 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2558 | .flags = ADDR_TYPE_RT | |
70034d38 | 2559 | }, |
844a3b63 | 2560 | { } |
70034d38 VC |
2561 | }; |
2562 | ||
844a3b63 PW |
2563 | /* l4_core -> usbhsotg */ |
2564 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2565 | .master = &omap3xxx_l4_core_hwmod, | |
2566 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2567 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2568 | .addr = am35xx_usbhsotg_addrs, |
2569 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2570 | }; |
2571 | ||
844a3b63 PW |
2572 | /* L4_WKUP -> L4_SEC interface */ |
2573 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2574 | .master = &omap3xxx_l4_wkup_hwmod, | |
2575 | .slave = &omap3xxx_l4_sec_hwmod, | |
2576 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2577 | }; |
2578 | ||
844a3b63 PW |
2579 | /* IVA2 <- L3 interface */ |
2580 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2581 | .master = &omap3xxx_l3_main_hwmod, | |
2582 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2583 | .clk = "core_l3_ick", |
844a3b63 | 2584 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2585 | }; |
2586 | ||
844a3b63 | 2587 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2588 | { |
844a3b63 PW |
2589 | .pa_start = 0x48318000, |
2590 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2591 | .flags = ADDR_TYPE_RT |
2592 | }, | |
78183f3f | 2593 | { } |
01438ab6 MK |
2594 | }; |
2595 | ||
844a3b63 PW |
2596 | /* l4_wkup -> timer1 */ |
2597 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2598 | .master = &omap3xxx_l4_wkup_hwmod, | |
2599 | .slave = &omap3xxx_timer1_hwmod, | |
2600 | .clk = "gpt1_ick", | |
2601 | .addr = omap3xxx_timer1_addrs, | |
2602 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2603 | }; |
2604 | ||
844a3b63 PW |
2605 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2606 | { | |
2607 | .pa_start = 0x49032000, | |
2608 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2609 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2610 | }, |
844a3b63 | 2611 | { } |
01438ab6 MK |
2612 | }; |
2613 | ||
844a3b63 PW |
2614 | /* l4_per -> timer2 */ |
2615 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2616 | .master = &omap3xxx_l4_per_hwmod, | |
2617 | .slave = &omap3xxx_timer2_hwmod, | |
2618 | .clk = "gpt2_ick", | |
2619 | .addr = omap3xxx_timer2_addrs, | |
2620 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2621 | }; |
2622 | ||
844a3b63 | 2623 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2624 | { |
844a3b63 PW |
2625 | .pa_start = 0x49034000, |
2626 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2627 | .flags = ADDR_TYPE_RT |
2628 | }, | |
78183f3f | 2629 | { } |
01438ab6 MK |
2630 | }; |
2631 | ||
844a3b63 PW |
2632 | /* l4_per -> timer3 */ |
2633 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2634 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2635 | .slave = &omap3xxx_timer3_hwmod, |
2636 | .clk = "gpt3_ick", | |
2637 | .addr = omap3xxx_timer3_addrs, | |
2638 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2639 | }; |
2640 | ||
844a3b63 PW |
2641 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2642 | { | |
2643 | .pa_start = 0x49036000, | |
2644 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2645 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2646 | }, |
844a3b63 | 2647 | { } |
01438ab6 MK |
2648 | }; |
2649 | ||
844a3b63 PW |
2650 | /* l4_per -> timer4 */ |
2651 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2652 | .master = &omap3xxx_l4_per_hwmod, | |
2653 | .slave = &omap3xxx_timer4_hwmod, | |
2654 | .clk = "gpt4_ick", | |
2655 | .addr = omap3xxx_timer4_addrs, | |
2656 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2657 | }; |
2658 | ||
844a3b63 PW |
2659 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2660 | { | |
2661 | .pa_start = 0x49038000, | |
2662 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2663 | .flags = ADDR_TYPE_RT | |
2664 | }, | |
2665 | { } | |
d3442726 TG |
2666 | }; |
2667 | ||
844a3b63 PW |
2668 | /* l4_per -> timer5 */ |
2669 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2670 | .master = &omap3xxx_l4_per_hwmod, | |
2671 | .slave = &omap3xxx_timer5_hwmod, | |
2672 | .clk = "gpt5_ick", | |
2673 | .addr = omap3xxx_timer5_addrs, | |
2674 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2675 | }; |
2676 | ||
844a3b63 PW |
2677 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2678 | { | |
2679 | .pa_start = 0x4903A000, | |
2680 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2681 | .flags = ADDR_TYPE_RT | |
2682 | }, | |
2683 | { } | |
cea6b942 SG |
2684 | }; |
2685 | ||
844a3b63 PW |
2686 | /* l4_per -> timer6 */ |
2687 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2688 | .master = &omap3xxx_l4_per_hwmod, | |
2689 | .slave = &omap3xxx_timer6_hwmod, | |
2690 | .clk = "gpt6_ick", | |
2691 | .addr = omap3xxx_timer6_addrs, | |
2692 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2693 | }; |
2694 | ||
844a3b63 PW |
2695 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2696 | { | |
2697 | .pa_start = 0x4903C000, | |
2698 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2699 | .flags = ADDR_TYPE_RT | |
d3442726 | 2700 | }, |
844a3b63 | 2701 | { } |
d3442726 TG |
2702 | }; |
2703 | ||
844a3b63 PW |
2704 | /* l4_per -> timer7 */ |
2705 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2706 | .master = &omap3xxx_l4_per_hwmod, | |
2707 | .slave = &omap3xxx_timer7_hwmod, | |
2708 | .clk = "gpt7_ick", | |
2709 | .addr = omap3xxx_timer7_addrs, | |
2710 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2711 | }; |
2712 | ||
844a3b63 PW |
2713 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2714 | { | |
2715 | .pa_start = 0x4903E000, | |
2716 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2717 | .flags = ADDR_TYPE_RT | |
d3442726 | 2718 | }, |
844a3b63 | 2719 | { } |
d3442726 TG |
2720 | }; |
2721 | ||
844a3b63 PW |
2722 | /* l4_per -> timer8 */ |
2723 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2724 | .master = &omap3xxx_l4_per_hwmod, | |
2725 | .slave = &omap3xxx_timer8_hwmod, | |
2726 | .clk = "gpt8_ick", | |
2727 | .addr = omap3xxx_timer8_addrs, | |
2728 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2729 | }; |
2730 | ||
844a3b63 PW |
2731 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2732 | { | |
2733 | .pa_start = 0x49040000, | |
2734 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2735 | .flags = ADDR_TYPE_RT | |
2736 | }, | |
2737 | { } | |
2738 | }; | |
0f9dfdd3 | 2739 | |
844a3b63 PW |
2740 | /* l4_per -> timer9 */ |
2741 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2742 | .master = &omap3xxx_l4_per_hwmod, | |
2743 | .slave = &omap3xxx_timer9_hwmod, | |
2744 | .clk = "gpt9_ick", | |
2745 | .addr = omap3xxx_timer9_addrs, | |
2746 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2747 | }; |
2748 | ||
844a3b63 PW |
2749 | /* l4_core -> timer10 */ |
2750 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2751 | .master = &omap3xxx_l4_core_hwmod, | |
2752 | .slave = &omap3xxx_timer10_hwmod, | |
2753 | .clk = "gpt10_ick", | |
2754 | .addr = omap2_timer10_addrs, | |
2755 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2756 | }; |
2757 | ||
844a3b63 PW |
2758 | /* l4_core -> timer11 */ |
2759 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2760 | .master = &omap3xxx_l4_core_hwmod, | |
2761 | .slave = &omap3xxx_timer11_hwmod, | |
2762 | .clk = "gpt11_ick", | |
2763 | .addr = omap2_timer11_addrs, | |
2764 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2765 | }; |
2766 | ||
844a3b63 | 2767 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2768 | { |
844a3b63 PW |
2769 | .pa_start = 0x48304000, |
2770 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2771 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2772 | }, |
78183f3f | 2773 | { } |
0f9dfdd3 FC |
2774 | }; |
2775 | ||
844a3b63 PW |
2776 | /* l4_core -> timer12 */ |
2777 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2778 | .master = &omap3xxx_l4_sec_hwmod, | |
2779 | .slave = &omap3xxx_timer12_hwmod, | |
2780 | .clk = "gpt12_ick", | |
2781 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2782 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2783 | }; | |
2784 | ||
844a3b63 PW |
2785 | /* l4_wkup -> wd_timer2 */ |
2786 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2787 | { | |
2788 | .pa_start = 0x48314000, | |
2789 | .pa_end = 0x4831407f, | |
2790 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2791 | }, |
844a3b63 | 2792 | { } |
0f9dfdd3 FC |
2793 | }; |
2794 | ||
844a3b63 PW |
2795 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2796 | .master = &omap3xxx_l4_wkup_hwmod, | |
2797 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2798 | .clk = "wdt2_ick", | |
2799 | .addr = omap3xxx_wd_timer2_addrs, | |
2800 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2801 | }; | |
2802 | ||
2803 | /* l4_core -> dss */ | |
2804 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2805 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2806 | .slave = &omap3430es1_dss_core_hwmod, |
2807 | .clk = "dss_ick", | |
2808 | .addr = omap2_dss_addrs, | |
2809 | .fw = { | |
2810 | .omap2 = { | |
2811 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2812 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2813 | .flags = OMAP_FIREWALL_L4, | |
2814 | } | |
2815 | }, | |
0f616a4e C |
2816 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2817 | }; | |
2818 | ||
844a3b63 | 2819 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2820 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2821 | .slave = &omap3xxx_dss_core_hwmod, |
2822 | .clk = "dss_ick", | |
2823 | .addr = omap2_dss_addrs, | |
2824 | .fw = { | |
2825 | .omap2 = { | |
2826 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2827 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2828 | .flags = OMAP_FIREWALL_L4, | |
2829 | } | |
2830 | }, | |
0f616a4e C |
2831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2832 | }; | |
2833 | ||
844a3b63 PW |
2834 | /* l4_core -> dss_dispc */ |
2835 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2836 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2837 | .slave = &omap3xxx_dss_dispc_hwmod, |
2838 | .clk = "dss_ick", | |
2839 | .addr = omap2_dss_dispc_addrs, | |
2840 | .fw = { | |
2841 | .omap2 = { | |
2842 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2843 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2844 | .flags = OMAP_FIREWALL_L4, | |
2845 | } | |
2846 | }, | |
0f616a4e C |
2847 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2848 | }; | |
2849 | ||
844a3b63 | 2850 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2851 | { |
844a3b63 PW |
2852 | .pa_start = 0x4804FC00, |
2853 | .pa_end = 0x4804FFFF, | |
2854 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2855 | }, |
78183f3f | 2856 | { } |
0f616a4e C |
2857 | }; |
2858 | ||
844a3b63 PW |
2859 | /* l4_core -> dss_dsi1 */ |
2860 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2861 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2862 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2863 | .clk = "dss_ick", | |
2864 | .addr = omap3xxx_dss_dsi1_addrs, | |
2865 | .fw = { | |
2866 | .omap2 = { | |
2867 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2868 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2869 | .flags = OMAP_FIREWALL_L4, | |
2870 | } | |
2871 | }, | |
0f616a4e C |
2872 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2873 | }; | |
2874 | ||
844a3b63 PW |
2875 | /* l4_core -> dss_rfbi */ |
2876 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2877 | .master = &omap3xxx_l4_core_hwmod, | |
2878 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2879 | .clk = "dss_ick", | |
2880 | .addr = omap2_dss_rfbi_addrs, | |
2881 | .fw = { | |
0f616a4e | 2882 | .omap2 = { |
844a3b63 PW |
2883 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2884 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2885 | .flags = OMAP_FIREWALL_L4, | |
2886 | } | |
0f616a4e | 2887 | }, |
844a3b63 | 2888 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2889 | }; |
2890 | ||
844a3b63 PW |
2891 | /* l4_core -> dss_venc */ |
2892 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2893 | .master = &omap3xxx_l4_core_hwmod, | |
2894 | .slave = &omap3xxx_dss_venc_hwmod, | |
2895 | .clk = "dss_ick", | |
2896 | .addr = omap2_dss_venc_addrs, | |
2897 | .fw = { | |
70034d38 | 2898 | .omap2 = { |
844a3b63 PW |
2899 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2900 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2901 | .flags = OMAP_FIREWALL_L4, | |
2902 | } | |
70034d38 | 2903 | }, |
844a3b63 PW |
2904 | .flags = OCPIF_SWSUP_IDLE, |
2905 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2906 | }; |
2907 | ||
844a3b63 PW |
2908 | /* l4_wkup -> gpio1 */ |
2909 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2910 | { | |
2911 | .pa_start = 0x48310000, | |
2912 | .pa_end = 0x483101ff, | |
2913 | .flags = ADDR_TYPE_RT | |
2914 | }, | |
2915 | { } | |
70034d38 VC |
2916 | }; |
2917 | ||
844a3b63 PW |
2918 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2919 | .master = &omap3xxx_l4_wkup_hwmod, | |
2920 | .slave = &omap3xxx_gpio1_hwmod, | |
2921 | .addr = omap3xxx_gpio1_addrs, | |
2922 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2923 | }; |
2924 | ||
844a3b63 PW |
2925 | /* l4_per -> gpio2 */ |
2926 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2927 | { | |
2928 | .pa_start = 0x49050000, | |
2929 | .pa_end = 0x490501ff, | |
2930 | .flags = ADDR_TYPE_RT | |
70034d38 | 2931 | }, |
844a3b63 | 2932 | { } |
70034d38 VC |
2933 | }; |
2934 | ||
844a3b63 PW |
2935 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2936 | .master = &omap3xxx_l4_per_hwmod, | |
2937 | .slave = &omap3xxx_gpio2_hwmod, | |
2938 | .addr = omap3xxx_gpio2_addrs, | |
2939 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2940 | }; |
2941 | ||
844a3b63 PW |
2942 | /* l4_per -> gpio3 */ |
2943 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2944 | { | |
2945 | .pa_start = 0x49052000, | |
2946 | .pa_end = 0x490521ff, | |
2947 | .flags = ADDR_TYPE_RT | |
2948 | }, | |
2949 | { } | |
70034d38 VC |
2950 | }; |
2951 | ||
844a3b63 PW |
2952 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2953 | .master = &omap3xxx_l4_per_hwmod, | |
2954 | .slave = &omap3xxx_gpio3_hwmod, | |
2955 | .addr = omap3xxx_gpio3_addrs, | |
2956 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2957 | }; |
2958 | ||
5486474c PW |
2959 | /* |
2960 | * 'mmu' class | |
2961 | * The memory management unit performs virtual to physical address translation | |
2962 | * for its requestors. | |
2963 | */ | |
2964 | ||
2965 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2966 | .rev_offs = 0x000, | |
2967 | .sysc_offs = 0x010, | |
2968 | .syss_offs = 0x014, | |
2969 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2970 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2971 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2972 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2973 | }; | |
2974 | ||
2975 | static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { | |
2976 | .name = "mmu", | |
2977 | .sysc = &mmu_sysc, | |
2978 | }; | |
2979 | ||
2980 | /* mmu isp */ | |
2981 | ||
2982 | static struct omap_mmu_dev_attr mmu_isp_dev_attr = { | |
2983 | .da_start = 0x0, | |
2984 | .da_end = 0xfffff000, | |
2985 | .nr_tlb_entries = 8, | |
2986 | }; | |
2987 | ||
2988 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod; | |
2989 | static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { | |
2990 | { .irq = 24 }, | |
2991 | { .irq = -1 } | |
2992 | }; | |
2993 | ||
2994 | static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { | |
2995 | { | |
2996 | .pa_start = 0x480bd400, | |
2997 | .pa_end = 0x480bd47f, | |
2998 | .flags = ADDR_TYPE_RT, | |
2999 | }, | |
3000 | { } | |
3001 | }; | |
3002 | ||
3003 | /* l4_core -> mmu isp */ | |
3004 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { | |
3005 | .master = &omap3xxx_l4_core_hwmod, | |
3006 | .slave = &omap3xxx_mmu_isp_hwmod, | |
3007 | .addr = omap3xxx_mmu_isp_addrs, | |
3008 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3009 | }; | |
3010 | ||
3011 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |
3012 | .name = "mmu_isp", | |
3013 | .class = &omap3xxx_mmu_hwmod_class, | |
3014 | .mpu_irqs = omap3xxx_mmu_isp_irqs, | |
3015 | .main_clk = "cam_ick", | |
3016 | .dev_attr = &mmu_isp_dev_attr, | |
3017 | .flags = HWMOD_NO_IDLEST, | |
3018 | }; | |
3019 | ||
3020 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3021 | ||
3022 | /* mmu iva */ | |
3023 | ||
3024 | static struct omap_mmu_dev_attr mmu_iva_dev_attr = { | |
3025 | .da_start = 0x11000000, | |
3026 | .da_end = 0xfffff000, | |
3027 | .nr_tlb_entries = 32, | |
3028 | }; | |
3029 | ||
3030 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod; | |
3031 | static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { | |
3032 | { .irq = 28 }, | |
3033 | { .irq = -1 } | |
3034 | }; | |
3035 | ||
3036 | static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { | |
3037 | { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, | |
3038 | }; | |
3039 | ||
3040 | static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { | |
3041 | { | |
3042 | .pa_start = 0x5d000000, | |
3043 | .pa_end = 0x5d00007f, | |
3044 | .flags = ADDR_TYPE_RT, | |
3045 | }, | |
3046 | { } | |
3047 | }; | |
3048 | ||
3049 | /* l3_main -> iva mmu */ | |
3050 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { | |
3051 | .master = &omap3xxx_l3_main_hwmod, | |
3052 | .slave = &omap3xxx_mmu_iva_hwmod, | |
3053 | .addr = omap3xxx_mmu_iva_addrs, | |
3054 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3055 | }; | |
3056 | ||
3057 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |
3058 | .name = "mmu_iva", | |
3059 | .class = &omap3xxx_mmu_hwmod_class, | |
3060 | .mpu_irqs = omap3xxx_mmu_iva_irqs, | |
3061 | .rst_lines = omap3xxx_mmu_iva_resets, | |
3062 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | |
3063 | .main_clk = "iva2_ck", | |
3064 | .prcm = { | |
3065 | .omap2 = { | |
3066 | .module_offs = OMAP3430_IVA2_MOD, | |
3067 | }, | |
3068 | }, | |
3069 | .dev_attr = &mmu_iva_dev_attr, | |
3070 | .flags = HWMOD_NO_IDLEST, | |
3071 | }; | |
3072 | ||
3073 | #endif | |
3074 | ||
844a3b63 PW |
3075 | /* l4_per -> gpio4 */ |
3076 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
3077 | { | |
3078 | .pa_start = 0x49054000, | |
3079 | .pa_end = 0x490541ff, | |
3080 | .flags = ADDR_TYPE_RT | |
70034d38 | 3081 | }, |
844a3b63 | 3082 | { } |
70034d38 VC |
3083 | }; |
3084 | ||
844a3b63 PW |
3085 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
3086 | .master = &omap3xxx_l4_per_hwmod, | |
3087 | .slave = &omap3xxx_gpio4_hwmod, | |
3088 | .addr = omap3xxx_gpio4_addrs, | |
3089 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3090 | }; |
3091 | ||
844a3b63 PW |
3092 | /* l4_per -> gpio5 */ |
3093 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
3094 | { | |
3095 | .pa_start = 0x49056000, | |
3096 | .pa_end = 0x490561ff, | |
3097 | .flags = ADDR_TYPE_RT | |
3098 | }, | |
3099 | { } | |
01438ab6 MK |
3100 | }; |
3101 | ||
844a3b63 PW |
3102 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
3103 | .master = &omap3xxx_l4_per_hwmod, | |
3104 | .slave = &omap3xxx_gpio5_hwmod, | |
3105 | .addr = omap3xxx_gpio5_addrs, | |
3106 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3107 | }; |
3108 | ||
844a3b63 PW |
3109 | /* l4_per -> gpio6 */ |
3110 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
3111 | { | |
3112 | .pa_start = 0x49058000, | |
3113 | .pa_end = 0x490581ff, | |
3114 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3115 | }, |
844a3b63 | 3116 | { } |
01438ab6 MK |
3117 | }; |
3118 | ||
844a3b63 PW |
3119 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
3120 | .master = &omap3xxx_l4_per_hwmod, | |
3121 | .slave = &omap3xxx_gpio6_hwmod, | |
3122 | .addr = omap3xxx_gpio6_addrs, | |
3123 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3124 | }; |
3125 | ||
844a3b63 PW |
3126 | /* dma_system -> L3 */ |
3127 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
3128 | .master = &omap3xxx_dma_system_hwmod, | |
3129 | .slave = &omap3xxx_l3_main_hwmod, | |
3130 | .clk = "core_l3_ick", | |
3131 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3132 | }; |
3133 | ||
844a3b63 PW |
3134 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
3135 | { | |
3136 | .pa_start = 0x48056000, | |
3137 | .pa_end = 0x48056fff, | |
3138 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3139 | }, |
844a3b63 | 3140 | { } |
01438ab6 MK |
3141 | }; |
3142 | ||
844a3b63 PW |
3143 | /* l4_cfg -> dma_system */ |
3144 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
3145 | .master = &omap3xxx_l4_core_hwmod, | |
3146 | .slave = &omap3xxx_dma_system_hwmod, | |
3147 | .clk = "core_l4_ick", | |
3148 | .addr = omap3xxx_dma_system_addrs, | |
3149 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3150 | }; |
3151 | ||
844a3b63 PW |
3152 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
3153 | { | |
3154 | .name = "mpu", | |
3155 | .pa_start = 0x48074000, | |
3156 | .pa_end = 0x480740ff, | |
3157 | .flags = ADDR_TYPE_RT | |
3158 | }, | |
3159 | { } | |
d3442726 TG |
3160 | }; |
3161 | ||
844a3b63 PW |
3162 | /* l4_core -> mcbsp1 */ |
3163 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
3164 | .master = &omap3xxx_l4_core_hwmod, | |
3165 | .slave = &omap3xxx_mcbsp1_hwmod, | |
3166 | .clk = "mcbsp1_ick", | |
3167 | .addr = omap3xxx_mcbsp1_addrs, | |
3168 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3169 | }; |
3170 | ||
844a3b63 PW |
3171 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
3172 | { | |
3173 | .name = "mpu", | |
3174 | .pa_start = 0x49022000, | |
3175 | .pa_end = 0x490220ff, | |
3176 | .flags = ADDR_TYPE_RT | |
3177 | }, | |
3178 | { } | |
d3442726 TG |
3179 | }; |
3180 | ||
844a3b63 PW |
3181 | /* l4_per -> mcbsp2 */ |
3182 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
3183 | .master = &omap3xxx_l4_per_hwmod, | |
3184 | .slave = &omap3xxx_mcbsp2_hwmod, | |
3185 | .clk = "mcbsp2_ick", | |
3186 | .addr = omap3xxx_mcbsp2_addrs, | |
3187 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3188 | }; |
3189 | ||
844a3b63 PW |
3190 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
3191 | { | |
3192 | .name = "mpu", | |
3193 | .pa_start = 0x49024000, | |
3194 | .pa_end = 0x490240ff, | |
3195 | .flags = ADDR_TYPE_RT | |
3196 | }, | |
3197 | { } | |
d3442726 TG |
3198 | }; |
3199 | ||
844a3b63 PW |
3200 | /* l4_per -> mcbsp3 */ |
3201 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
3202 | .master = &omap3xxx_l4_per_hwmod, | |
3203 | .slave = &omap3xxx_mcbsp3_hwmod, | |
3204 | .clk = "mcbsp3_ick", | |
3205 | .addr = omap3xxx_mcbsp3_addrs, | |
3206 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
3207 | }; |
3208 | ||
844a3b63 PW |
3209 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
3210 | { | |
3211 | .name = "mpu", | |
3212 | .pa_start = 0x49026000, | |
3213 | .pa_end = 0x490260ff, | |
3214 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 3215 | }, |
844a3b63 | 3216 | { } |
a52e2ab6 PW |
3217 | }; |
3218 | ||
844a3b63 PW |
3219 | /* l4_per -> mcbsp4 */ |
3220 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
3221 | .master = &omap3xxx_l4_per_hwmod, | |
3222 | .slave = &omap3xxx_mcbsp4_hwmod, | |
3223 | .clk = "mcbsp4_ick", | |
3224 | .addr = omap3xxx_mcbsp4_addrs, | |
3225 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3226 | }; |
3227 | ||
844a3b63 PW |
3228 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
3229 | { | |
3230 | .name = "mpu", | |
3231 | .pa_start = 0x48096000, | |
3232 | .pa_end = 0x480960ff, | |
3233 | .flags = ADDR_TYPE_RT | |
3234 | }, | |
3235 | { } | |
3236 | }; | |
b163605e | 3237 | |
844a3b63 PW |
3238 | /* l4_core -> mcbsp5 */ |
3239 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
3240 | .master = &omap3xxx_l4_core_hwmod, | |
3241 | .slave = &omap3xxx_mcbsp5_hwmod, | |
3242 | .clk = "mcbsp5_ick", | |
3243 | .addr = omap3xxx_mcbsp5_addrs, | |
3244 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3245 | }; |
3246 | ||
844a3b63 PW |
3247 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
3248 | { | |
3249 | .name = "sidetone", | |
3250 | .pa_start = 0x49028000, | |
3251 | .pa_end = 0x490280ff, | |
3252 | .flags = ADDR_TYPE_RT | |
3253 | }, | |
3254 | { } | |
d3442726 TG |
3255 | }; |
3256 | ||
844a3b63 PW |
3257 | /* l4_per -> mcbsp2_sidetone */ |
3258 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
3259 | .master = &omap3xxx_l4_per_hwmod, | |
3260 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
3261 | .clk = "mcbsp2_ick", | |
3262 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
3263 | .user = OCP_USER_MPU, | |
b163605e PW |
3264 | }; |
3265 | ||
844a3b63 PW |
3266 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
3267 | { | |
3268 | .name = "sidetone", | |
3269 | .pa_start = 0x4902A000, | |
3270 | .pa_end = 0x4902A0ff, | |
3271 | .flags = ADDR_TYPE_RT | |
3272 | }, | |
3273 | { } | |
a52e2ab6 PW |
3274 | }; |
3275 | ||
844a3b63 PW |
3276 | /* l4_per -> mcbsp3_sidetone */ |
3277 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
3278 | .master = &omap3xxx_l4_per_hwmod, | |
3279 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
3280 | .clk = "mcbsp3_ick", | |
3281 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
3282 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
3283 | }; |
3284 | ||
844a3b63 PW |
3285 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
3286 | { | |
3287 | .pa_start = 0x48094000, | |
3288 | .pa_end = 0x480941ff, | |
3289 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3290 | }, |
844a3b63 | 3291 | { } |
d3442726 TG |
3292 | }; |
3293 | ||
844a3b63 PW |
3294 | /* l4_core -> mailbox */ |
3295 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3296 | .master = &omap3xxx_l4_core_hwmod, | |
3297 | .slave = &omap3xxx_mailbox_hwmod, | |
3298 | .addr = omap3xxx_mailbox_addrs, | |
3299 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3300 | }; | |
b163605e | 3301 | |
844a3b63 PW |
3302 | /* l4 core -> mcspi1 interface */ |
3303 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3304 | .master = &omap3xxx_l4_core_hwmod, | |
3305 | .slave = &omap34xx_mcspi1, | |
3306 | .clk = "mcspi1_ick", | |
3307 | .addr = omap2_mcspi1_addr_space, | |
3308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3309 | }; |
3310 | ||
844a3b63 PW |
3311 | /* l4 core -> mcspi2 interface */ |
3312 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3313 | .master = &omap3xxx_l4_core_hwmod, | |
3314 | .slave = &omap34xx_mcspi2, | |
3315 | .clk = "mcspi2_ick", | |
3316 | .addr = omap2_mcspi2_addr_space, | |
3317 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3318 | }; |
3319 | ||
844a3b63 PW |
3320 | /* l4 core -> mcspi3 interface */ |
3321 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3322 | .master = &omap3xxx_l4_core_hwmod, | |
3323 | .slave = &omap34xx_mcspi3, | |
3324 | .clk = "mcspi3_ick", | |
3325 | .addr = omap2430_mcspi3_addr_space, | |
3326 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3327 | }; |
3328 | ||
844a3b63 PW |
3329 | /* l4 core -> mcspi4 interface */ |
3330 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3331 | { | |
3332 | .pa_start = 0x480ba000, | |
3333 | .pa_end = 0x480ba0ff, | |
3334 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3335 | }, |
844a3b63 PW |
3336 | { } |
3337 | }; | |
3338 | ||
3339 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3340 | .master = &omap3xxx_l4_core_hwmod, | |
3341 | .slave = &omap34xx_mcspi4, | |
3342 | .clk = "mcspi4_ick", | |
3343 | .addr = omap34xx_mcspi4_addr_space, | |
3344 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3345 | }; |
3346 | ||
de231388 KM |
3347 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3348 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3349 | .slave = &omap3xxx_l3_main_hwmod, | |
3350 | .clk = "core_l3_ick", | |
3351 | .user = OCP_USER_MPU, | |
3352 | }; | |
3353 | ||
de231388 KM |
3354 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3355 | { | |
3356 | .name = "uhh", | |
3357 | .pa_start = 0x48064000, | |
3358 | .pa_end = 0x480643ff, | |
3359 | .flags = ADDR_TYPE_RT | |
3360 | }, | |
3361 | { | |
3362 | .name = "ohci", | |
3363 | .pa_start = 0x48064400, | |
3364 | .pa_end = 0x480647ff, | |
3365 | }, | |
3366 | { | |
3367 | .name = "ehci", | |
3368 | .pa_start = 0x48064800, | |
3369 | .pa_end = 0x48064cff, | |
3370 | }, | |
3371 | {} | |
3372 | }; | |
3373 | ||
3374 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3375 | .master = &omap3xxx_l4_core_hwmod, | |
3376 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3377 | .clk = "usbhost_ick", | |
3378 | .addr = omap3xxx_usb_host_hs_addrs, | |
3379 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3380 | }; | |
3381 | ||
de231388 KM |
3382 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3383 | { | |
3384 | .name = "tll", | |
3385 | .pa_start = 0x48062000, | |
3386 | .pa_end = 0x48062fff, | |
3387 | .flags = ADDR_TYPE_RT | |
3388 | }, | |
3389 | {} | |
3390 | }; | |
3391 | ||
3392 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3393 | .master = &omap3xxx_l4_core_hwmod, | |
3394 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3395 | .clk = "usbtll_ick", | |
3396 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3397 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3398 | }; | |
3399 | ||
45a4bb06 PW |
3400 | /* l4_core -> hdq1w interface */ |
3401 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3402 | .master = &omap3xxx_l4_core_hwmod, | |
3403 | .slave = &omap3xxx_hdq1w_hwmod, | |
3404 | .clk = "hdq_ick", | |
3405 | .addr = omap2_hdq1w_addr_space, | |
3406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3407 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3408 | }; | |
3409 | ||
c8d82ff6 VH |
3410 | /* l4_wkup -> 32ksync_counter */ |
3411 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3412 | { | |
3413 | .pa_start = 0x48320000, | |
3414 | .pa_end = 0x4832001f, | |
3415 | .flags = ADDR_TYPE_RT | |
3416 | }, | |
3417 | { } | |
3418 | }; | |
3419 | ||
49484a60 AM |
3420 | static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { |
3421 | { | |
3422 | .pa_start = 0x6e000000, | |
3423 | .pa_end = 0x6e000fff, | |
3424 | .flags = ADDR_TYPE_RT | |
3425 | }, | |
3426 | { } | |
3427 | }; | |
3428 | ||
c8d82ff6 VH |
3429 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { |
3430 | .master = &omap3xxx_l4_wkup_hwmod, | |
3431 | .slave = &omap3xxx_counter_32k_hwmod, | |
3432 | .clk = "omap_32ksync_ick", | |
3433 | .addr = omap3xxx_counter_32k_addrs, | |
3434 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3435 | }; | |
3436 | ||
31ba8808 MG |
3437 | /* am35xx has Davinci MDIO & EMAC */ |
3438 | static struct omap_hwmod_class am35xx_mdio_class = { | |
3439 | .name = "davinci_mdio", | |
3440 | }; | |
3441 | ||
3442 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
3443 | .name = "davinci_mdio", | |
3444 | .class = &am35xx_mdio_class, | |
3445 | .flags = HWMOD_NO_IDLEST, | |
3446 | }; | |
3447 | ||
3448 | /* | |
3449 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3450 | * but this will probably require some additional hwmod core support, | |
3451 | * so is left as a future to-do item. | |
3452 | */ | |
3453 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
3454 | .master = &am35xx_mdio_hwmod, | |
3455 | .slave = &omap3xxx_l3_main_hwmod, | |
3456 | .clk = "emac_fck", | |
3457 | .user = OCP_USER_MPU, | |
3458 | }; | |
3459 | ||
3460 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | |
3461 | { | |
3462 | .pa_start = AM35XX_IPSS_MDIO_BASE, | |
3463 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | |
3464 | .flags = ADDR_TYPE_RT, | |
3465 | }, | |
3466 | { } | |
3467 | }; | |
3468 | ||
3469 | /* l4_core -> davinci mdio */ | |
3470 | /* | |
3471 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3472 | * but this will probably require some additional hwmod core support, | |
3473 | * so is left as a future to-do item. | |
3474 | */ | |
3475 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
3476 | .master = &omap3xxx_l4_core_hwmod, | |
3477 | .slave = &am35xx_mdio_hwmod, | |
3478 | .clk = "emac_fck", | |
3479 | .addr = am35xx_mdio_addrs, | |
3480 | .user = OCP_USER_MPU, | |
3481 | }; | |
3482 | ||
3483 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | |
7d7e1eba TL |
3484 | { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, |
3485 | { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, | |
3486 | { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, | |
3487 | { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, | |
3488 | { .irq = -1 }, | |
31ba8808 MG |
3489 | }; |
3490 | ||
3491 | static struct omap_hwmod_class am35xx_emac_class = { | |
3492 | .name = "davinci_emac", | |
3493 | }; | |
3494 | ||
3495 | static struct omap_hwmod am35xx_emac_hwmod = { | |
3496 | .name = "davinci_emac", | |
3497 | .mpu_irqs = am35xx_emac_mpu_irqs, | |
3498 | .class = &am35xx_emac_class, | |
3499 | .flags = HWMOD_NO_IDLEST, | |
3500 | }; | |
3501 | ||
3502 | /* l3_core -> davinci emac interface */ | |
3503 | /* | |
3504 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3505 | * but this will probably require some additional hwmod core support, | |
3506 | * so is left as a future to-do item. | |
3507 | */ | |
3508 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
3509 | .master = &am35xx_emac_hwmod, | |
3510 | .slave = &omap3xxx_l3_main_hwmod, | |
3511 | .clk = "emac_ick", | |
3512 | .user = OCP_USER_MPU, | |
3513 | }; | |
3514 | ||
3515 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | |
3516 | { | |
3517 | .pa_start = AM35XX_IPSS_EMAC_BASE, | |
3518 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | |
3519 | .flags = ADDR_TYPE_RT, | |
3520 | }, | |
3521 | { } | |
3522 | }; | |
3523 | ||
3524 | /* l4_core -> davinci emac */ | |
3525 | /* | |
3526 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3527 | * but this will probably require some additional hwmod core support, | |
3528 | * so is left as a future to-do item. | |
3529 | */ | |
3530 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
3531 | .master = &omap3xxx_l4_core_hwmod, | |
3532 | .slave = &am35xx_emac_hwmod, | |
3533 | .clk = "emac_ick", | |
3534 | .addr = am35xx_emac_addrs, | |
3535 | .user = OCP_USER_MPU, | |
3536 | }; | |
3537 | ||
49484a60 AM |
3538 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { |
3539 | .master = &omap3xxx_l3_main_hwmod, | |
3540 | .slave = &omap3xxx_gpmc_hwmod, | |
3541 | .clk = "core_l3_ick", | |
3542 | .addr = omap3xxx_gpmc_addrs, | |
3543 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3544 | }; | |
3545 | ||
0a78c5c5 PW |
3546 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3547 | &omap3xxx_l3_main__l4_core, | |
3548 | &omap3xxx_l3_main__l4_per, | |
3549 | &omap3xxx_mpu__l3_main, | |
c7dad45f | 3550 | &omap3xxx_l3_main__l4_debugss, |
0a78c5c5 PW |
3551 | &omap3xxx_l4_core__l4_wkup, |
3552 | &omap3xxx_l4_core__mmc3, | |
3553 | &omap3_l4_core__uart1, | |
3554 | &omap3_l4_core__uart2, | |
3555 | &omap3_l4_per__uart3, | |
3556 | &omap3_l4_core__i2c1, | |
3557 | &omap3_l4_core__i2c2, | |
3558 | &omap3_l4_core__i2c3, | |
3559 | &omap3xxx_l4_wkup__l4_sec, | |
3560 | &omap3xxx_l4_wkup__timer1, | |
3561 | &omap3xxx_l4_per__timer2, | |
3562 | &omap3xxx_l4_per__timer3, | |
3563 | &omap3xxx_l4_per__timer4, | |
3564 | &omap3xxx_l4_per__timer5, | |
3565 | &omap3xxx_l4_per__timer6, | |
3566 | &omap3xxx_l4_per__timer7, | |
3567 | &omap3xxx_l4_per__timer8, | |
3568 | &omap3xxx_l4_per__timer9, | |
3569 | &omap3xxx_l4_core__timer10, | |
3570 | &omap3xxx_l4_core__timer11, | |
3571 | &omap3xxx_l4_wkup__wd_timer2, | |
3572 | &omap3xxx_l4_wkup__gpio1, | |
3573 | &omap3xxx_l4_per__gpio2, | |
3574 | &omap3xxx_l4_per__gpio3, | |
3575 | &omap3xxx_l4_per__gpio4, | |
3576 | &omap3xxx_l4_per__gpio5, | |
3577 | &omap3xxx_l4_per__gpio6, | |
3578 | &omap3xxx_dma_system__l3, | |
3579 | &omap3xxx_l4_core__dma_system, | |
3580 | &omap3xxx_l4_core__mcbsp1, | |
3581 | &omap3xxx_l4_per__mcbsp2, | |
3582 | &omap3xxx_l4_per__mcbsp3, | |
3583 | &omap3xxx_l4_per__mcbsp4, | |
3584 | &omap3xxx_l4_core__mcbsp5, | |
3585 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3586 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3587 | &omap34xx_l4_core__mcspi1, | |
3588 | &omap34xx_l4_core__mcspi2, | |
3589 | &omap34xx_l4_core__mcspi3, | |
3590 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3591 | &omap3xxx_l4_wkup__counter_32k, |
49484a60 | 3592 | &omap3xxx_l3_main__gpmc, |
d6504acd PW |
3593 | NULL, |
3594 | }; | |
3595 | ||
0a78c5c5 PW |
3596 | /* GP-only hwmod links */ |
3597 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3598 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3599 | NULL |
3600 | }; | |
3601 | ||
0a78c5c5 PW |
3602 | /* 3430ES1-only hwmod links */ |
3603 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3604 | &omap3430es1_dss__l3, | |
3605 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3606 | NULL |
3607 | }; | |
3608 | ||
0a78c5c5 PW |
3609 | /* 3430ES2+-only hwmod links */ |
3610 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3611 | &omap3xxx_dss__l3, | |
3612 | &omap3xxx_l4_core__dss, | |
3613 | &omap3xxx_usbhsotg__l3, | |
3614 | &omap3xxx_l4_core__usbhsotg, | |
3615 | &omap3xxx_usb_host_hs__l3_main_2, | |
3616 | &omap3xxx_l4_core__usb_host_hs, | |
3617 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3618 | NULL |
3619 | }; | |
870ea2b8 | 3620 | |
0a78c5c5 PW |
3621 | /* <= 3430ES3-only hwmod links */ |
3622 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3623 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3624 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3625 | NULL |
3626 | }; | |
3627 | ||
0a78c5c5 PW |
3628 | /* 3430ES3+-only hwmod links */ |
3629 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3630 | &omap3xxx_l4_core__es3plus_mmc1, | |
3631 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3632 | NULL |
3633 | }; | |
3634 | ||
0a78c5c5 PW |
3635 | /* 34xx-only hwmod links (all ES revisions) */ |
3636 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3637 | &omap3xxx_l3__iva, | |
3638 | &omap34xx_l4_core__sr1, | |
3639 | &omap34xx_l4_core__sr2, | |
3640 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3641 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3642 | &omap3xxx_sad2d__l3, |
5486474c PW |
3643 | &omap3xxx_l4_core__mmu_isp, |
3644 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3645 | &omap3xxx_l3_main__mmu_iva, | |
3646 | #endif | |
d6504acd PW |
3647 | NULL |
3648 | }; | |
273ff8c3 | 3649 | |
0a78c5c5 PW |
3650 | /* 36xx-only hwmod links (all ES revisions) */ |
3651 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3652 | &omap3xxx_l3__iva, | |
3653 | &omap36xx_l4_per__uart4, | |
3654 | &omap3xxx_dss__l3, | |
3655 | &omap3xxx_l4_core__dss, | |
3656 | &omap36xx_l4_core__sr1, | |
3657 | &omap36xx_l4_core__sr2, | |
3658 | &omap3xxx_usbhsotg__l3, | |
3659 | &omap3xxx_l4_core__usbhsotg, | |
3660 | &omap3xxx_l4_core__mailbox, | |
3661 | &omap3xxx_usb_host_hs__l3_main_2, | |
3662 | &omap3xxx_l4_core__usb_host_hs, | |
3663 | &omap3xxx_l4_core__usb_tll_hs, | |
3664 | &omap3xxx_l4_core__es3plus_mmc1, | |
3665 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3666 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3667 | &omap3xxx_sad2d__l3, |
5486474c PW |
3668 | &omap3xxx_l4_core__mmu_isp, |
3669 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3670 | &omap3xxx_l3_main__mmu_iva, | |
3671 | #endif | |
d6504acd PW |
3672 | NULL |
3673 | }; | |
3674 | ||
0a78c5c5 PW |
3675 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3676 | &omap3xxx_dss__l3, | |
3677 | &omap3xxx_l4_core__dss, | |
3678 | &am35xx_usbhsotg__l3, | |
3679 | &am35xx_l4_core__usbhsotg, | |
3680 | &am35xx_l4_core__uart4, | |
3681 | &omap3xxx_usb_host_hs__l3_main_2, | |
3682 | &omap3xxx_l4_core__usb_host_hs, | |
3683 | &omap3xxx_l4_core__usb_tll_hs, | |
3684 | &omap3xxx_l4_core__es3plus_mmc1, | |
3685 | &omap3xxx_l4_core__es3plus_mmc2, | |
b1a923d0 | 3686 | &omap3xxx_l4_core__hdq1w, |
31ba8808 MG |
3687 | &am35xx_mdio__l3, |
3688 | &am35xx_l4_core__mdio, | |
3689 | &am35xx_emac__l3, | |
3690 | &am35xx_l4_core__emac, | |
d6504acd | 3691 | NULL |
7359154e PW |
3692 | }; |
3693 | ||
0a78c5c5 PW |
3694 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3695 | &omap3xxx_l4_core__dss_dispc, | |
3696 | &omap3xxx_l4_core__dss_dsi1, | |
3697 | &omap3xxx_l4_core__dss_rfbi, | |
3698 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3699 | NULL |
3700 | }; | |
3701 | ||
7359154e PW |
3702 | int __init omap3xxx_hwmod_init(void) |
3703 | { | |
d6504acd | 3704 | int r; |
0a78c5c5 | 3705 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3706 | unsigned int rev; |
3707 | ||
9ebfd285 KH |
3708 | omap_hwmod_init(); |
3709 | ||
0a78c5c5 PW |
3710 | /* Register hwmod links common to all OMAP3 */ |
3711 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3712 | if (r < 0) |
d6504acd PW |
3713 | return r; |
3714 | ||
0a78c5c5 | 3715 | /* Register GP-only hwmod links. */ |
91a36bdb | 3716 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3717 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3718 | if (r < 0) |
3719 | return r; | |
3720 | } | |
3721 | ||
d6504acd PW |
3722 | rev = omap_rev(); |
3723 | ||
3724 | /* | |
0a78c5c5 | 3725 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3726 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3727 | * All possible revisions should be included in this conditional. | |
3728 | */ | |
3729 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3730 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3731 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3732 | h = omap34xx_hwmod_ocp_ifs; |
68a88b98 | 3733 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3734 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3735 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3736 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3737 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3738 | } else { |
3739 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3740 | return -EINVAL; | |
c09fcc43 | 3741 | } |
d6504acd | 3742 | |
0a78c5c5 | 3743 | r = omap_hwmod_register_links(h); |
ace90216 | 3744 | if (r < 0) |
d6504acd PW |
3745 | return r; |
3746 | ||
3747 | /* | |
0a78c5c5 | 3748 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3749 | * particular family of silicon (e.g., 34xx ES1.0) |
3750 | */ | |
3751 | h = NULL; | |
3752 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3753 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3754 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3755 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3756 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3757 | h = omap3430es2plus_hwmod_ocp_ifs; |
c09fcc43 | 3758 | } |
d6504acd | 3759 | |
a52e2ab6 | 3760 | if (h) { |
0a78c5c5 | 3761 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3762 | if (r < 0) |
3763 | return r; | |
3764 | } | |
3765 | ||
3766 | h = NULL; | |
3767 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3768 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3769 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3770 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3771 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3772 | h = omap3430_es3plus_hwmod_ocp_ifs; |
c09fcc43 | 3773 | } |
a52e2ab6 | 3774 | |
d6504acd | 3775 | if (h) |
0a78c5c5 | 3776 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3777 | if (r < 0) |
3778 | return r; | |
3779 | ||
3780 | /* | |
3781 | * DSS code presumes that dss_core hwmod is handled first, | |
3782 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3783 | * DSS hwmod links last to ensure that dss_core is already |
3784 | * registered. Otherwise some change things may happen, for | |
3785 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3786 | * in bootloader DISPC will be reset with outputs enabled | |
3787 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3788 | * long-term fix to this is to ensure hwmods are set up in | |
3789 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3790 | */ |
0a78c5c5 | 3791 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3792 | |
3793 | return r; | |
7359154e | 3794 | } |