Commit | Line | Data |
---|---|---|
a2cfc509 VH |
1 | /* |
2 | * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips | |
3 | * | |
4 | * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is automatically generated from the AM33XX hardware databases. | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <plat/omap_hwmod.h> | |
18 | #include <plat/cpu.h> | |
11964f53 | 19 | #include <linux/platform_data/gpio-omap.h> |
aa817b2e | 20 | #include <linux/platform_data/spi-omap2-mcspi.h> |
a2cfc509 VH |
21 | #include <plat/i2c.h> |
22 | ||
23 | #include "omap_hwmod_common_data.h" | |
24 | ||
25 | #include "control.h" | |
26 | #include "cm33xx.h" | |
27 | #include "prm33xx.h" | |
28 | #include "prm-regbits-33xx.h" | |
68f39e74 | 29 | #include "mmc.h" |
a2cfc509 | 30 | |
a2cfc509 VH |
31 | /* |
32 | * IP blocks | |
33 | */ | |
34 | ||
35 | /* | |
36 | * 'emif_fw' class | |
37 | * instance(s): emif_fw | |
38 | */ | |
39 | static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { | |
40 | .name = "emif_fw", | |
41 | }; | |
42 | ||
43 | /* emif_fw */ | |
44 | static struct omap_hwmod am33xx_emif_fw_hwmod = { | |
45 | .name = "emif_fw", | |
46 | .class = &am33xx_emif_fw_hwmod_class, | |
47 | .clkdm_name = "l4fw_clkdm", | |
48 | .main_clk = "l4fw_gclk", | |
49 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
50 | .prcm = { | |
51 | .omap4 = { | |
52 | .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, | |
53 | .modulemode = MODULEMODE_SWCTRL, | |
54 | }, | |
55 | }, | |
56 | }; | |
57 | ||
58 | /* | |
59 | * 'emif' class | |
60 | * instance(s): emif | |
61 | */ | |
62 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { | |
63 | .rev_offs = 0x0000, | |
64 | }; | |
65 | ||
66 | static struct omap_hwmod_class am33xx_emif_hwmod_class = { | |
67 | .name = "emif", | |
68 | .sysc = &am33xx_emif_sysc, | |
69 | }; | |
70 | ||
71 | static struct omap_hwmod_irq_info am33xx_emif_irqs[] = { | |
72 | { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, }, | |
73 | { .irq = -1 }, | |
74 | }; | |
75 | ||
76 | /* emif */ | |
77 | static struct omap_hwmod am33xx_emif_hwmod = { | |
78 | .name = "emif", | |
79 | .class = &am33xx_emif_hwmod_class, | |
80 | .clkdm_name = "l3_clkdm", | |
81 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
82 | .mpu_irqs = am33xx_emif_irqs, | |
83 | .main_clk = "dpll_ddr_m2_div2_ck", | |
84 | .prcm = { | |
85 | .omap4 = { | |
86 | .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, | |
87 | .modulemode = MODULEMODE_SWCTRL, | |
88 | }, | |
89 | }, | |
90 | }; | |
91 | ||
92 | /* | |
93 | * 'l3' class | |
94 | * instance(s): l3_main, l3_s, l3_instr | |
95 | */ | |
96 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | |
97 | .name = "l3", | |
98 | }; | |
99 | ||
100 | /* l3_main (l3_fast) */ | |
101 | static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = { | |
102 | { .name = "l3debug", .irq = 9 + OMAP_INTC_START, }, | |
103 | { .name = "l3appint", .irq = 10 + OMAP_INTC_START, }, | |
104 | { .irq = -1 }, | |
105 | }; | |
106 | ||
107 | static struct omap_hwmod am33xx_l3_main_hwmod = { | |
108 | .name = "l3_main", | |
109 | .class = &am33xx_l3_hwmod_class, | |
110 | .clkdm_name = "l3_clkdm", | |
111 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
112 | .mpu_irqs = am33xx_l3_main_irqs, | |
113 | .main_clk = "l3_gclk", | |
114 | .prcm = { | |
115 | .omap4 = { | |
116 | .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, | |
117 | .modulemode = MODULEMODE_SWCTRL, | |
118 | }, | |
119 | }, | |
120 | }; | |
121 | ||
122 | /* l3_s */ | |
123 | static struct omap_hwmod am33xx_l3_s_hwmod = { | |
124 | .name = "l3_s", | |
125 | .class = &am33xx_l3_hwmod_class, | |
126 | .clkdm_name = "l3s_clkdm", | |
127 | }; | |
128 | ||
129 | /* l3_instr */ | |
130 | static struct omap_hwmod am33xx_l3_instr_hwmod = { | |
131 | .name = "l3_instr", | |
132 | .class = &am33xx_l3_hwmod_class, | |
133 | .clkdm_name = "l3_clkdm", | |
134 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
135 | .main_clk = "l3_gclk", | |
136 | .prcm = { | |
137 | .omap4 = { | |
138 | .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, | |
139 | .modulemode = MODULEMODE_SWCTRL, | |
140 | }, | |
141 | }, | |
142 | }; | |
143 | ||
144 | /* | |
145 | * 'l4' class | |
146 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | |
147 | */ | |
148 | static struct omap_hwmod_class am33xx_l4_hwmod_class = { | |
149 | .name = "l4", | |
150 | }; | |
151 | ||
152 | /* l4_ls */ | |
153 | static struct omap_hwmod am33xx_l4_ls_hwmod = { | |
154 | .name = "l4_ls", | |
155 | .class = &am33xx_l4_hwmod_class, | |
156 | .clkdm_name = "l4ls_clkdm", | |
157 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
158 | .main_clk = "l4ls_gclk", | |
159 | .prcm = { | |
160 | .omap4 = { | |
161 | .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, | |
162 | .modulemode = MODULEMODE_SWCTRL, | |
163 | }, | |
164 | }, | |
165 | }; | |
166 | ||
167 | /* l4_hs */ | |
168 | static struct omap_hwmod am33xx_l4_hs_hwmod = { | |
169 | .name = "l4_hs", | |
170 | .class = &am33xx_l4_hwmod_class, | |
171 | .clkdm_name = "l4hs_clkdm", | |
172 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
173 | .main_clk = "l4hs_gclk", | |
174 | .prcm = { | |
175 | .omap4 = { | |
176 | .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, | |
177 | .modulemode = MODULEMODE_SWCTRL, | |
178 | }, | |
179 | }, | |
180 | }; | |
181 | ||
182 | ||
183 | /* l4_wkup */ | |
184 | static struct omap_hwmod am33xx_l4_wkup_hwmod = { | |
185 | .name = "l4_wkup", | |
186 | .class = &am33xx_l4_hwmod_class, | |
187 | .clkdm_name = "l4_wkup_clkdm", | |
188 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
189 | .prcm = { | |
190 | .omap4 = { | |
191 | .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
192 | .modulemode = MODULEMODE_SWCTRL, | |
193 | }, | |
194 | }, | |
195 | }; | |
196 | ||
197 | /* l4_fw */ | |
198 | static struct omap_hwmod am33xx_l4_fw_hwmod = { | |
199 | .name = "l4_fw", | |
200 | .class = &am33xx_l4_hwmod_class, | |
201 | .clkdm_name = "l4fw_clkdm", | |
202 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
203 | .prcm = { | |
204 | .omap4 = { | |
205 | .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, | |
206 | .modulemode = MODULEMODE_SWCTRL, | |
207 | }, | |
208 | }, | |
209 | }; | |
210 | ||
211 | /* | |
212 | * 'mpu' class | |
213 | */ | |
214 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | |
215 | .name = "mpu", | |
216 | }; | |
217 | ||
218 | /* mpu */ | |
219 | static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = { | |
220 | { .name = "emuint", .irq = 0 + OMAP_INTC_START, }, | |
221 | { .name = "commtx", .irq = 1 + OMAP_INTC_START, }, | |
222 | { .name = "commrx", .irq = 2 + OMAP_INTC_START, }, | |
223 | { .name = "bench", .irq = 3 + OMAP_INTC_START, }, | |
224 | { .irq = -1 }, | |
225 | }; | |
226 | ||
227 | static struct omap_hwmod am33xx_mpu_hwmod = { | |
228 | .name = "mpu", | |
229 | .class = &am33xx_mpu_hwmod_class, | |
230 | .clkdm_name = "mpu_clkdm", | |
231 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
232 | .mpu_irqs = am33xx_mpu_irqs, | |
233 | .main_clk = "dpll_mpu_m2_ck", | |
234 | .prcm = { | |
235 | .omap4 = { | |
236 | .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
237 | .modulemode = MODULEMODE_SWCTRL, | |
238 | }, | |
239 | }, | |
240 | }; | |
241 | ||
242 | /* | |
243 | * 'wakeup m3' class | |
244 | * Wakeup controller sub-system under wakeup domain | |
245 | */ | |
246 | static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | |
247 | .name = "wkup_m3", | |
248 | }; | |
249 | ||
250 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |
251 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | |
252 | }; | |
253 | ||
254 | static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = { | |
255 | { .name = "txev", .irq = 78 + OMAP_INTC_START, }, | |
256 | { .irq = -1 }, | |
257 | }; | |
258 | ||
259 | /* wkup_m3 */ | |
260 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { | |
261 | .name = "wkup_m3", | |
262 | .class = &am33xx_wkup_m3_hwmod_class, | |
263 | .clkdm_name = "l4_wkup_aon_clkdm", | |
264 | .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ | |
265 | .mpu_irqs = am33xx_wkup_m3_irqs, | |
266 | .main_clk = "dpll_core_m4_div2_ck", | |
267 | .prcm = { | |
268 | .omap4 = { | |
269 | .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | |
270 | .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, | |
271 | .modulemode = MODULEMODE_SWCTRL, | |
272 | }, | |
273 | }, | |
274 | .rst_lines = am33xx_wkup_m3_resets, | |
275 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | |
276 | }; | |
277 | ||
278 | /* | |
279 | * 'pru-icss' class | |
280 | * Programmable Real-Time Unit and Industrial Communication Subsystem | |
281 | */ | |
282 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | |
283 | .name = "pruss", | |
284 | }; | |
285 | ||
286 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | |
287 | { .name = "pruss", .rst_shift = 1 }, | |
288 | }; | |
289 | ||
290 | static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = { | |
291 | { .name = "evtout0", .irq = 20 + OMAP_INTC_START, }, | |
292 | { .name = "evtout1", .irq = 21 + OMAP_INTC_START, }, | |
293 | { .name = "evtout2", .irq = 22 + OMAP_INTC_START, }, | |
294 | { .name = "evtout3", .irq = 23 + OMAP_INTC_START, }, | |
295 | { .name = "evtout4", .irq = 24 + OMAP_INTC_START, }, | |
296 | { .name = "evtout5", .irq = 25 + OMAP_INTC_START, }, | |
297 | { .name = "evtout6", .irq = 26 + OMAP_INTC_START, }, | |
298 | { .name = "evtout7", .irq = 27 + OMAP_INTC_START, }, | |
299 | { .irq = -1 }, | |
300 | }; | |
301 | ||
302 | /* pru-icss */ | |
303 | /* Pseudo hwmod for reset control purpose only */ | |
304 | static struct omap_hwmod am33xx_pruss_hwmod = { | |
305 | .name = "pruss", | |
306 | .class = &am33xx_pruss_hwmod_class, | |
307 | .clkdm_name = "pruss_ocp_clkdm", | |
308 | .mpu_irqs = am33xx_pruss_irqs, | |
309 | .main_clk = "pruss_ocp_gclk", | |
310 | .prcm = { | |
311 | .omap4 = { | |
312 | .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, | |
313 | .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, | |
314 | .modulemode = MODULEMODE_SWCTRL, | |
315 | }, | |
316 | }, | |
317 | .rst_lines = am33xx_pruss_resets, | |
318 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | |
319 | }; | |
320 | ||
321 | /* gfx */ | |
322 | /* Pseudo hwmod for reset control purpose only */ | |
323 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | |
324 | .name = "gfx", | |
325 | }; | |
326 | ||
327 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | |
328 | { .name = "gfx", .rst_shift = 0 }, | |
329 | }; | |
330 | ||
331 | static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { | |
332 | { .name = "gfxint", .irq = 37 + OMAP_INTC_START, }, | |
333 | { .irq = -1 }, | |
334 | }; | |
335 | ||
336 | static struct omap_hwmod am33xx_gfx_hwmod = { | |
337 | .name = "gfx", | |
338 | .class = &am33xx_gfx_hwmod_class, | |
339 | .clkdm_name = "gfx_l3_clkdm", | |
340 | .mpu_irqs = am33xx_gfx_irqs, | |
341 | .main_clk = "gfx_fck_div_ck", | |
342 | .prcm = { | |
343 | .omap4 = { | |
344 | .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, | |
345 | .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, | |
346 | .modulemode = MODULEMODE_SWCTRL, | |
347 | }, | |
348 | }, | |
349 | .rst_lines = am33xx_gfx_resets, | |
350 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | |
351 | }; | |
352 | ||
353 | /* | |
354 | * 'prcm' class | |
355 | * power and reset manager (whole prcm infrastructure) | |
356 | */ | |
357 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | |
358 | .name = "prcm", | |
359 | }; | |
360 | ||
361 | /* prcm */ | |
362 | static struct omap_hwmod am33xx_prcm_hwmod = { | |
363 | .name = "prcm", | |
364 | .class = &am33xx_prcm_hwmod_class, | |
365 | .clkdm_name = "l4_wkup_clkdm", | |
366 | }; | |
367 | ||
368 | /* | |
369 | * 'adc/tsc' class | |
370 | * TouchScreen Controller (Anolog-To-Digital Converter) | |
371 | */ | |
372 | static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { | |
373 | .rev_offs = 0x00, | |
374 | .sysc_offs = 0x10, | |
375 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
376 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
377 | SIDLE_SMART_WKUP), | |
378 | .sysc_fields = &omap_hwmod_sysc_type2, | |
379 | }; | |
380 | ||
381 | static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { | |
382 | .name = "adc_tsc", | |
383 | .sysc = &am33xx_adc_tsc_sysc, | |
384 | }; | |
385 | ||
386 | static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { | |
387 | { .irq = 16 + OMAP_INTC_START, }, | |
388 | { .irq = -1 }, | |
389 | }; | |
390 | ||
391 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { | |
392 | .name = "adc_tsc", | |
393 | .class = &am33xx_adc_tsc_hwmod_class, | |
394 | .clkdm_name = "l4_wkup_clkdm", | |
395 | .mpu_irqs = am33xx_adc_tsc_irqs, | |
396 | .main_clk = "adc_tsc_fck", | |
397 | .prcm = { | |
398 | .omap4 = { | |
399 | .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, | |
400 | .modulemode = MODULEMODE_SWCTRL, | |
401 | }, | |
402 | }, | |
403 | }; | |
404 | ||
405 | /* | |
406 | * Modules omap_hwmod structures | |
407 | * | |
408 | * The following IPs are excluded for the moment because: | |
409 | * - They do not need an explicit SW control using omap_hwmod API. | |
410 | * - They still need to be validated with the driver | |
411 | * properly adapted to omap_hwmod / omap_device | |
412 | * | |
413 | * - cEFUSE (doesn't fall under any ocp_if) | |
414 | * - clkdiv32k | |
415 | * - debugss | |
416 | * - ocmc ram | |
417 | * - ocp watch point | |
418 | * - aes0 | |
419 | * - sha0 | |
420 | */ | |
421 | #if 0 | |
422 | /* | |
423 | * 'cefuse' class | |
424 | */ | |
425 | static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { | |
426 | .name = "cefuse", | |
427 | }; | |
428 | ||
429 | static struct omap_hwmod am33xx_cefuse_hwmod = { | |
430 | .name = "cefuse", | |
431 | .class = &am33xx_cefuse_hwmod_class, | |
432 | .clkdm_name = "l4_cefuse_clkdm", | |
433 | .main_clk = "cefuse_fck", | |
434 | .prcm = { | |
435 | .omap4 = { | |
436 | .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, | |
437 | .modulemode = MODULEMODE_SWCTRL, | |
438 | }, | |
439 | }, | |
440 | }; | |
441 | ||
442 | /* | |
443 | * 'clkdiv32k' class | |
444 | */ | |
445 | static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { | |
446 | .name = "clkdiv32k", | |
447 | }; | |
448 | ||
449 | static struct omap_hwmod am33xx_clkdiv32k_hwmod = { | |
450 | .name = "clkdiv32k", | |
451 | .class = &am33xx_clkdiv32k_hwmod_class, | |
452 | .clkdm_name = "clk_24mhz_clkdm", | |
453 | .main_clk = "clkdiv32k_ick", | |
454 | .prcm = { | |
455 | .omap4 = { | |
456 | .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, | |
457 | .modulemode = MODULEMODE_SWCTRL, | |
458 | }, | |
459 | }, | |
460 | }; | |
461 | ||
462 | /* | |
463 | * 'debugss' class | |
464 | * debug sub system | |
465 | */ | |
466 | static struct omap_hwmod_class am33xx_debugss_hwmod_class = { | |
467 | .name = "debugss", | |
468 | }; | |
469 | ||
470 | static struct omap_hwmod am33xx_debugss_hwmod = { | |
471 | .name = "debugss", | |
472 | .class = &am33xx_debugss_hwmod_class, | |
473 | .clkdm_name = "l3_aon_clkdm", | |
474 | .main_clk = "debugss_ick", | |
475 | .prcm = { | |
476 | .omap4 = { | |
477 | .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, | |
478 | .modulemode = MODULEMODE_SWCTRL, | |
479 | }, | |
480 | }, | |
481 | }; | |
482 | ||
483 | /* ocmcram */ | |
484 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | |
485 | .name = "ocmcram", | |
486 | }; | |
487 | ||
488 | static struct omap_hwmod am33xx_ocmcram_hwmod = { | |
489 | .name = "ocmcram", | |
490 | .class = &am33xx_ocmcram_hwmod_class, | |
491 | .clkdm_name = "l3_clkdm", | |
492 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
493 | .main_clk = "l3_gclk", | |
494 | .prcm = { | |
495 | .omap4 = { | |
496 | .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, | |
497 | .modulemode = MODULEMODE_SWCTRL, | |
498 | }, | |
499 | }, | |
500 | }; | |
501 | ||
502 | /* ocpwp */ | |
503 | static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { | |
504 | .name = "ocpwp", | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod am33xx_ocpwp_hwmod = { | |
508 | .name = "ocpwp", | |
509 | .class = &am33xx_ocpwp_hwmod_class, | |
510 | .clkdm_name = "l4ls_clkdm", | |
511 | .main_clk = "l4ls_gclk", | |
512 | .prcm = { | |
513 | .omap4 = { | |
514 | .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, | |
515 | .modulemode = MODULEMODE_SWCTRL, | |
516 | }, | |
517 | }, | |
518 | }; | |
519 | ||
520 | /* | |
521 | * 'aes' class | |
522 | */ | |
523 | static struct omap_hwmod_class am33xx_aes_hwmod_class = { | |
524 | .name = "aes", | |
525 | }; | |
526 | ||
527 | static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { | |
528 | { .irq = 102 + OMAP_INTC_START, }, | |
529 | { .irq = -1 }, | |
530 | }; | |
531 | ||
532 | static struct omap_hwmod am33xx_aes0_hwmod = { | |
533 | .name = "aes0", | |
534 | .class = &am33xx_aes_hwmod_class, | |
535 | .clkdm_name = "l3_clkdm", | |
536 | .mpu_irqs = am33xx_aes0_irqs, | |
537 | .main_clk = "l3_gclk", | |
538 | .prcm = { | |
539 | .omap4 = { | |
540 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, | |
541 | .modulemode = MODULEMODE_SWCTRL, | |
542 | }, | |
543 | }, | |
544 | }; | |
545 | ||
546 | /* sha0 */ | |
547 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | |
548 | .name = "sha0", | |
549 | }; | |
550 | ||
551 | static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { | |
552 | { .irq = 108 + OMAP_INTC_START, }, | |
553 | { .irq = -1 }, | |
554 | }; | |
555 | ||
556 | static struct omap_hwmod am33xx_sha0_hwmod = { | |
557 | .name = "sha0", | |
558 | .class = &am33xx_sha0_hwmod_class, | |
559 | .clkdm_name = "l3_clkdm", | |
560 | .mpu_irqs = am33xx_sha0_irqs, | |
561 | .main_clk = "l3_gclk", | |
562 | .prcm = { | |
563 | .omap4 = { | |
564 | .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, | |
565 | .modulemode = MODULEMODE_SWCTRL, | |
566 | }, | |
567 | }, | |
568 | }; | |
569 | ||
570 | #endif | |
571 | ||
572 | /* 'smartreflex' class */ | |
573 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | |
574 | .name = "smartreflex", | |
575 | }; | |
576 | ||
577 | /* smartreflex0 */ | |
578 | static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { | |
579 | { .irq = 120 + OMAP_INTC_START, }, | |
580 | { .irq = -1 }, | |
581 | }; | |
582 | ||
583 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { | |
584 | .name = "smartreflex0", | |
585 | .class = &am33xx_smartreflex_hwmod_class, | |
586 | .clkdm_name = "l4_wkup_clkdm", | |
587 | .mpu_irqs = am33xx_smartreflex0_irqs, | |
588 | .main_clk = "smartreflex0_fck", | |
589 | .prcm = { | |
590 | .omap4 = { | |
591 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, | |
592 | .modulemode = MODULEMODE_SWCTRL, | |
593 | }, | |
594 | }, | |
595 | }; | |
596 | ||
597 | /* smartreflex1 */ | |
598 | static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { | |
599 | { .irq = 121 + OMAP_INTC_START, }, | |
600 | { .irq = -1 }, | |
601 | }; | |
602 | ||
603 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { | |
604 | .name = "smartreflex1", | |
605 | .class = &am33xx_smartreflex_hwmod_class, | |
606 | .clkdm_name = "l4_wkup_clkdm", | |
607 | .mpu_irqs = am33xx_smartreflex1_irqs, | |
608 | .main_clk = "smartreflex1_fck", | |
609 | .prcm = { | |
610 | .omap4 = { | |
611 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, | |
612 | .modulemode = MODULEMODE_SWCTRL, | |
613 | }, | |
614 | }, | |
615 | }; | |
616 | ||
617 | /* | |
618 | * 'control' module class | |
619 | */ | |
620 | static struct omap_hwmod_class am33xx_control_hwmod_class = { | |
621 | .name = "control", | |
622 | }; | |
623 | ||
624 | static struct omap_hwmod_irq_info am33xx_control_irqs[] = { | |
625 | { .irq = 8 + OMAP_INTC_START, }, | |
626 | { .irq = -1 }, | |
627 | }; | |
628 | ||
629 | static struct omap_hwmod am33xx_control_hwmod = { | |
630 | .name = "control", | |
631 | .class = &am33xx_control_hwmod_class, | |
632 | .clkdm_name = "l4_wkup_clkdm", | |
633 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
634 | .mpu_irqs = am33xx_control_irqs, | |
635 | .main_clk = "dpll_core_m4_div2_ck", | |
636 | .prcm = { | |
637 | .omap4 = { | |
638 | .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | |
639 | .modulemode = MODULEMODE_SWCTRL, | |
640 | }, | |
641 | }, | |
642 | }; | |
643 | ||
644 | /* | |
645 | * 'cpgmac' class | |
646 | * cpsw/cpgmac sub system | |
647 | */ | |
648 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | |
649 | .rev_offs = 0x0, | |
650 | .sysc_offs = 0x8, | |
651 | .syss_offs = 0x4, | |
652 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
653 | SYSS_HAS_RESET_STATUS), | |
654 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
655 | MSTANDBY_NO), | |
656 | .sysc_fields = &omap_hwmod_sysc_type3, | |
657 | }; | |
658 | ||
659 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | |
660 | .name = "cpgmac0", | |
661 | .sysc = &am33xx_cpgmac_sysc, | |
662 | }; | |
663 | ||
664 | static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = { | |
665 | { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, }, | |
666 | { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, }, | |
667 | { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, }, | |
668 | { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, }, | |
669 | { .irq = -1 }, | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { | |
673 | .name = "cpgmac0", | |
674 | .class = &am33xx_cpgmac0_hwmod_class, | |
675 | .clkdm_name = "cpsw_125mhz_clkdm", | |
676 | .mpu_irqs = am33xx_cpgmac0_irqs, | |
677 | .main_clk = "cpsw_125mhz_gclk", | |
678 | .prcm = { | |
679 | .omap4 = { | |
680 | .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, | |
681 | .modulemode = MODULEMODE_SWCTRL, | |
682 | }, | |
683 | }, | |
684 | }; | |
685 | ||
686 | /* | |
687 | * dcan class | |
688 | */ | |
689 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | |
690 | .name = "d_can", | |
691 | }; | |
692 | ||
693 | /* dcan0 */ | |
694 | static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { | |
695 | { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, }, | |
696 | { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, }, | |
697 | { .irq = -1 }, | |
698 | }; | |
699 | ||
700 | static struct omap_hwmod am33xx_dcan0_hwmod = { | |
701 | .name = "d_can0", | |
702 | .class = &am33xx_dcan_hwmod_class, | |
703 | .clkdm_name = "l4ls_clkdm", | |
704 | .mpu_irqs = am33xx_dcan0_irqs, | |
705 | .main_clk = "dcan0_fck", | |
706 | .prcm = { | |
707 | .omap4 = { | |
708 | .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, | |
709 | .modulemode = MODULEMODE_SWCTRL, | |
710 | }, | |
711 | }, | |
712 | }; | |
713 | ||
714 | /* dcan1 */ | |
715 | static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { | |
716 | { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, }, | |
717 | { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, }, | |
718 | { .irq = -1 }, | |
719 | }; | |
720 | static struct omap_hwmod am33xx_dcan1_hwmod = { | |
721 | .name = "d_can1", | |
722 | .class = &am33xx_dcan_hwmod_class, | |
723 | .clkdm_name = "l4ls_clkdm", | |
724 | .mpu_irqs = am33xx_dcan1_irqs, | |
725 | .main_clk = "dcan1_fck", | |
726 | .prcm = { | |
727 | .omap4 = { | |
728 | .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, | |
729 | .modulemode = MODULEMODE_SWCTRL, | |
730 | }, | |
731 | }, | |
732 | }; | |
733 | ||
734 | /* elm */ | |
735 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | |
736 | .rev_offs = 0x0000, | |
737 | .sysc_offs = 0x0010, | |
738 | .syss_offs = 0x0014, | |
739 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
740 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
741 | SYSS_HAS_RESET_STATUS), | |
742 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
743 | .sysc_fields = &omap_hwmod_sysc_type1, | |
744 | }; | |
745 | ||
746 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | |
747 | .name = "elm", | |
748 | .sysc = &am33xx_elm_sysc, | |
749 | }; | |
750 | ||
751 | static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { | |
752 | { .irq = 4 + OMAP_INTC_START, }, | |
753 | { .irq = -1 }, | |
754 | }; | |
755 | ||
756 | static struct omap_hwmod am33xx_elm_hwmod = { | |
757 | .name = "elm", | |
758 | .class = &am33xx_elm_hwmod_class, | |
759 | .clkdm_name = "l4ls_clkdm", | |
760 | .mpu_irqs = am33xx_elm_irqs, | |
761 | .main_clk = "l4ls_gclk", | |
762 | .prcm = { | |
763 | .omap4 = { | |
764 | .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, | |
765 | .modulemode = MODULEMODE_SWCTRL, | |
766 | }, | |
767 | }, | |
768 | }; | |
769 | ||
770 | /* | |
771 | * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2 | |
772 | */ | |
773 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { | |
774 | .rev_offs = 0x0, | |
775 | .sysc_offs = 0x4, | |
776 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
777 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
778 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
779 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
780 | .sysc_fields = &omap_hwmod_sysc_type2, | |
781 | }; | |
782 | ||
783 | static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | |
784 | .name = "epwmss", | |
785 | .sysc = &am33xx_epwmss_sysc, | |
786 | }; | |
787 | ||
788 | /* ehrpwm0 */ | |
789 | static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { | |
790 | { .name = "int", .irq = 86 + OMAP_INTC_START, }, | |
791 | { .name = "tzint", .irq = 58 + OMAP_INTC_START, }, | |
792 | { .irq = -1 }, | |
793 | }; | |
794 | ||
795 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { | |
796 | .name = "ehrpwm0", | |
797 | .class = &am33xx_epwmss_hwmod_class, | |
798 | .clkdm_name = "l4ls_clkdm", | |
799 | .mpu_irqs = am33xx_ehrpwm0_irqs, | |
800 | .main_clk = "l4ls_gclk", | |
801 | .prcm = { | |
802 | .omap4 = { | |
803 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, | |
804 | .modulemode = MODULEMODE_SWCTRL, | |
805 | }, | |
806 | }, | |
807 | }; | |
808 | ||
809 | /* ehrpwm1 */ | |
810 | static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { | |
811 | { .name = "int", .irq = 87 + OMAP_INTC_START, }, | |
812 | { .name = "tzint", .irq = 59 + OMAP_INTC_START, }, | |
813 | { .irq = -1 }, | |
814 | }; | |
815 | ||
816 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { | |
817 | .name = "ehrpwm1", | |
818 | .class = &am33xx_epwmss_hwmod_class, | |
819 | .clkdm_name = "l4ls_clkdm", | |
820 | .mpu_irqs = am33xx_ehrpwm1_irqs, | |
821 | .main_clk = "l4ls_gclk", | |
822 | .prcm = { | |
823 | .omap4 = { | |
824 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | |
825 | .modulemode = MODULEMODE_SWCTRL, | |
826 | }, | |
827 | }, | |
828 | }; | |
829 | ||
830 | /* ehrpwm2 */ | |
831 | static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { | |
832 | { .name = "int", .irq = 39 + OMAP_INTC_START, }, | |
833 | { .name = "tzint", .irq = 60 + OMAP_INTC_START, }, | |
834 | { .irq = -1 }, | |
835 | }; | |
836 | ||
837 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { | |
838 | .name = "ehrpwm2", | |
839 | .class = &am33xx_epwmss_hwmod_class, | |
840 | .clkdm_name = "l4ls_clkdm", | |
841 | .mpu_irqs = am33xx_ehrpwm2_irqs, | |
842 | .main_clk = "l4ls_gclk", | |
843 | .prcm = { | |
844 | .omap4 = { | |
845 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, | |
846 | .modulemode = MODULEMODE_SWCTRL, | |
847 | }, | |
848 | }, | |
849 | }; | |
850 | ||
851 | /* ecap0 */ | |
852 | static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { | |
853 | { .irq = 31 + OMAP_INTC_START, }, | |
854 | { .irq = -1 }, | |
855 | }; | |
856 | ||
857 | static struct omap_hwmod am33xx_ecap0_hwmod = { | |
858 | .name = "ecap0", | |
859 | .class = &am33xx_epwmss_hwmod_class, | |
860 | .clkdm_name = "l4ls_clkdm", | |
861 | .mpu_irqs = am33xx_ecap0_irqs, | |
862 | .main_clk = "l4ls_gclk", | |
863 | .prcm = { | |
864 | .omap4 = { | |
865 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, | |
866 | .modulemode = MODULEMODE_SWCTRL, | |
867 | }, | |
868 | }, | |
869 | }; | |
870 | ||
871 | /* ecap1 */ | |
872 | static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { | |
873 | { .irq = 47 + OMAP_INTC_START, }, | |
874 | { .irq = -1 }, | |
875 | }; | |
876 | ||
877 | static struct omap_hwmod am33xx_ecap1_hwmod = { | |
878 | .name = "ecap1", | |
879 | .class = &am33xx_epwmss_hwmod_class, | |
880 | .clkdm_name = "l4ls_clkdm", | |
881 | .mpu_irqs = am33xx_ecap1_irqs, | |
882 | .main_clk = "l4ls_gclk", | |
883 | .prcm = { | |
884 | .omap4 = { | |
885 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | |
886 | .modulemode = MODULEMODE_SWCTRL, | |
887 | }, | |
888 | }, | |
889 | }; | |
890 | ||
891 | /* ecap2 */ | |
892 | static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = { | |
893 | { .irq = 61 + OMAP_INTC_START, }, | |
894 | { .irq = -1 }, | |
895 | }; | |
896 | ||
897 | static struct omap_hwmod am33xx_ecap2_hwmod = { | |
898 | .name = "ecap2", | |
899 | .mpu_irqs = am33xx_ecap2_irqs, | |
900 | .class = &am33xx_epwmss_hwmod_class, | |
901 | .clkdm_name = "l4ls_clkdm", | |
902 | .main_clk = "l4ls_gclk", | |
903 | .prcm = { | |
904 | .omap4 = { | |
905 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, | |
906 | .modulemode = MODULEMODE_SWCTRL, | |
907 | }, | |
908 | }, | |
909 | }; | |
910 | ||
911 | /* | |
912 | * 'gpio' class: for gpio 0,1,2,3 | |
913 | */ | |
914 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | |
915 | .rev_offs = 0x0000, | |
916 | .sysc_offs = 0x0010, | |
917 | .syss_offs = 0x0114, | |
918 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
919 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
920 | SYSS_HAS_RESET_STATUS), | |
921 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
922 | SIDLE_SMART_WKUP), | |
923 | .sysc_fields = &omap_hwmod_sysc_type1, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod_class am33xx_gpio_hwmod_class = { | |
927 | .name = "gpio", | |
928 | .sysc = &am33xx_gpio_sysc, | |
929 | .rev = 2, | |
930 | }; | |
931 | ||
932 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
933 | .bank_width = 32, | |
934 | .dbck_flag = true, | |
935 | }; | |
936 | ||
937 | /* gpio0 */ | |
938 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |
939 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | |
940 | }; | |
941 | ||
942 | static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { | |
943 | { .irq = 96 + OMAP_INTC_START, }, | |
944 | { .irq = -1 }, | |
945 | }; | |
946 | ||
947 | static struct omap_hwmod am33xx_gpio0_hwmod = { | |
948 | .name = "gpio1", | |
949 | .class = &am33xx_gpio_hwmod_class, | |
950 | .clkdm_name = "l4_wkup_clkdm", | |
951 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
952 | .mpu_irqs = am33xx_gpio0_irqs, | |
953 | .main_clk = "dpll_core_m4_div2_ck", | |
954 | .prcm = { | |
955 | .omap4 = { | |
956 | .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | |
957 | .modulemode = MODULEMODE_SWCTRL, | |
958 | }, | |
959 | }, | |
960 | .opt_clks = gpio0_opt_clks, | |
961 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | |
962 | .dev_attr = &gpio_dev_attr, | |
963 | }; | |
964 | ||
965 | /* gpio1 */ | |
966 | static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { | |
967 | { .irq = 98 + OMAP_INTC_START, }, | |
968 | { .irq = -1 }, | |
969 | }; | |
970 | ||
971 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
972 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
973 | }; | |
974 | ||
975 | static struct omap_hwmod am33xx_gpio1_hwmod = { | |
976 | .name = "gpio2", | |
977 | .class = &am33xx_gpio_hwmod_class, | |
978 | .clkdm_name = "l4ls_clkdm", | |
979 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
980 | .mpu_irqs = am33xx_gpio1_irqs, | |
981 | .main_clk = "l4ls_gclk", | |
982 | .prcm = { | |
983 | .omap4 = { | |
984 | .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, | |
985 | .modulemode = MODULEMODE_SWCTRL, | |
986 | }, | |
987 | }, | |
988 | .opt_clks = gpio1_opt_clks, | |
989 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
990 | .dev_attr = &gpio_dev_attr, | |
991 | }; | |
992 | ||
993 | /* gpio2 */ | |
994 | static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { | |
995 | { .irq = 32 + OMAP_INTC_START, }, | |
996 | { .irq = -1 }, | |
997 | }; | |
998 | ||
999 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
1000 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
1001 | }; | |
1002 | ||
1003 | static struct omap_hwmod am33xx_gpio2_hwmod = { | |
1004 | .name = "gpio3", | |
1005 | .class = &am33xx_gpio_hwmod_class, | |
1006 | .clkdm_name = "l4ls_clkdm", | |
1007 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1008 | .mpu_irqs = am33xx_gpio2_irqs, | |
1009 | .main_clk = "l4ls_gclk", | |
1010 | .prcm = { | |
1011 | .omap4 = { | |
1012 | .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, | |
1013 | .modulemode = MODULEMODE_SWCTRL, | |
1014 | }, | |
1015 | }, | |
1016 | .opt_clks = gpio2_opt_clks, | |
1017 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1018 | .dev_attr = &gpio_dev_attr, | |
1019 | }; | |
1020 | ||
1021 | /* gpio3 */ | |
1022 | static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { | |
1023 | { .irq = 62 + OMAP_INTC_START, }, | |
1024 | { .irq = -1 }, | |
1025 | }; | |
1026 | ||
1027 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
1028 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
1029 | }; | |
1030 | ||
1031 | static struct omap_hwmod am33xx_gpio3_hwmod = { | |
1032 | .name = "gpio4", | |
1033 | .class = &am33xx_gpio_hwmod_class, | |
1034 | .clkdm_name = "l4ls_clkdm", | |
1035 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1036 | .mpu_irqs = am33xx_gpio3_irqs, | |
1037 | .main_clk = "l4ls_gclk", | |
1038 | .prcm = { | |
1039 | .omap4 = { | |
1040 | .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, | |
1041 | .modulemode = MODULEMODE_SWCTRL, | |
1042 | }, | |
1043 | }, | |
1044 | .opt_clks = gpio3_opt_clks, | |
1045 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1046 | .dev_attr = &gpio_dev_attr, | |
1047 | }; | |
1048 | ||
1049 | /* gpmc */ | |
1050 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | |
1051 | .rev_offs = 0x0, | |
1052 | .sysc_offs = 0x10, | |
1053 | .syss_offs = 0x14, | |
1054 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1055 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1056 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1057 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1058 | }; | |
1059 | ||
1060 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | |
1061 | .name = "gpmc", | |
1062 | .sysc = &gpmc_sysc, | |
1063 | }; | |
1064 | ||
1065 | static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = { | |
1066 | { .irq = 100 + OMAP_INTC_START, }, | |
1067 | { .irq = -1 }, | |
1068 | }; | |
1069 | ||
1070 | static struct omap_hwmod am33xx_gpmc_hwmod = { | |
1071 | .name = "gpmc", | |
1072 | .class = &am33xx_gpmc_hwmod_class, | |
1073 | .clkdm_name = "l3s_clkdm", | |
1074 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1075 | .mpu_irqs = am33xx_gpmc_irqs, | |
1076 | .main_clk = "l3s_gclk", | |
1077 | .prcm = { | |
1078 | .omap4 = { | |
1079 | .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, | |
1080 | .modulemode = MODULEMODE_SWCTRL, | |
1081 | }, | |
1082 | }, | |
1083 | }; | |
1084 | ||
1085 | /* 'i2c' class */ | |
1086 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | |
1087 | .sysc_offs = 0x0010, | |
1088 | .syss_offs = 0x0090, | |
1089 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1090 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1091 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1092 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1093 | SIDLE_SMART_WKUP), | |
1094 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1095 | }; | |
1096 | ||
1097 | static struct omap_hwmod_class i2c_class = { | |
1098 | .name = "i2c", | |
1099 | .sysc = &am33xx_i2c_sysc, | |
1100 | .rev = OMAP_I2C_IP_VERSION_2, | |
1101 | .reset = &omap_i2c_reset, | |
1102 | }; | |
1103 | ||
1104 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
1105 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | | |
1106 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, | |
1107 | }; | |
1108 | ||
1109 | /* i2c1 */ | |
1110 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | |
1111 | { .irq = 70 + OMAP_INTC_START, }, | |
1112 | { .irq = -1 }, | |
1113 | }; | |
1114 | ||
1115 | static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { | |
1116 | { .name = "tx", .dma_req = 0, }, | |
1117 | { .name = "rx", .dma_req = 0, }, | |
1118 | { .dma_req = -1 } | |
1119 | }; | |
1120 | ||
1121 | static struct omap_hwmod am33xx_i2c1_hwmod = { | |
1122 | .name = "i2c1", | |
1123 | .class = &i2c_class, | |
1124 | .clkdm_name = "l4_wkup_clkdm", | |
1125 | .mpu_irqs = i2c1_mpu_irqs, | |
1126 | .sdma_reqs = i2c1_edma_reqs, | |
1127 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1128 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
1129 | .prcm = { | |
1130 | .omap4 = { | |
1131 | .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, | |
1132 | .modulemode = MODULEMODE_SWCTRL, | |
1133 | }, | |
1134 | }, | |
1135 | .dev_attr = &i2c_dev_attr, | |
1136 | }; | |
1137 | ||
1138 | /* i2c1 */ | |
1139 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | |
1140 | { .irq = 71 + OMAP_INTC_START, }, | |
1141 | { .irq = -1 }, | |
1142 | }; | |
1143 | ||
1144 | static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { | |
1145 | { .name = "tx", .dma_req = 0, }, | |
1146 | { .name = "rx", .dma_req = 0, }, | |
1147 | { .dma_req = -1 } | |
1148 | }; | |
1149 | ||
1150 | static struct omap_hwmod am33xx_i2c2_hwmod = { | |
1151 | .name = "i2c2", | |
1152 | .class = &i2c_class, | |
1153 | .clkdm_name = "l4ls_clkdm", | |
1154 | .mpu_irqs = i2c2_mpu_irqs, | |
1155 | .sdma_reqs = i2c2_edma_reqs, | |
1156 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1157 | .main_clk = "dpll_per_m2_div4_ck", | |
1158 | .prcm = { | |
1159 | .omap4 = { | |
1160 | .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, | |
1161 | .modulemode = MODULEMODE_SWCTRL, | |
1162 | }, | |
1163 | }, | |
1164 | .dev_attr = &i2c_dev_attr, | |
1165 | }; | |
1166 | ||
1167 | /* i2c3 */ | |
1168 | static struct omap_hwmod_dma_info i2c3_edma_reqs[] = { | |
1169 | { .name = "tx", .dma_req = 0, }, | |
1170 | { .name = "rx", .dma_req = 0, }, | |
1171 | { .dma_req = -1 } | |
1172 | }; | |
1173 | ||
1174 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | |
1175 | { .irq = 30 + OMAP_INTC_START, }, | |
1176 | { .irq = -1 }, | |
1177 | }; | |
1178 | ||
1179 | static struct omap_hwmod am33xx_i2c3_hwmod = { | |
1180 | .name = "i2c3", | |
1181 | .class = &i2c_class, | |
1182 | .clkdm_name = "l4ls_clkdm", | |
1183 | .mpu_irqs = i2c3_mpu_irqs, | |
1184 | .sdma_reqs = i2c3_edma_reqs, | |
1185 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1186 | .main_clk = "dpll_per_m2_div4_ck", | |
1187 | .prcm = { | |
1188 | .omap4 = { | |
1189 | .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, | |
1190 | .modulemode = MODULEMODE_SWCTRL, | |
1191 | }, | |
1192 | }, | |
1193 | .dev_attr = &i2c_dev_attr, | |
1194 | }; | |
1195 | ||
1196 | ||
1197 | /* lcdc */ | |
1198 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { | |
1199 | .rev_offs = 0x0, | |
1200 | .sysc_offs = 0x54, | |
1201 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
1202 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1203 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1204 | }; | |
1205 | ||
1206 | static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { | |
1207 | .name = "lcdc", | |
1208 | .sysc = &lcdc_sysc, | |
1209 | }; | |
1210 | ||
1211 | static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { | |
1212 | { .irq = 36 + OMAP_INTC_START, }, | |
1213 | { .irq = -1 }, | |
1214 | }; | |
1215 | ||
1216 | static struct omap_hwmod am33xx_lcdc_hwmod = { | |
1217 | .name = "lcdc", | |
1218 | .class = &am33xx_lcdc_hwmod_class, | |
1219 | .clkdm_name = "lcdc_clkdm", | |
1220 | .mpu_irqs = am33xx_lcdc_irqs, | |
1221 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
1222 | .main_clk = "lcd_gclk", | |
1223 | .prcm = { | |
1224 | .omap4 = { | |
1225 | .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, | |
1226 | .modulemode = MODULEMODE_SWCTRL, | |
1227 | }, | |
1228 | }, | |
1229 | }; | |
1230 | ||
1231 | /* | |
1232 | * 'mailbox' class | |
1233 | * mailbox module allowing communication between the on-chip processors using a | |
1234 | * queued mailbox-interrupt mechanism. | |
1235 | */ | |
1236 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | |
1237 | .rev_offs = 0x0000, | |
1238 | .sysc_offs = 0x0010, | |
1239 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1240 | SYSC_HAS_SOFTRESET), | |
1241 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1242 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1243 | }; | |
1244 | ||
1245 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | |
1246 | .name = "mailbox", | |
1247 | .sysc = &am33xx_mailbox_sysc, | |
1248 | }; | |
1249 | ||
1250 | static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = { | |
1251 | { .irq = 77 + OMAP_INTC_START, }, | |
1252 | { .irq = -1 }, | |
1253 | }; | |
1254 | ||
1255 | static struct omap_hwmod am33xx_mailbox_hwmod = { | |
1256 | .name = "mailbox", | |
1257 | .class = &am33xx_mailbox_hwmod_class, | |
1258 | .clkdm_name = "l4ls_clkdm", | |
1259 | .mpu_irqs = am33xx_mailbox_irqs, | |
1260 | .main_clk = "l4ls_gclk", | |
1261 | .prcm = { | |
1262 | .omap4 = { | |
1263 | .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, | |
1264 | .modulemode = MODULEMODE_SWCTRL, | |
1265 | }, | |
1266 | }, | |
1267 | }; | |
1268 | ||
1269 | /* | |
1270 | * 'mcasp' class | |
1271 | */ | |
1272 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | |
1273 | .rev_offs = 0x0, | |
1274 | .sysc_offs = 0x4, | |
1275 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1276 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1277 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1278 | }; | |
1279 | ||
1280 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | |
1281 | .name = "mcasp", | |
1282 | .sysc = &am33xx_mcasp_sysc, | |
1283 | }; | |
1284 | ||
1285 | /* mcasp0 */ | |
1286 | static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { | |
1287 | { .name = "ax", .irq = 80 + OMAP_INTC_START, }, | |
1288 | { .name = "ar", .irq = 81 + OMAP_INTC_START, }, | |
1289 | { .irq = -1 }, | |
1290 | }; | |
1291 | ||
1292 | static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = { | |
1293 | { .name = "tx", .dma_req = 8, }, | |
1294 | { .name = "rx", .dma_req = 9, }, | |
1295 | { .dma_req = -1 } | |
1296 | }; | |
1297 | ||
1298 | static struct omap_hwmod am33xx_mcasp0_hwmod = { | |
1299 | .name = "mcasp0", | |
1300 | .class = &am33xx_mcasp_hwmod_class, | |
1301 | .clkdm_name = "l3s_clkdm", | |
1302 | .mpu_irqs = am33xx_mcasp0_irqs, | |
1303 | .sdma_reqs = am33xx_mcasp0_edma_reqs, | |
1304 | .main_clk = "mcasp0_fck", | |
1305 | .prcm = { | |
1306 | .omap4 = { | |
1307 | .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, | |
1308 | .modulemode = MODULEMODE_SWCTRL, | |
1309 | }, | |
1310 | }, | |
1311 | }; | |
1312 | ||
1313 | /* mcasp1 */ | |
1314 | static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = { | |
1315 | { .name = "ax", .irq = 82 + OMAP_INTC_START, }, | |
1316 | { .name = "ar", .irq = 83 + OMAP_INTC_START, }, | |
1317 | { .irq = -1 }, | |
1318 | }; | |
1319 | ||
1320 | static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = { | |
1321 | { .name = "tx", .dma_req = 10, }, | |
1322 | { .name = "rx", .dma_req = 11, }, | |
1323 | { .dma_req = -1 } | |
1324 | }; | |
1325 | ||
1326 | static struct omap_hwmod am33xx_mcasp1_hwmod = { | |
1327 | .name = "mcasp1", | |
1328 | .class = &am33xx_mcasp_hwmod_class, | |
1329 | .clkdm_name = "l3s_clkdm", | |
1330 | .mpu_irqs = am33xx_mcasp1_irqs, | |
1331 | .sdma_reqs = am33xx_mcasp1_edma_reqs, | |
1332 | .main_clk = "mcasp1_fck", | |
1333 | .prcm = { | |
1334 | .omap4 = { | |
1335 | .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, | |
1336 | .modulemode = MODULEMODE_SWCTRL, | |
1337 | }, | |
1338 | }, | |
1339 | }; | |
1340 | ||
1341 | /* 'mmc' class */ | |
1342 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | |
1343 | .rev_offs = 0x1fc, | |
1344 | .sysc_offs = 0x10, | |
1345 | .syss_offs = 0x14, | |
1346 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1347 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1348 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1349 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1350 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1351 | }; | |
1352 | ||
1353 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | |
1354 | .name = "mmc", | |
1355 | .sysc = &am33xx_mmc_sysc, | |
1356 | }; | |
1357 | ||
1358 | /* mmc0 */ | |
1359 | static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { | |
1360 | { .irq = 64 + OMAP_INTC_START, }, | |
1361 | { .irq = -1 }, | |
1362 | }; | |
1363 | ||
1364 | static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { | |
1365 | { .name = "tx", .dma_req = 24, }, | |
1366 | { .name = "rx", .dma_req = 25, }, | |
1367 | { .dma_req = -1 } | |
1368 | }; | |
1369 | ||
1370 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { | |
1371 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1372 | }; | |
1373 | ||
1374 | static struct omap_hwmod am33xx_mmc0_hwmod = { | |
1375 | .name = "mmc1", | |
1376 | .class = &am33xx_mmc_hwmod_class, | |
1377 | .clkdm_name = "l4ls_clkdm", | |
1378 | .mpu_irqs = am33xx_mmc0_irqs, | |
1379 | .sdma_reqs = am33xx_mmc0_edma_reqs, | |
1380 | .main_clk = "mmc_clk", | |
1381 | .prcm = { | |
1382 | .omap4 = { | |
1383 | .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, | |
1384 | .modulemode = MODULEMODE_SWCTRL, | |
1385 | }, | |
1386 | }, | |
1387 | .dev_attr = &am33xx_mmc0_dev_attr, | |
1388 | }; | |
1389 | ||
1390 | /* mmc1 */ | |
1391 | static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { | |
1392 | { .irq = 28 + OMAP_INTC_START, }, | |
1393 | { .irq = -1 }, | |
1394 | }; | |
1395 | ||
1396 | static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { | |
1397 | { .name = "tx", .dma_req = 2, }, | |
1398 | { .name = "rx", .dma_req = 3, }, | |
1399 | { .dma_req = -1 } | |
1400 | }; | |
1401 | ||
1402 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { | |
1403 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1404 | }; | |
1405 | ||
1406 | static struct omap_hwmod am33xx_mmc1_hwmod = { | |
1407 | .name = "mmc2", | |
1408 | .class = &am33xx_mmc_hwmod_class, | |
1409 | .clkdm_name = "l4ls_clkdm", | |
1410 | .mpu_irqs = am33xx_mmc1_irqs, | |
1411 | .sdma_reqs = am33xx_mmc1_edma_reqs, | |
1412 | .main_clk = "mmc_clk", | |
1413 | .prcm = { | |
1414 | .omap4 = { | |
1415 | .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, | |
1416 | .modulemode = MODULEMODE_SWCTRL, | |
1417 | }, | |
1418 | }, | |
1419 | .dev_attr = &am33xx_mmc1_dev_attr, | |
1420 | }; | |
1421 | ||
1422 | /* mmc2 */ | |
1423 | static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { | |
1424 | { .irq = 29 + OMAP_INTC_START, }, | |
1425 | { .irq = -1 }, | |
1426 | }; | |
1427 | ||
1428 | static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { | |
1429 | { .name = "tx", .dma_req = 64, }, | |
1430 | { .name = "rx", .dma_req = 65, }, | |
1431 | { .dma_req = -1 } | |
1432 | }; | |
1433 | ||
1434 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { | |
1435 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1436 | }; | |
1437 | static struct omap_hwmod am33xx_mmc2_hwmod = { | |
1438 | .name = "mmc3", | |
1439 | .class = &am33xx_mmc_hwmod_class, | |
1440 | .clkdm_name = "l3s_clkdm", | |
1441 | .mpu_irqs = am33xx_mmc2_irqs, | |
1442 | .sdma_reqs = am33xx_mmc2_edma_reqs, | |
1443 | .main_clk = "mmc_clk", | |
1444 | .prcm = { | |
1445 | .omap4 = { | |
1446 | .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, | |
1447 | .modulemode = MODULEMODE_SWCTRL, | |
1448 | }, | |
1449 | }, | |
1450 | .dev_attr = &am33xx_mmc2_dev_attr, | |
1451 | }; | |
1452 | ||
1453 | /* | |
1454 | * 'rtc' class | |
1455 | * rtc subsystem | |
1456 | */ | |
1457 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | |
1458 | .rev_offs = 0x0074, | |
1459 | .sysc_offs = 0x0078, | |
1460 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1461 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | |
1462 | SIDLE_SMART | SIDLE_SMART_WKUP), | |
1463 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1464 | }; | |
1465 | ||
1466 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | |
1467 | .name = "rtc", | |
1468 | .sysc = &am33xx_rtc_sysc, | |
1469 | }; | |
1470 | ||
1471 | static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { | |
1472 | { .name = "rtcint", .irq = 75 + OMAP_INTC_START, }, | |
1473 | { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, }, | |
1474 | { .irq = -1 }, | |
1475 | }; | |
1476 | ||
1477 | static struct omap_hwmod am33xx_rtc_hwmod = { | |
1478 | .name = "rtc", | |
1479 | .class = &am33xx_rtc_hwmod_class, | |
1480 | .clkdm_name = "l4_rtc_clkdm", | |
1481 | .mpu_irqs = am33xx_rtc_irqs, | |
1482 | .main_clk = "clk_32768_ck", | |
1483 | .prcm = { | |
1484 | .omap4 = { | |
1485 | .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, | |
1486 | .modulemode = MODULEMODE_SWCTRL, | |
1487 | }, | |
1488 | }, | |
1489 | }; | |
1490 | ||
1491 | /* 'spi' class */ | |
1492 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | |
1493 | .rev_offs = 0x0000, | |
1494 | .sysc_offs = 0x0110, | |
1495 | .syss_offs = 0x0114, | |
1496 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1497 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1498 | SYSS_HAS_RESET_STATUS), | |
1499 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1500 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1501 | }; | |
1502 | ||
1503 | static struct omap_hwmod_class am33xx_spi_hwmod_class = { | |
1504 | .name = "mcspi", | |
1505 | .sysc = &am33xx_mcspi_sysc, | |
1506 | .rev = OMAP4_MCSPI_REV, | |
1507 | }; | |
1508 | ||
1509 | /* spi0 */ | |
1510 | static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { | |
1511 | { .irq = 65 + OMAP_INTC_START, }, | |
1512 | { .irq = -1 }, | |
1513 | }; | |
1514 | ||
1515 | static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = { | |
1516 | { .name = "rx0", .dma_req = 17 }, | |
1517 | { .name = "tx0", .dma_req = 16 }, | |
1518 | { .name = "rx1", .dma_req = 19 }, | |
1519 | { .name = "tx1", .dma_req = 18 }, | |
1520 | { .dma_req = -1 } | |
1521 | }; | |
1522 | ||
1523 | static struct omap2_mcspi_dev_attr mcspi_attrib = { | |
1524 | .num_chipselect = 2, | |
1525 | }; | |
1526 | static struct omap_hwmod am33xx_spi0_hwmod = { | |
1527 | .name = "spi0", | |
1528 | .class = &am33xx_spi_hwmod_class, | |
1529 | .clkdm_name = "l4ls_clkdm", | |
1530 | .mpu_irqs = am33xx_spi0_irqs, | |
1531 | .sdma_reqs = am33xx_mcspi0_edma_reqs, | |
1532 | .main_clk = "dpll_per_m2_div4_ck", | |
1533 | .prcm = { | |
1534 | .omap4 = { | |
1535 | .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, | |
1536 | .modulemode = MODULEMODE_SWCTRL, | |
1537 | }, | |
1538 | }, | |
1539 | .dev_attr = &mcspi_attrib, | |
1540 | }; | |
1541 | ||
1542 | /* spi1 */ | |
1543 | static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { | |
1544 | { .irq = 125 + OMAP_INTC_START, }, | |
1545 | { .irq = -1 }, | |
1546 | }; | |
1547 | ||
1548 | static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = { | |
1549 | { .name = "rx0", .dma_req = 43 }, | |
1550 | { .name = "tx0", .dma_req = 42 }, | |
1551 | { .name = "rx1", .dma_req = 45 }, | |
1552 | { .name = "tx1", .dma_req = 44 }, | |
1553 | { .dma_req = -1 } | |
1554 | }; | |
1555 | ||
1556 | static struct omap_hwmod am33xx_spi1_hwmod = { | |
1557 | .name = "spi1", | |
1558 | .class = &am33xx_spi_hwmod_class, | |
1559 | .clkdm_name = "l4ls_clkdm", | |
1560 | .mpu_irqs = am33xx_spi1_irqs, | |
1561 | .sdma_reqs = am33xx_mcspi1_edma_reqs, | |
1562 | .main_clk = "dpll_per_m2_div4_ck", | |
1563 | .prcm = { | |
1564 | .omap4 = { | |
1565 | .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, | |
1566 | .modulemode = MODULEMODE_SWCTRL, | |
1567 | }, | |
1568 | }, | |
1569 | .dev_attr = &mcspi_attrib, | |
1570 | }; | |
1571 | ||
1572 | /* | |
1573 | * 'spinlock' class | |
1574 | * spinlock provides hardware assistance for synchronizing the | |
1575 | * processes running on multiple processors | |
1576 | */ | |
1577 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { | |
1578 | .name = "spinlock", | |
1579 | }; | |
1580 | ||
1581 | static struct omap_hwmod am33xx_spinlock_hwmod = { | |
1582 | .name = "spinlock", | |
1583 | .class = &am33xx_spinlock_hwmod_class, | |
1584 | .clkdm_name = "l4ls_clkdm", | |
1585 | .main_clk = "l4ls_gclk", | |
1586 | .prcm = { | |
1587 | .omap4 = { | |
1588 | .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, | |
1589 | .modulemode = MODULEMODE_SWCTRL, | |
1590 | }, | |
1591 | }, | |
1592 | }; | |
1593 | ||
1594 | /* 'timer 2-7' class */ | |
1595 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | |
1596 | .rev_offs = 0x0000, | |
1597 | .sysc_offs = 0x0010, | |
1598 | .syss_offs = 0x0014, | |
1599 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1600 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1601 | SIDLE_SMART_WKUP), | |
1602 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1603 | }; | |
1604 | ||
1605 | static struct omap_hwmod_class am33xx_timer_hwmod_class = { | |
1606 | .name = "timer", | |
1607 | .sysc = &am33xx_timer_sysc, | |
1608 | }; | |
1609 | ||
1610 | /* timer1 1ms */ | |
1611 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | |
1612 | .rev_offs = 0x0000, | |
1613 | .sysc_offs = 0x0010, | |
1614 | .syss_offs = 0x0014, | |
1615 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1616 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1617 | SYSS_HAS_RESET_STATUS), | |
1618 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1619 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1620 | }; | |
1621 | ||
1622 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | |
1623 | .name = "timer", | |
1624 | .sysc = &am33xx_timer1ms_sysc, | |
1625 | }; | |
1626 | ||
1627 | static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { | |
1628 | { .irq = 67 + OMAP_INTC_START, }, | |
1629 | { .irq = -1 }, | |
1630 | }; | |
1631 | ||
1632 | static struct omap_hwmod am33xx_timer1_hwmod = { | |
1633 | .name = "timer1", | |
1634 | .class = &am33xx_timer1ms_hwmod_class, | |
1635 | .clkdm_name = "l4_wkup_clkdm", | |
1636 | .mpu_irqs = am33xx_timer1_irqs, | |
1637 | .main_clk = "timer1_fck", | |
1638 | .prcm = { | |
1639 | .omap4 = { | |
1640 | .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, | |
1641 | .modulemode = MODULEMODE_SWCTRL, | |
1642 | }, | |
1643 | }, | |
1644 | }; | |
1645 | ||
1646 | static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { | |
1647 | { .irq = 68 + OMAP_INTC_START, }, | |
1648 | { .irq = -1 }, | |
1649 | }; | |
1650 | ||
1651 | static struct omap_hwmod am33xx_timer2_hwmod = { | |
1652 | .name = "timer2", | |
1653 | .class = &am33xx_timer_hwmod_class, | |
1654 | .clkdm_name = "l4ls_clkdm", | |
1655 | .mpu_irqs = am33xx_timer2_irqs, | |
1656 | .main_clk = "timer2_fck", | |
1657 | .prcm = { | |
1658 | .omap4 = { | |
1659 | .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, | |
1660 | .modulemode = MODULEMODE_SWCTRL, | |
1661 | }, | |
1662 | }, | |
1663 | }; | |
1664 | ||
1665 | static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { | |
1666 | { .irq = 69 + OMAP_INTC_START, }, | |
1667 | { .irq = -1 }, | |
1668 | }; | |
1669 | ||
1670 | static struct omap_hwmod am33xx_timer3_hwmod = { | |
1671 | .name = "timer3", | |
1672 | .class = &am33xx_timer_hwmod_class, | |
1673 | .clkdm_name = "l4ls_clkdm", | |
1674 | .mpu_irqs = am33xx_timer3_irqs, | |
1675 | .main_clk = "timer3_fck", | |
1676 | .prcm = { | |
1677 | .omap4 = { | |
1678 | .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, | |
1679 | .modulemode = MODULEMODE_SWCTRL, | |
1680 | }, | |
1681 | }, | |
1682 | }; | |
1683 | ||
1684 | static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { | |
1685 | { .irq = 92 + OMAP_INTC_START, }, | |
1686 | { .irq = -1 }, | |
1687 | }; | |
1688 | ||
1689 | static struct omap_hwmod am33xx_timer4_hwmod = { | |
1690 | .name = "timer4", | |
1691 | .class = &am33xx_timer_hwmod_class, | |
1692 | .clkdm_name = "l4ls_clkdm", | |
1693 | .mpu_irqs = am33xx_timer4_irqs, | |
1694 | .main_clk = "timer4_fck", | |
1695 | .prcm = { | |
1696 | .omap4 = { | |
1697 | .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, | |
1698 | .modulemode = MODULEMODE_SWCTRL, | |
1699 | }, | |
1700 | }, | |
1701 | }; | |
1702 | ||
1703 | static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { | |
1704 | { .irq = 93 + OMAP_INTC_START, }, | |
1705 | { .irq = -1 }, | |
1706 | }; | |
1707 | ||
1708 | static struct omap_hwmod am33xx_timer5_hwmod = { | |
1709 | .name = "timer5", | |
1710 | .class = &am33xx_timer_hwmod_class, | |
1711 | .clkdm_name = "l4ls_clkdm", | |
1712 | .mpu_irqs = am33xx_timer5_irqs, | |
1713 | .main_clk = "timer5_fck", | |
1714 | .prcm = { | |
1715 | .omap4 = { | |
1716 | .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, | |
1717 | .modulemode = MODULEMODE_SWCTRL, | |
1718 | }, | |
1719 | }, | |
1720 | }; | |
1721 | ||
1722 | static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { | |
1723 | { .irq = 94 + OMAP_INTC_START, }, | |
1724 | { .irq = -1 }, | |
1725 | }; | |
1726 | ||
1727 | static struct omap_hwmod am33xx_timer6_hwmod = { | |
1728 | .name = "timer6", | |
1729 | .class = &am33xx_timer_hwmod_class, | |
1730 | .clkdm_name = "l4ls_clkdm", | |
1731 | .mpu_irqs = am33xx_timer6_irqs, | |
1732 | .main_clk = "timer6_fck", | |
1733 | .prcm = { | |
1734 | .omap4 = { | |
1735 | .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, | |
1736 | .modulemode = MODULEMODE_SWCTRL, | |
1737 | }, | |
1738 | }, | |
1739 | }; | |
1740 | ||
1741 | static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { | |
1742 | { .irq = 95 + OMAP_INTC_START, }, | |
1743 | { .irq = -1 }, | |
1744 | }; | |
1745 | ||
1746 | static struct omap_hwmod am33xx_timer7_hwmod = { | |
1747 | .name = "timer7", | |
1748 | .class = &am33xx_timer_hwmod_class, | |
1749 | .clkdm_name = "l4ls_clkdm", | |
1750 | .mpu_irqs = am33xx_timer7_irqs, | |
1751 | .main_clk = "timer7_fck", | |
1752 | .prcm = { | |
1753 | .omap4 = { | |
1754 | .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, | |
1755 | .modulemode = MODULEMODE_SWCTRL, | |
1756 | }, | |
1757 | }, | |
1758 | }; | |
1759 | ||
1760 | /* tpcc */ | |
1761 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | |
1762 | .name = "tpcc", | |
1763 | }; | |
1764 | ||
1765 | static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { | |
1766 | { .name = "edma0", .irq = 12 + OMAP_INTC_START, }, | |
1767 | { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, }, | |
1768 | { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, }, | |
1769 | { .irq = -1 }, | |
1770 | }; | |
1771 | ||
1772 | static struct omap_hwmod am33xx_tpcc_hwmod = { | |
1773 | .name = "tpcc", | |
1774 | .class = &am33xx_tpcc_hwmod_class, | |
1775 | .clkdm_name = "l3_clkdm", | |
1776 | .mpu_irqs = am33xx_tpcc_irqs, | |
1777 | .main_clk = "l3_gclk", | |
1778 | .prcm = { | |
1779 | .omap4 = { | |
1780 | .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, | |
1781 | .modulemode = MODULEMODE_SWCTRL, | |
1782 | }, | |
1783 | }, | |
1784 | }; | |
1785 | ||
1786 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | |
1787 | .rev_offs = 0x0, | |
1788 | .sysc_offs = 0x10, | |
1789 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1790 | SYSC_HAS_MIDLEMODE), | |
1791 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | |
1792 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1793 | }; | |
1794 | ||
1795 | /* 'tptc' class */ | |
1796 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | |
1797 | .name = "tptc", | |
1798 | .sysc = &am33xx_tptc_sysc, | |
1799 | }; | |
1800 | ||
1801 | /* tptc0 */ | |
1802 | static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { | |
1803 | { .irq = 112 + OMAP_INTC_START, }, | |
1804 | { .irq = -1 }, | |
1805 | }; | |
1806 | ||
1807 | static struct omap_hwmod am33xx_tptc0_hwmod = { | |
1808 | .name = "tptc0", | |
1809 | .class = &am33xx_tptc_hwmod_class, | |
1810 | .clkdm_name = "l3_clkdm", | |
1811 | .mpu_irqs = am33xx_tptc0_irqs, | |
1812 | .main_clk = "l3_gclk", | |
1813 | .prcm = { | |
1814 | .omap4 = { | |
1815 | .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, | |
1816 | .modulemode = MODULEMODE_SWCTRL, | |
1817 | }, | |
1818 | }, | |
1819 | }; | |
1820 | ||
1821 | /* tptc1 */ | |
1822 | static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { | |
1823 | { .irq = 113 + OMAP_INTC_START, }, | |
1824 | { .irq = -1 }, | |
1825 | }; | |
1826 | ||
1827 | static struct omap_hwmod am33xx_tptc1_hwmod = { | |
1828 | .name = "tptc1", | |
1829 | .class = &am33xx_tptc_hwmod_class, | |
1830 | .clkdm_name = "l3_clkdm", | |
1831 | .mpu_irqs = am33xx_tptc1_irqs, | |
1832 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
1833 | .main_clk = "l3_gclk", | |
1834 | .prcm = { | |
1835 | .omap4 = { | |
1836 | .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, | |
1837 | .modulemode = MODULEMODE_SWCTRL, | |
1838 | }, | |
1839 | }, | |
1840 | }; | |
1841 | ||
1842 | /* tptc2 */ | |
1843 | static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { | |
1844 | { .irq = 114 + OMAP_INTC_START, }, | |
1845 | { .irq = -1 }, | |
1846 | }; | |
1847 | ||
1848 | static struct omap_hwmod am33xx_tptc2_hwmod = { | |
1849 | .name = "tptc2", | |
1850 | .class = &am33xx_tptc_hwmod_class, | |
1851 | .clkdm_name = "l3_clkdm", | |
1852 | .mpu_irqs = am33xx_tptc2_irqs, | |
1853 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
1854 | .main_clk = "l3_gclk", | |
1855 | .prcm = { | |
1856 | .omap4 = { | |
1857 | .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, | |
1858 | .modulemode = MODULEMODE_SWCTRL, | |
1859 | }, | |
1860 | }, | |
1861 | }; | |
1862 | ||
1863 | /* 'uart' class */ | |
1864 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
1865 | .rev_offs = 0x50, | |
1866 | .sysc_offs = 0x54, | |
1867 | .syss_offs = 0x58, | |
1868 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1869 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1870 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1871 | SIDLE_SMART_WKUP), | |
1872 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1873 | }; | |
1874 | ||
1875 | static struct omap_hwmod_class uart_class = { | |
1876 | .name = "uart", | |
1877 | .sysc = &uart_sysc, | |
1878 | }; | |
1879 | ||
1880 | /* uart1 */ | |
1881 | static struct omap_hwmod_dma_info uart1_edma_reqs[] = { | |
1882 | { .name = "tx", .dma_req = 26, }, | |
1883 | { .name = "rx", .dma_req = 27, }, | |
1884 | { .dma_req = -1 } | |
1885 | }; | |
1886 | ||
1887 | static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { | |
1888 | { .irq = 72 + OMAP_INTC_START, }, | |
1889 | { .irq = -1 }, | |
1890 | }; | |
1891 | ||
1892 | static struct omap_hwmod am33xx_uart1_hwmod = { | |
1893 | .name = "uart1", | |
1894 | .class = &uart_class, | |
1895 | .clkdm_name = "l4_wkup_clkdm", | |
1896 | .mpu_irqs = am33xx_uart1_irqs, | |
1897 | .sdma_reqs = uart1_edma_reqs, | |
1898 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
1899 | .prcm = { | |
1900 | .omap4 = { | |
1901 | .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, | |
1902 | .modulemode = MODULEMODE_SWCTRL, | |
1903 | }, | |
1904 | }, | |
1905 | }; | |
1906 | ||
1907 | static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { | |
1908 | { .irq = 73 + OMAP_INTC_START, }, | |
1909 | { .irq = -1 }, | |
1910 | }; | |
1911 | ||
1912 | static struct omap_hwmod am33xx_uart2_hwmod = { | |
1913 | .name = "uart2", | |
1914 | .class = &uart_class, | |
1915 | .clkdm_name = "l4ls_clkdm", | |
1916 | .mpu_irqs = am33xx_uart2_irqs, | |
1917 | .sdma_reqs = uart1_edma_reqs, | |
1918 | .main_clk = "dpll_per_m2_div4_ck", | |
1919 | .prcm = { | |
1920 | .omap4 = { | |
1921 | .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, | |
1922 | .modulemode = MODULEMODE_SWCTRL, | |
1923 | }, | |
1924 | }, | |
1925 | }; | |
1926 | ||
1927 | /* uart3 */ | |
1928 | static struct omap_hwmod_dma_info uart3_edma_reqs[] = { | |
1929 | { .name = "tx", .dma_req = 30, }, | |
1930 | { .name = "rx", .dma_req = 31, }, | |
1931 | { .dma_req = -1 } | |
1932 | }; | |
1933 | ||
1934 | static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { | |
1935 | { .irq = 74 + OMAP_INTC_START, }, | |
1936 | { .irq = -1 }, | |
1937 | }; | |
1938 | ||
1939 | static struct omap_hwmod am33xx_uart3_hwmod = { | |
1940 | .name = "uart3", | |
1941 | .class = &uart_class, | |
1942 | .clkdm_name = "l4ls_clkdm", | |
1943 | .mpu_irqs = am33xx_uart3_irqs, | |
1944 | .sdma_reqs = uart3_edma_reqs, | |
1945 | .main_clk = "dpll_per_m2_div4_ck", | |
1946 | .prcm = { | |
1947 | .omap4 = { | |
1948 | .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, | |
1949 | .modulemode = MODULEMODE_SWCTRL, | |
1950 | }, | |
1951 | }, | |
1952 | }; | |
1953 | ||
1954 | static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { | |
1955 | { .irq = 44 + OMAP_INTC_START, }, | |
1956 | { .irq = -1 }, | |
1957 | }; | |
1958 | ||
1959 | static struct omap_hwmod am33xx_uart4_hwmod = { | |
1960 | .name = "uart4", | |
1961 | .class = &uart_class, | |
1962 | .clkdm_name = "l4ls_clkdm", | |
1963 | .mpu_irqs = am33xx_uart4_irqs, | |
1964 | .sdma_reqs = uart1_edma_reqs, | |
1965 | .main_clk = "dpll_per_m2_div4_ck", | |
1966 | .prcm = { | |
1967 | .omap4 = { | |
1968 | .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, | |
1969 | .modulemode = MODULEMODE_SWCTRL, | |
1970 | }, | |
1971 | }, | |
1972 | }; | |
1973 | ||
1974 | static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { | |
1975 | { .irq = 45 + OMAP_INTC_START, }, | |
1976 | { .irq = -1 }, | |
1977 | }; | |
1978 | ||
1979 | static struct omap_hwmod am33xx_uart5_hwmod = { | |
1980 | .name = "uart5", | |
1981 | .class = &uart_class, | |
1982 | .clkdm_name = "l4ls_clkdm", | |
1983 | .mpu_irqs = am33xx_uart5_irqs, | |
1984 | .sdma_reqs = uart1_edma_reqs, | |
1985 | .main_clk = "dpll_per_m2_div4_ck", | |
1986 | .prcm = { | |
1987 | .omap4 = { | |
1988 | .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, | |
1989 | .modulemode = MODULEMODE_SWCTRL, | |
1990 | }, | |
1991 | }, | |
1992 | }; | |
1993 | ||
1994 | static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { | |
1995 | { .irq = 46 + OMAP_INTC_START, }, | |
1996 | { .irq = -1 }, | |
1997 | }; | |
1998 | ||
1999 | static struct omap_hwmod am33xx_uart6_hwmod = { | |
2000 | .name = "uart6", | |
2001 | .class = &uart_class, | |
2002 | .clkdm_name = "l4ls_clkdm", | |
2003 | .mpu_irqs = am33xx_uart6_irqs, | |
2004 | .sdma_reqs = uart1_edma_reqs, | |
2005 | .main_clk = "dpll_per_m2_div4_ck", | |
2006 | .prcm = { | |
2007 | .omap4 = { | |
2008 | .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, | |
2009 | .modulemode = MODULEMODE_SWCTRL, | |
2010 | }, | |
2011 | }, | |
2012 | }; | |
2013 | ||
2014 | /* 'wd_timer' class */ | |
2015 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { | |
2016 | .name = "wd_timer", | |
2017 | }; | |
2018 | ||
2019 | /* | |
2020 | * XXX: device.c file uses hardcoded name for watchdog timer | |
2021 | * driver "wd_timer2, so we are also using same name as of now... | |
2022 | */ | |
2023 | static struct omap_hwmod am33xx_wd_timer1_hwmod = { | |
2024 | .name = "wd_timer2", | |
2025 | .class = &am33xx_wd_timer_hwmod_class, | |
2026 | .clkdm_name = "l4_wkup_clkdm", | |
2027 | .main_clk = "wdt1_fck", | |
2028 | .prcm = { | |
2029 | .omap4 = { | |
2030 | .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, | |
2031 | .modulemode = MODULEMODE_SWCTRL, | |
2032 | }, | |
2033 | }, | |
2034 | }; | |
2035 | ||
2036 | /* | |
2037 | * 'usb_otg' class | |
2038 | * high-speed on-the-go universal serial bus (usb_otg) controller | |
2039 | */ | |
2040 | static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { | |
2041 | .rev_offs = 0x0, | |
2042 | .sysc_offs = 0x10, | |
2043 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
2044 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2045 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
2046 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2047 | }; | |
2048 | ||
2049 | static struct omap_hwmod_class am33xx_usbotg_class = { | |
2050 | .name = "usbotg", | |
2051 | .sysc = &am33xx_usbhsotg_sysc, | |
2052 | }; | |
2053 | ||
2054 | static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { | |
2055 | { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, | |
2056 | { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, | |
2057 | { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, | |
2058 | { .irq = -1 + OMAP_INTC_START, }, | |
2059 | }; | |
2060 | ||
2061 | static struct omap_hwmod am33xx_usbss_hwmod = { | |
2062 | .name = "usb_otg_hs", | |
2063 | .class = &am33xx_usbotg_class, | |
2064 | .clkdm_name = "l3s_clkdm", | |
2065 | .mpu_irqs = am33xx_usbss_mpu_irqs, | |
2066 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
2067 | .main_clk = "usbotg_fck", | |
2068 | .prcm = { | |
2069 | .omap4 = { | |
2070 | .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, | |
2071 | .modulemode = MODULEMODE_SWCTRL, | |
2072 | }, | |
2073 | }, | |
2074 | }; | |
2075 | ||
2076 | ||
2077 | /* | |
2078 | * Interfaces | |
2079 | */ | |
2080 | ||
2081 | /* l4 fw -> emif fw */ | |
2082 | static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = { | |
2083 | .master = &am33xx_l4_fw_hwmod, | |
2084 | .slave = &am33xx_emif_fw_hwmod, | |
2085 | .clk = "l4fw_gclk", | |
2086 | .user = OCP_USER_MPU, | |
2087 | }; | |
2088 | ||
2089 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { | |
2090 | { | |
2091 | .pa_start = 0x4c000000, | |
2092 | .pa_end = 0x4c000fff, | |
2093 | .flags = ADDR_TYPE_RT | |
2094 | }, | |
2095 | { } | |
2096 | }; | |
2097 | /* l3 main -> emif */ | |
2098 | static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { | |
2099 | .master = &am33xx_l3_main_hwmod, | |
2100 | .slave = &am33xx_emif_hwmod, | |
2101 | .clk = "dpll_core_m4_ck", | |
2102 | .addr = am33xx_emif_addrs, | |
2103 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2104 | }; | |
2105 | ||
2106 | /* mpu -> l3 main */ | |
2107 | static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | |
2108 | .master = &am33xx_mpu_hwmod, | |
2109 | .slave = &am33xx_l3_main_hwmod, | |
2110 | .clk = "dpll_mpu_m2_ck", | |
2111 | .user = OCP_USER_MPU, | |
2112 | }; | |
2113 | ||
2114 | /* l3 main -> l4 hs */ | |
2115 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { | |
2116 | .master = &am33xx_l3_main_hwmod, | |
2117 | .slave = &am33xx_l4_hs_hwmod, | |
2118 | .clk = "l3s_gclk", | |
2119 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2120 | }; | |
2121 | ||
2122 | /* l3 main -> l3 s */ | |
2123 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | |
2124 | .master = &am33xx_l3_main_hwmod, | |
2125 | .slave = &am33xx_l3_s_hwmod, | |
2126 | .clk = "l3s_gclk", | |
2127 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2128 | }; | |
2129 | ||
2130 | /* l3 s -> l4 per/ls */ | |
2131 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | |
2132 | .master = &am33xx_l3_s_hwmod, | |
2133 | .slave = &am33xx_l4_ls_hwmod, | |
2134 | .clk = "l3s_gclk", | |
2135 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2136 | }; | |
2137 | ||
2138 | /* l3 s -> l4 wkup */ | |
2139 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |
2140 | .master = &am33xx_l3_s_hwmod, | |
2141 | .slave = &am33xx_l4_wkup_hwmod, | |
2142 | .clk = "l3s_gclk", | |
2143 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2144 | }; | |
2145 | ||
2146 | /* l3 s -> l4 fw */ | |
2147 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = { | |
2148 | .master = &am33xx_l3_s_hwmod, | |
2149 | .slave = &am33xx_l4_fw_hwmod, | |
2150 | .clk = "l3s_gclk", | |
2151 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2152 | }; | |
2153 | ||
2154 | /* l3 main -> l3 instr */ | |
2155 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | |
2156 | .master = &am33xx_l3_main_hwmod, | |
2157 | .slave = &am33xx_l3_instr_hwmod, | |
2158 | .clk = "l3s_gclk", | |
2159 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2160 | }; | |
2161 | ||
2162 | /* mpu -> prcm */ | |
2163 | static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | |
2164 | .master = &am33xx_mpu_hwmod, | |
2165 | .slave = &am33xx_prcm_hwmod, | |
2166 | .clk = "dpll_mpu_m2_ck", | |
2167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2168 | }; | |
2169 | ||
2170 | /* l3 s -> l3 main*/ | |
2171 | static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | |
2172 | .master = &am33xx_l3_s_hwmod, | |
2173 | .slave = &am33xx_l3_main_hwmod, | |
2174 | .clk = "l3s_gclk", | |
2175 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2176 | }; | |
2177 | ||
2178 | /* pru-icss -> l3 main */ | |
2179 | static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | |
2180 | .master = &am33xx_pruss_hwmod, | |
2181 | .slave = &am33xx_l3_main_hwmod, | |
2182 | .clk = "l3_gclk", | |
2183 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2184 | }; | |
2185 | ||
2186 | /* wkup m3 -> l4 wkup */ | |
2187 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { | |
2188 | .master = &am33xx_wkup_m3_hwmod, | |
2189 | .slave = &am33xx_l4_wkup_hwmod, | |
2190 | .clk = "dpll_core_m4_div2_ck", | |
2191 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2192 | }; | |
2193 | ||
2194 | /* gfx -> l3 main */ | |
2195 | static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |
2196 | .master = &am33xx_gfx_hwmod, | |
2197 | .slave = &am33xx_l3_main_hwmod, | |
2198 | .clk = "dpll_core_m4_ck", | |
2199 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2200 | }; | |
2201 | ||
2202 | /* l4 wkup -> wkup m3 */ | |
2203 | static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = { | |
2204 | { | |
2205 | .name = "umem", | |
2206 | .pa_start = 0x44d00000, | |
2207 | .pa_end = 0x44d00000 + SZ_16K - 1, | |
2208 | .flags = ADDR_TYPE_RT | |
2209 | }, | |
2210 | { | |
2211 | .name = "dmem", | |
2212 | .pa_start = 0x44d80000, | |
2213 | .pa_end = 0x44d80000 + SZ_8K - 1, | |
2214 | .flags = ADDR_TYPE_RT | |
2215 | }, | |
2216 | { } | |
2217 | }; | |
2218 | ||
2219 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { | |
2220 | .master = &am33xx_l4_wkup_hwmod, | |
2221 | .slave = &am33xx_wkup_m3_hwmod, | |
2222 | .clk = "dpll_core_m4_div2_ck", | |
2223 | .addr = am33xx_wkup_m3_addrs, | |
2224 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2225 | }; | |
2226 | ||
2227 | /* l4 hs -> pru-icss */ | |
2228 | static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = { | |
2229 | { | |
2230 | .pa_start = 0x4a300000, | |
2231 | .pa_end = 0x4a300000 + SZ_512K - 1, | |
2232 | .flags = ADDR_TYPE_RT | |
2233 | }, | |
2234 | { } | |
2235 | }; | |
2236 | ||
2237 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { | |
2238 | .master = &am33xx_l4_hs_hwmod, | |
2239 | .slave = &am33xx_pruss_hwmod, | |
2240 | .clk = "dpll_core_m4_ck", | |
2241 | .addr = am33xx_pruss_addrs, | |
2242 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2243 | }; | |
2244 | ||
2245 | /* l3 main -> gfx */ | |
2246 | static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = { | |
2247 | { | |
2248 | .pa_start = 0x56000000, | |
2249 | .pa_end = 0x56000000 + SZ_16M - 1, | |
2250 | .flags = ADDR_TYPE_RT | |
2251 | }, | |
2252 | { } | |
2253 | }; | |
2254 | ||
2255 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | |
2256 | .master = &am33xx_l3_main_hwmod, | |
2257 | .slave = &am33xx_gfx_hwmod, | |
2258 | .clk = "dpll_core_m4_ck", | |
2259 | .addr = am33xx_gfx_addrs, | |
2260 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2261 | }; | |
2262 | ||
2263 | /* l4 wkup -> smartreflex0 */ | |
2264 | static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = { | |
2265 | { | |
2266 | .pa_start = 0x44e37000, | |
2267 | .pa_end = 0x44e37000 + SZ_4K - 1, | |
2268 | .flags = ADDR_TYPE_RT | |
2269 | }, | |
2270 | { } | |
2271 | }; | |
2272 | ||
2273 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { | |
2274 | .master = &am33xx_l4_wkup_hwmod, | |
2275 | .slave = &am33xx_smartreflex0_hwmod, | |
2276 | .clk = "dpll_core_m4_div2_ck", | |
2277 | .addr = am33xx_smartreflex0_addrs, | |
2278 | .user = OCP_USER_MPU, | |
2279 | }; | |
2280 | ||
2281 | /* l4 wkup -> smartreflex1 */ | |
2282 | static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = { | |
2283 | { | |
2284 | .pa_start = 0x44e39000, | |
2285 | .pa_end = 0x44e39000 + SZ_4K - 1, | |
2286 | .flags = ADDR_TYPE_RT | |
2287 | }, | |
2288 | { } | |
2289 | }; | |
2290 | ||
2291 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { | |
2292 | .master = &am33xx_l4_wkup_hwmod, | |
2293 | .slave = &am33xx_smartreflex1_hwmod, | |
2294 | .clk = "dpll_core_m4_div2_ck", | |
2295 | .addr = am33xx_smartreflex1_addrs, | |
2296 | .user = OCP_USER_MPU, | |
2297 | }; | |
2298 | ||
2299 | /* l4 wkup -> control */ | |
2300 | static struct omap_hwmod_addr_space am33xx_control_addrs[] = { | |
2301 | { | |
2302 | .pa_start = 0x44e10000, | |
2303 | .pa_end = 0x44e10000 + SZ_8K - 1, | |
2304 | .flags = ADDR_TYPE_RT | |
2305 | }, | |
2306 | { } | |
2307 | }; | |
2308 | ||
2309 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { | |
2310 | .master = &am33xx_l4_wkup_hwmod, | |
2311 | .slave = &am33xx_control_hwmod, | |
2312 | .clk = "dpll_core_m4_div2_ck", | |
2313 | .addr = am33xx_control_addrs, | |
2314 | .user = OCP_USER_MPU, | |
2315 | }; | |
2316 | ||
2317 | /* l4 wkup -> rtc */ | |
2318 | static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = { | |
2319 | { | |
2320 | .pa_start = 0x44e3e000, | |
2321 | .pa_end = 0x44e3e000 + SZ_4K - 1, | |
2322 | .flags = ADDR_TYPE_RT | |
2323 | }, | |
2324 | { } | |
2325 | }; | |
2326 | ||
2327 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | |
2328 | .master = &am33xx_l4_wkup_hwmod, | |
2329 | .slave = &am33xx_rtc_hwmod, | |
2330 | .clk = "clkdiv32k_ick", | |
2331 | .addr = am33xx_rtc_addrs, | |
2332 | .user = OCP_USER_MPU, | |
2333 | }; | |
2334 | ||
2335 | /* l4 per/ls -> DCAN0 */ | |
2336 | static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = { | |
2337 | { | |
2338 | .pa_start = 0x481CC000, | |
2339 | .pa_end = 0x481CC000 + SZ_4K - 1, | |
2340 | .flags = ADDR_TYPE_RT | |
2341 | }, | |
2342 | { } | |
2343 | }; | |
2344 | ||
2345 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | |
2346 | .master = &am33xx_l4_ls_hwmod, | |
2347 | .slave = &am33xx_dcan0_hwmod, | |
2348 | .clk = "l4ls_gclk", | |
2349 | .addr = am33xx_dcan0_addrs, | |
2350 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2351 | }; | |
2352 | ||
2353 | /* l4 per/ls -> DCAN1 */ | |
2354 | static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = { | |
2355 | { | |
2356 | .pa_start = 0x481D0000, | |
2357 | .pa_end = 0x481D0000 + SZ_4K - 1, | |
2358 | .flags = ADDR_TYPE_RT | |
2359 | }, | |
2360 | { } | |
2361 | }; | |
2362 | ||
2363 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | |
2364 | .master = &am33xx_l4_ls_hwmod, | |
2365 | .slave = &am33xx_dcan1_hwmod, | |
2366 | .clk = "l4ls_gclk", | |
2367 | .addr = am33xx_dcan1_addrs, | |
2368 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2369 | }; | |
2370 | ||
2371 | /* l4 per/ls -> GPIO2 */ | |
2372 | static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { | |
2373 | { | |
2374 | .pa_start = 0x4804C000, | |
2375 | .pa_end = 0x4804C000 + SZ_4K - 1, | |
2376 | .flags = ADDR_TYPE_RT, | |
2377 | }, | |
2378 | { } | |
2379 | }; | |
2380 | ||
2381 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | |
2382 | .master = &am33xx_l4_ls_hwmod, | |
2383 | .slave = &am33xx_gpio1_hwmod, | |
2384 | .clk = "l4ls_gclk", | |
2385 | .addr = am33xx_gpio1_addrs, | |
2386 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2387 | }; | |
2388 | ||
2389 | /* l4 per/ls -> gpio3 */ | |
2390 | static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { | |
2391 | { | |
2392 | .pa_start = 0x481AC000, | |
2393 | .pa_end = 0x481AC000 + SZ_4K - 1, | |
2394 | .flags = ADDR_TYPE_RT, | |
2395 | }, | |
2396 | { } | |
2397 | }; | |
2398 | ||
2399 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | |
2400 | .master = &am33xx_l4_ls_hwmod, | |
2401 | .slave = &am33xx_gpio2_hwmod, | |
2402 | .clk = "l4ls_gclk", | |
2403 | .addr = am33xx_gpio2_addrs, | |
2404 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2405 | }; | |
2406 | ||
2407 | /* l4 per/ls -> gpio4 */ | |
2408 | static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { | |
2409 | { | |
2410 | .pa_start = 0x481AE000, | |
2411 | .pa_end = 0x481AE000 + SZ_4K - 1, | |
2412 | .flags = ADDR_TYPE_RT, | |
2413 | }, | |
2414 | { } | |
2415 | }; | |
2416 | ||
2417 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | |
2418 | .master = &am33xx_l4_ls_hwmod, | |
2419 | .slave = &am33xx_gpio3_hwmod, | |
2420 | .clk = "l4ls_gclk", | |
2421 | .addr = am33xx_gpio3_addrs, | |
2422 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2423 | }; | |
2424 | ||
2425 | /* L4 WKUP -> I2C1 */ | |
2426 | static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { | |
2427 | { | |
2428 | .pa_start = 0x44E0B000, | |
2429 | .pa_end = 0x44E0B000 + SZ_4K - 1, | |
2430 | .flags = ADDR_TYPE_RT, | |
2431 | }, | |
2432 | { } | |
2433 | }; | |
2434 | ||
2435 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { | |
2436 | .master = &am33xx_l4_wkup_hwmod, | |
2437 | .slave = &am33xx_i2c1_hwmod, | |
2438 | .clk = "dpll_core_m4_div2_ck", | |
2439 | .addr = am33xx_i2c1_addr_space, | |
2440 | .user = OCP_USER_MPU, | |
2441 | }; | |
2442 | ||
2443 | /* L4 WKUP -> GPIO1 */ | |
2444 | static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { | |
2445 | { | |
2446 | .pa_start = 0x44E07000, | |
2447 | .pa_end = 0x44E07000 + SZ_4K - 1, | |
2448 | .flags = ADDR_TYPE_RT, | |
2449 | }, | |
2450 | { } | |
2451 | }; | |
2452 | ||
2453 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { | |
2454 | .master = &am33xx_l4_wkup_hwmod, | |
2455 | .slave = &am33xx_gpio0_hwmod, | |
2456 | .clk = "dpll_core_m4_div2_ck", | |
2457 | .addr = am33xx_gpio0_addrs, | |
2458 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2459 | }; | |
2460 | ||
2461 | /* L4 WKUP -> ADC_TSC */ | |
2462 | static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { | |
2463 | { | |
2464 | .pa_start = 0x44E0D000, | |
2465 | .pa_end = 0x44E0D000 + SZ_8K - 1, | |
2466 | .flags = ADDR_TYPE_RT | |
2467 | }, | |
2468 | { } | |
2469 | }; | |
2470 | ||
2471 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { | |
2472 | .master = &am33xx_l4_wkup_hwmod, | |
2473 | .slave = &am33xx_adc_tsc_hwmod, | |
2474 | .clk = "dpll_core_m4_div2_ck", | |
2475 | .addr = am33xx_adc_tsc_addrs, | |
2476 | .user = OCP_USER_MPU, | |
2477 | }; | |
2478 | ||
2479 | static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = { | |
2480 | /* cpsw ss */ | |
2481 | { | |
2482 | .pa_start = 0x4a100000, | |
2483 | .pa_end = 0x4a100000 + SZ_2K - 1, | |
2484 | .flags = ADDR_TYPE_RT, | |
2485 | }, | |
2486 | /* cpsw wr */ | |
2487 | { | |
2488 | .pa_start = 0x4a101200, | |
2489 | .pa_end = 0x4a101200 + SZ_256 - 1, | |
2490 | .flags = ADDR_TYPE_RT, | |
2491 | }, | |
2492 | { } | |
2493 | }; | |
2494 | ||
2495 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { | |
2496 | .master = &am33xx_l4_hs_hwmod, | |
2497 | .slave = &am33xx_cpgmac0_hwmod, | |
2498 | .clk = "cpsw_125mhz_gclk", | |
2499 | .addr = am33xx_cpgmac0_addr_space, | |
2500 | .user = OCP_USER_MPU, | |
2501 | }; | |
2502 | ||
2503 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { | |
2504 | { | |
2505 | .pa_start = 0x48080000, | |
2506 | .pa_end = 0x48080000 + SZ_8K - 1, | |
2507 | .flags = ADDR_TYPE_RT | |
2508 | }, | |
2509 | { } | |
2510 | }; | |
2511 | ||
2512 | static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | |
2513 | .master = &am33xx_l4_ls_hwmod, | |
2514 | .slave = &am33xx_elm_hwmod, | |
2515 | .clk = "l4ls_gclk", | |
2516 | .addr = am33xx_elm_addr_space, | |
2517 | .user = OCP_USER_MPU, | |
2518 | }; | |
2519 | ||
2520 | /* | |
2521 | * Splitting the resources to handle access of PWMSS config space | |
2522 | * and module specific part independently | |
2523 | */ | |
2524 | static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { | |
2525 | { | |
2526 | .pa_start = 0x48300000, | |
2527 | .pa_end = 0x48300000 + SZ_16 - 1, | |
2528 | .flags = ADDR_TYPE_RT | |
2529 | }, | |
2530 | { | |
2531 | .pa_start = 0x48300200, | |
2532 | .pa_end = 0x48300200 + SZ_256 - 1, | |
2533 | .flags = ADDR_TYPE_RT | |
2534 | }, | |
2535 | { } | |
2536 | }; | |
2537 | ||
2538 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { | |
2539 | .master = &am33xx_l4_ls_hwmod, | |
2540 | .slave = &am33xx_ehrpwm0_hwmod, | |
2541 | .clk = "l4ls_gclk", | |
2542 | .addr = am33xx_ehrpwm0_addr_space, | |
2543 | .user = OCP_USER_MPU, | |
2544 | }; | |
2545 | ||
2546 | /* | |
2547 | * Splitting the resources to handle access of PWMSS config space | |
2548 | * and module specific part independently | |
2549 | */ | |
2550 | static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { | |
2551 | { | |
2552 | .pa_start = 0x48302000, | |
2553 | .pa_end = 0x48302000 + SZ_16 - 1, | |
2554 | .flags = ADDR_TYPE_RT | |
2555 | }, | |
2556 | { | |
2557 | .pa_start = 0x48302200, | |
2558 | .pa_end = 0x48302200 + SZ_256 - 1, | |
2559 | .flags = ADDR_TYPE_RT | |
2560 | }, | |
2561 | { } | |
2562 | }; | |
2563 | ||
2564 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { | |
2565 | .master = &am33xx_l4_ls_hwmod, | |
2566 | .slave = &am33xx_ehrpwm1_hwmod, | |
2567 | .clk = "l4ls_gclk", | |
2568 | .addr = am33xx_ehrpwm1_addr_space, | |
2569 | .user = OCP_USER_MPU, | |
2570 | }; | |
2571 | ||
2572 | /* | |
2573 | * Splitting the resources to handle access of PWMSS config space | |
2574 | * and module specific part independently | |
2575 | */ | |
2576 | static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { | |
2577 | { | |
2578 | .pa_start = 0x48304000, | |
2579 | .pa_end = 0x48304000 + SZ_16 - 1, | |
2580 | .flags = ADDR_TYPE_RT | |
2581 | }, | |
2582 | { | |
2583 | .pa_start = 0x48304200, | |
2584 | .pa_end = 0x48304200 + SZ_256 - 1, | |
2585 | .flags = ADDR_TYPE_RT | |
2586 | }, | |
2587 | { } | |
2588 | }; | |
2589 | ||
2590 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { | |
2591 | .master = &am33xx_l4_ls_hwmod, | |
2592 | .slave = &am33xx_ehrpwm2_hwmod, | |
2593 | .clk = "l4ls_gclk", | |
2594 | .addr = am33xx_ehrpwm2_addr_space, | |
2595 | .user = OCP_USER_MPU, | |
2596 | }; | |
2597 | ||
2598 | /* | |
2599 | * Splitting the resources to handle access of PWMSS config space | |
2600 | * and module specific part independently | |
2601 | */ | |
2602 | static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { | |
2603 | { | |
2604 | .pa_start = 0x48300000, | |
2605 | .pa_end = 0x48300000 + SZ_16 - 1, | |
2606 | .flags = ADDR_TYPE_RT | |
2607 | }, | |
2608 | { | |
2609 | .pa_start = 0x48300100, | |
2610 | .pa_end = 0x48300100 + SZ_256 - 1, | |
2611 | .flags = ADDR_TYPE_RT | |
2612 | }, | |
2613 | { } | |
2614 | }; | |
2615 | ||
2616 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { | |
2617 | .master = &am33xx_l4_ls_hwmod, | |
2618 | .slave = &am33xx_ecap0_hwmod, | |
2619 | .clk = "l4ls_gclk", | |
2620 | .addr = am33xx_ecap0_addr_space, | |
2621 | .user = OCP_USER_MPU, | |
2622 | }; | |
2623 | ||
2624 | /* | |
2625 | * Splitting the resources to handle access of PWMSS config space | |
2626 | * and module specific part independently | |
2627 | */ | |
2628 | static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { | |
2629 | { | |
2630 | .pa_start = 0x48302000, | |
2631 | .pa_end = 0x48302000 + SZ_16 - 1, | |
2632 | .flags = ADDR_TYPE_RT | |
2633 | }, | |
2634 | { | |
2635 | .pa_start = 0x48302100, | |
2636 | .pa_end = 0x48302100 + SZ_256 - 1, | |
2637 | .flags = ADDR_TYPE_RT | |
2638 | }, | |
2639 | { } | |
2640 | }; | |
2641 | ||
2642 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { | |
2643 | .master = &am33xx_l4_ls_hwmod, | |
2644 | .slave = &am33xx_ecap1_hwmod, | |
2645 | .clk = "l4ls_gclk", | |
2646 | .addr = am33xx_ecap1_addr_space, | |
2647 | .user = OCP_USER_MPU, | |
2648 | }; | |
2649 | ||
2650 | /* | |
2651 | * Splitting the resources to handle access of PWMSS config space | |
2652 | * and module specific part independently | |
2653 | */ | |
2654 | static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { | |
2655 | { | |
2656 | .pa_start = 0x48304000, | |
2657 | .pa_end = 0x48304000 + SZ_16 - 1, | |
2658 | .flags = ADDR_TYPE_RT | |
2659 | }, | |
2660 | { | |
2661 | .pa_start = 0x48304100, | |
2662 | .pa_end = 0x48304100 + SZ_256 - 1, | |
2663 | .flags = ADDR_TYPE_RT | |
2664 | }, | |
2665 | { } | |
2666 | }; | |
2667 | ||
2668 | static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { | |
2669 | .master = &am33xx_l4_ls_hwmod, | |
2670 | .slave = &am33xx_ecap2_hwmod, | |
2671 | .clk = "l4ls_gclk", | |
2672 | .addr = am33xx_ecap2_addr_space, | |
2673 | .user = OCP_USER_MPU, | |
2674 | }; | |
2675 | ||
2676 | /* l3s cfg -> gpmc */ | |
2677 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | |
2678 | { | |
2679 | .pa_start = 0x50000000, | |
2680 | .pa_end = 0x50000000 + SZ_8K - 1, | |
2681 | .flags = ADDR_TYPE_RT, | |
2682 | }, | |
2683 | { } | |
2684 | }; | |
2685 | ||
2686 | static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | |
2687 | .master = &am33xx_l3_s_hwmod, | |
2688 | .slave = &am33xx_gpmc_hwmod, | |
2689 | .clk = "l3s_gclk", | |
2690 | .addr = am33xx_gpmc_addr_space, | |
2691 | .user = OCP_USER_MPU, | |
2692 | }; | |
2693 | ||
2694 | /* i2c2 */ | |
2695 | static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { | |
2696 | { | |
2697 | .pa_start = 0x4802A000, | |
2698 | .pa_end = 0x4802A000 + SZ_4K - 1, | |
2699 | .flags = ADDR_TYPE_RT, | |
2700 | }, | |
2701 | { } | |
2702 | }; | |
2703 | ||
2704 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | |
2705 | .master = &am33xx_l4_ls_hwmod, | |
2706 | .slave = &am33xx_i2c2_hwmod, | |
2707 | .clk = "l4ls_gclk", | |
2708 | .addr = am33xx_i2c2_addr_space, | |
2709 | .user = OCP_USER_MPU, | |
2710 | }; | |
2711 | ||
2712 | static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = { | |
2713 | { | |
2714 | .pa_start = 0x4819C000, | |
2715 | .pa_end = 0x4819C000 + SZ_4K - 1, | |
2716 | .flags = ADDR_TYPE_RT | |
2717 | }, | |
2718 | { } | |
2719 | }; | |
2720 | ||
2721 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | |
2722 | .master = &am33xx_l4_ls_hwmod, | |
2723 | .slave = &am33xx_i2c3_hwmod, | |
2724 | .clk = "l4ls_gclk", | |
2725 | .addr = am33xx_i2c3_addr_space, | |
2726 | .user = OCP_USER_MPU, | |
2727 | }; | |
2728 | ||
2729 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { | |
2730 | { | |
2731 | .pa_start = 0x4830E000, | |
2732 | .pa_end = 0x4830E000 + SZ_8K - 1, | |
2733 | .flags = ADDR_TYPE_RT, | |
2734 | }, | |
2735 | { } | |
2736 | }; | |
2737 | ||
2738 | static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { | |
2739 | .master = &am33xx_l3_main_hwmod, | |
2740 | .slave = &am33xx_lcdc_hwmod, | |
2741 | .clk = "dpll_core_m4_ck", | |
2742 | .addr = am33xx_lcdc_addr_space, | |
2743 | .user = OCP_USER_MPU, | |
2744 | }; | |
2745 | ||
2746 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { | |
2747 | { | |
2748 | .pa_start = 0x480C8000, | |
2749 | .pa_end = 0x480C8000 + (SZ_4K - 1), | |
2750 | .flags = ADDR_TYPE_RT | |
2751 | }, | |
2752 | { } | |
2753 | }; | |
2754 | ||
2755 | /* l4 ls -> mailbox */ | |
2756 | static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |
2757 | .master = &am33xx_l4_ls_hwmod, | |
2758 | .slave = &am33xx_mailbox_hwmod, | |
2759 | .clk = "l4ls_gclk", | |
2760 | .addr = am33xx_mailbox_addrs, | |
2761 | .user = OCP_USER_MPU, | |
2762 | }; | |
2763 | ||
2764 | /* l4 ls -> spinlock */ | |
2765 | static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = { | |
2766 | { | |
2767 | .pa_start = 0x480Ca000, | |
2768 | .pa_end = 0x480Ca000 + SZ_4K - 1, | |
2769 | .flags = ADDR_TYPE_RT | |
2770 | }, | |
2771 | { } | |
2772 | }; | |
2773 | ||
2774 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | |
2775 | .master = &am33xx_l4_ls_hwmod, | |
2776 | .slave = &am33xx_spinlock_hwmod, | |
2777 | .clk = "l4ls_gclk", | |
2778 | .addr = am33xx_spinlock_addrs, | |
2779 | .user = OCP_USER_MPU, | |
2780 | }; | |
2781 | ||
2782 | /* l4 ls -> mcasp0 */ | |
2783 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | |
2784 | { | |
2785 | .pa_start = 0x48038000, | |
2786 | .pa_end = 0x48038000 + SZ_8K - 1, | |
2787 | .flags = ADDR_TYPE_RT | |
2788 | }, | |
2789 | { } | |
2790 | }; | |
2791 | ||
2792 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |
2793 | .master = &am33xx_l4_ls_hwmod, | |
2794 | .slave = &am33xx_mcasp0_hwmod, | |
2795 | .clk = "l4ls_gclk", | |
2796 | .addr = am33xx_mcasp0_addr_space, | |
2797 | .user = OCP_USER_MPU, | |
2798 | }; | |
2799 | ||
2800 | /* l3 s -> mcasp0 data */ | |
2801 | static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = { | |
2802 | { | |
2803 | .pa_start = 0x46000000, | |
2804 | .pa_end = 0x46000000 + SZ_4M - 1, | |
2805 | .flags = ADDR_TYPE_RT | |
2806 | }, | |
2807 | { } | |
2808 | }; | |
2809 | ||
2810 | static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = { | |
2811 | .master = &am33xx_l3_s_hwmod, | |
2812 | .slave = &am33xx_mcasp0_hwmod, | |
2813 | .clk = "l3s_gclk", | |
2814 | .addr = am33xx_mcasp0_data_addr_space, | |
2815 | .user = OCP_USER_SDMA, | |
2816 | }; | |
2817 | ||
2818 | /* l4 ls -> mcasp1 */ | |
2819 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | |
2820 | { | |
2821 | .pa_start = 0x4803C000, | |
2822 | .pa_end = 0x4803C000 + SZ_8K - 1, | |
2823 | .flags = ADDR_TYPE_RT | |
2824 | }, | |
2825 | { } | |
2826 | }; | |
2827 | ||
2828 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |
2829 | .master = &am33xx_l4_ls_hwmod, | |
2830 | .slave = &am33xx_mcasp1_hwmod, | |
2831 | .clk = "l4ls_gclk", | |
2832 | .addr = am33xx_mcasp1_addr_space, | |
2833 | .user = OCP_USER_MPU, | |
2834 | }; | |
2835 | ||
2836 | /* l3 s -> mcasp1 data */ | |
2837 | static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = { | |
2838 | { | |
2839 | .pa_start = 0x46400000, | |
2840 | .pa_end = 0x46400000 + SZ_4M - 1, | |
2841 | .flags = ADDR_TYPE_RT | |
2842 | }, | |
2843 | { } | |
2844 | }; | |
2845 | ||
2846 | static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = { | |
2847 | .master = &am33xx_l3_s_hwmod, | |
2848 | .slave = &am33xx_mcasp1_hwmod, | |
2849 | .clk = "l3s_gclk", | |
2850 | .addr = am33xx_mcasp1_data_addr_space, | |
2851 | .user = OCP_USER_SDMA, | |
2852 | }; | |
2853 | ||
2854 | /* l4 ls -> mmc0 */ | |
2855 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | |
2856 | { | |
2857 | .pa_start = 0x48060100, | |
2858 | .pa_end = 0x48060100 + SZ_4K - 1, | |
2859 | .flags = ADDR_TYPE_RT, | |
2860 | }, | |
2861 | { } | |
2862 | }; | |
2863 | ||
2864 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | |
2865 | .master = &am33xx_l4_ls_hwmod, | |
2866 | .slave = &am33xx_mmc0_hwmod, | |
2867 | .clk = "l4ls_gclk", | |
2868 | .addr = am33xx_mmc0_addr_space, | |
2869 | .user = OCP_USER_MPU, | |
2870 | }; | |
2871 | ||
2872 | /* l4 ls -> mmc1 */ | |
2873 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | |
2874 | { | |
2875 | .pa_start = 0x481d8100, | |
2876 | .pa_end = 0x481d8100 + SZ_4K - 1, | |
2877 | .flags = ADDR_TYPE_RT, | |
2878 | }, | |
2879 | { } | |
2880 | }; | |
2881 | ||
2882 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | |
2883 | .master = &am33xx_l4_ls_hwmod, | |
2884 | .slave = &am33xx_mmc1_hwmod, | |
2885 | .clk = "l4ls_gclk", | |
2886 | .addr = am33xx_mmc1_addr_space, | |
2887 | .user = OCP_USER_MPU, | |
2888 | }; | |
2889 | ||
2890 | /* l3 s -> mmc2 */ | |
2891 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | |
2892 | { | |
2893 | .pa_start = 0x47810100, | |
2894 | .pa_end = 0x47810100 + SZ_64K - 1, | |
2895 | .flags = ADDR_TYPE_RT, | |
2896 | }, | |
2897 | { } | |
2898 | }; | |
2899 | ||
2900 | static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |
2901 | .master = &am33xx_l3_s_hwmod, | |
2902 | .slave = &am33xx_mmc2_hwmod, | |
2903 | .clk = "l3s_gclk", | |
2904 | .addr = am33xx_mmc2_addr_space, | |
2905 | .user = OCP_USER_MPU, | |
2906 | }; | |
2907 | ||
2908 | /* l4 ls -> mcspi0 */ | |
2909 | static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { | |
2910 | { | |
2911 | .pa_start = 0x48030000, | |
2912 | .pa_end = 0x48030000 + SZ_1K - 1, | |
2913 | .flags = ADDR_TYPE_RT, | |
2914 | }, | |
2915 | { } | |
2916 | }; | |
2917 | ||
2918 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | |
2919 | .master = &am33xx_l4_ls_hwmod, | |
2920 | .slave = &am33xx_spi0_hwmod, | |
2921 | .clk = "l4ls_gclk", | |
2922 | .addr = am33xx_mcspi0_addr_space, | |
2923 | .user = OCP_USER_MPU, | |
2924 | }; | |
2925 | ||
2926 | /* l4 ls -> mcspi1 */ | |
2927 | static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { | |
2928 | { | |
2929 | .pa_start = 0x481A0000, | |
2930 | .pa_end = 0x481A0000 + SZ_1K - 1, | |
2931 | .flags = ADDR_TYPE_RT, | |
2932 | }, | |
2933 | { } | |
2934 | }; | |
2935 | ||
2936 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | |
2937 | .master = &am33xx_l4_ls_hwmod, | |
2938 | .slave = &am33xx_spi1_hwmod, | |
2939 | .clk = "l4ls_gclk", | |
2940 | .addr = am33xx_mcspi1_addr_space, | |
2941 | .user = OCP_USER_MPU, | |
2942 | }; | |
2943 | ||
2944 | /* l4 wkup -> timer1 */ | |
2945 | static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { | |
2946 | { | |
2947 | .pa_start = 0x44E31000, | |
2948 | .pa_end = 0x44E31000 + SZ_1K - 1, | |
2949 | .flags = ADDR_TYPE_RT | |
2950 | }, | |
2951 | { } | |
2952 | }; | |
2953 | ||
2954 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { | |
2955 | .master = &am33xx_l4_wkup_hwmod, | |
2956 | .slave = &am33xx_timer1_hwmod, | |
2957 | .clk = "dpll_core_m4_div2_ck", | |
2958 | .addr = am33xx_timer1_addr_space, | |
2959 | .user = OCP_USER_MPU, | |
2960 | }; | |
2961 | ||
2962 | /* l4 per -> timer2 */ | |
2963 | static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { | |
2964 | { | |
2965 | .pa_start = 0x48040000, | |
2966 | .pa_end = 0x48040000 + SZ_1K - 1, | |
2967 | .flags = ADDR_TYPE_RT | |
2968 | }, | |
2969 | { } | |
2970 | }; | |
2971 | ||
2972 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | |
2973 | .master = &am33xx_l4_ls_hwmod, | |
2974 | .slave = &am33xx_timer2_hwmod, | |
2975 | .clk = "l4ls_gclk", | |
2976 | .addr = am33xx_timer2_addr_space, | |
2977 | .user = OCP_USER_MPU, | |
2978 | }; | |
2979 | ||
2980 | /* l4 per -> timer3 */ | |
2981 | static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { | |
2982 | { | |
2983 | .pa_start = 0x48042000, | |
2984 | .pa_end = 0x48042000 + SZ_1K - 1, | |
2985 | .flags = ADDR_TYPE_RT | |
2986 | }, | |
2987 | { } | |
2988 | }; | |
2989 | ||
2990 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | |
2991 | .master = &am33xx_l4_ls_hwmod, | |
2992 | .slave = &am33xx_timer3_hwmod, | |
2993 | .clk = "l4ls_gclk", | |
2994 | .addr = am33xx_timer3_addr_space, | |
2995 | .user = OCP_USER_MPU, | |
2996 | }; | |
2997 | ||
2998 | /* l4 per -> timer4 */ | |
2999 | static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { | |
3000 | { | |
3001 | .pa_start = 0x48044000, | |
3002 | .pa_end = 0x48044000 + SZ_1K - 1, | |
3003 | .flags = ADDR_TYPE_RT | |
3004 | }, | |
3005 | { } | |
3006 | }; | |
3007 | ||
3008 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | |
3009 | .master = &am33xx_l4_ls_hwmod, | |
3010 | .slave = &am33xx_timer4_hwmod, | |
3011 | .clk = "l4ls_gclk", | |
3012 | .addr = am33xx_timer4_addr_space, | |
3013 | .user = OCP_USER_MPU, | |
3014 | }; | |
3015 | ||
3016 | /* l4 per -> timer5 */ | |
3017 | static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { | |
3018 | { | |
3019 | .pa_start = 0x48046000, | |
3020 | .pa_end = 0x48046000 + SZ_1K - 1, | |
3021 | .flags = ADDR_TYPE_RT | |
3022 | }, | |
3023 | { } | |
3024 | }; | |
3025 | ||
3026 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | |
3027 | .master = &am33xx_l4_ls_hwmod, | |
3028 | .slave = &am33xx_timer5_hwmod, | |
3029 | .clk = "l4ls_gclk", | |
3030 | .addr = am33xx_timer5_addr_space, | |
3031 | .user = OCP_USER_MPU, | |
3032 | }; | |
3033 | ||
3034 | /* l4 per -> timer6 */ | |
3035 | static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { | |
3036 | { | |
3037 | .pa_start = 0x48048000, | |
3038 | .pa_end = 0x48048000 + SZ_1K - 1, | |
3039 | .flags = ADDR_TYPE_RT | |
3040 | }, | |
3041 | { } | |
3042 | }; | |
3043 | ||
3044 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | |
3045 | .master = &am33xx_l4_ls_hwmod, | |
3046 | .slave = &am33xx_timer6_hwmod, | |
3047 | .clk = "l4ls_gclk", | |
3048 | .addr = am33xx_timer6_addr_space, | |
3049 | .user = OCP_USER_MPU, | |
3050 | }; | |
3051 | ||
3052 | /* l4 per -> timer7 */ | |
3053 | static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { | |
3054 | { | |
3055 | .pa_start = 0x4804A000, | |
3056 | .pa_end = 0x4804A000 + SZ_1K - 1, | |
3057 | .flags = ADDR_TYPE_RT | |
3058 | }, | |
3059 | { } | |
3060 | }; | |
3061 | ||
3062 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | |
3063 | .master = &am33xx_l4_ls_hwmod, | |
3064 | .slave = &am33xx_timer7_hwmod, | |
3065 | .clk = "l4ls_gclk", | |
3066 | .addr = am33xx_timer7_addr_space, | |
3067 | .user = OCP_USER_MPU, | |
3068 | }; | |
3069 | ||
3070 | /* l3 main -> tpcc */ | |
3071 | static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = { | |
3072 | { | |
3073 | .pa_start = 0x49000000, | |
3074 | .pa_end = 0x49000000 + SZ_32K - 1, | |
3075 | .flags = ADDR_TYPE_RT | |
3076 | }, | |
3077 | { } | |
3078 | }; | |
3079 | ||
3080 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | |
3081 | .master = &am33xx_l3_main_hwmod, | |
3082 | .slave = &am33xx_tpcc_hwmod, | |
3083 | .clk = "l3_gclk", | |
3084 | .addr = am33xx_tpcc_addr_space, | |
3085 | .user = OCP_USER_MPU, | |
3086 | }; | |
3087 | ||
3088 | /* l3 main -> tpcc0 */ | |
3089 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | |
3090 | { | |
3091 | .pa_start = 0x49800000, | |
3092 | .pa_end = 0x49800000 + SZ_8K - 1, | |
3093 | .flags = ADDR_TYPE_RT, | |
3094 | }, | |
3095 | { } | |
3096 | }; | |
3097 | ||
3098 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | |
3099 | .master = &am33xx_l3_main_hwmod, | |
3100 | .slave = &am33xx_tptc0_hwmod, | |
3101 | .clk = "l3_gclk", | |
3102 | .addr = am33xx_tptc0_addr_space, | |
3103 | .user = OCP_USER_MPU, | |
3104 | }; | |
3105 | ||
3106 | /* l3 main -> tpcc1 */ | |
3107 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | |
3108 | { | |
3109 | .pa_start = 0x49900000, | |
3110 | .pa_end = 0x49900000 + SZ_8K - 1, | |
3111 | .flags = ADDR_TYPE_RT, | |
3112 | }, | |
3113 | { } | |
3114 | }; | |
3115 | ||
3116 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | |
3117 | .master = &am33xx_l3_main_hwmod, | |
3118 | .slave = &am33xx_tptc1_hwmod, | |
3119 | .clk = "l3_gclk", | |
3120 | .addr = am33xx_tptc1_addr_space, | |
3121 | .user = OCP_USER_MPU, | |
3122 | }; | |
3123 | ||
3124 | /* l3 main -> tpcc2 */ | |
3125 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | |
3126 | { | |
3127 | .pa_start = 0x49a00000, | |
3128 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
3129 | .flags = ADDR_TYPE_RT, | |
3130 | }, | |
3131 | { } | |
3132 | }; | |
3133 | ||
3134 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |
3135 | .master = &am33xx_l3_main_hwmod, | |
3136 | .slave = &am33xx_tptc2_hwmod, | |
3137 | .clk = "l3_gclk", | |
3138 | .addr = am33xx_tptc2_addr_space, | |
3139 | .user = OCP_USER_MPU, | |
3140 | }; | |
3141 | ||
3142 | /* l4 wkup -> uart1 */ | |
3143 | static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { | |
3144 | { | |
3145 | .pa_start = 0x44E09000, | |
3146 | .pa_end = 0x44E09000 + SZ_8K - 1, | |
3147 | .flags = ADDR_TYPE_RT, | |
3148 | }, | |
3149 | { } | |
3150 | }; | |
3151 | ||
3152 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { | |
3153 | .master = &am33xx_l4_wkup_hwmod, | |
3154 | .slave = &am33xx_uart1_hwmod, | |
3155 | .clk = "dpll_core_m4_div2_ck", | |
3156 | .addr = am33xx_uart1_addr_space, | |
3157 | .user = OCP_USER_MPU, | |
3158 | }; | |
3159 | ||
3160 | /* l4 ls -> uart2 */ | |
3161 | static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { | |
3162 | { | |
3163 | .pa_start = 0x48022000, | |
3164 | .pa_end = 0x48022000 + SZ_8K - 1, | |
3165 | .flags = ADDR_TYPE_RT, | |
3166 | }, | |
3167 | { } | |
3168 | }; | |
3169 | ||
3170 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | |
3171 | .master = &am33xx_l4_ls_hwmod, | |
3172 | .slave = &am33xx_uart2_hwmod, | |
3173 | .clk = "l4ls_gclk", | |
3174 | .addr = am33xx_uart2_addr_space, | |
3175 | .user = OCP_USER_MPU, | |
3176 | }; | |
3177 | ||
3178 | /* l4 ls -> uart3 */ | |
3179 | static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { | |
3180 | { | |
3181 | .pa_start = 0x48024000, | |
3182 | .pa_end = 0x48024000 + SZ_8K - 1, | |
3183 | .flags = ADDR_TYPE_RT, | |
3184 | }, | |
3185 | { } | |
3186 | }; | |
3187 | ||
3188 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | |
3189 | .master = &am33xx_l4_ls_hwmod, | |
3190 | .slave = &am33xx_uart3_hwmod, | |
3191 | .clk = "l4ls_gclk", | |
3192 | .addr = am33xx_uart3_addr_space, | |
3193 | .user = OCP_USER_MPU, | |
3194 | }; | |
3195 | ||
3196 | /* l4 ls -> uart4 */ | |
3197 | static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { | |
3198 | { | |
3199 | .pa_start = 0x481A6000, | |
3200 | .pa_end = 0x481A6000 + SZ_8K - 1, | |
3201 | .flags = ADDR_TYPE_RT, | |
3202 | }, | |
3203 | { } | |
3204 | }; | |
3205 | ||
3206 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | |
3207 | .master = &am33xx_l4_ls_hwmod, | |
3208 | .slave = &am33xx_uart4_hwmod, | |
3209 | .clk = "l4ls_gclk", | |
3210 | .addr = am33xx_uart4_addr_space, | |
3211 | .user = OCP_USER_MPU, | |
3212 | }; | |
3213 | ||
3214 | /* l4 ls -> uart5 */ | |
3215 | static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { | |
3216 | { | |
3217 | .pa_start = 0x481A8000, | |
3218 | .pa_end = 0x481A8000 + SZ_8K - 1, | |
3219 | .flags = ADDR_TYPE_RT, | |
3220 | }, | |
3221 | { } | |
3222 | }; | |
3223 | ||
3224 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | |
3225 | .master = &am33xx_l4_ls_hwmod, | |
3226 | .slave = &am33xx_uart5_hwmod, | |
3227 | .clk = "l4ls_gclk", | |
3228 | .addr = am33xx_uart5_addr_space, | |
3229 | .user = OCP_USER_MPU, | |
3230 | }; | |
3231 | ||
3232 | /* l4 ls -> uart6 */ | |
3233 | static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { | |
3234 | { | |
3235 | .pa_start = 0x481aa000, | |
3236 | .pa_end = 0x481aa000 + SZ_8K - 1, | |
3237 | .flags = ADDR_TYPE_RT, | |
3238 | }, | |
3239 | { } | |
3240 | }; | |
3241 | ||
3242 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | |
3243 | .master = &am33xx_l4_ls_hwmod, | |
3244 | .slave = &am33xx_uart6_hwmod, | |
3245 | .clk = "l4ls_gclk", | |
3246 | .addr = am33xx_uart6_addr_space, | |
3247 | .user = OCP_USER_MPU, | |
3248 | }; | |
3249 | ||
3250 | /* l4 wkup -> wd_timer1 */ | |
3251 | static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { | |
3252 | { | |
3253 | .pa_start = 0x44e35000, | |
3254 | .pa_end = 0x44e35000 + SZ_4K - 1, | |
3255 | .flags = ADDR_TYPE_RT | |
3256 | }, | |
3257 | { } | |
3258 | }; | |
3259 | ||
3260 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { | |
3261 | .master = &am33xx_l4_wkup_hwmod, | |
3262 | .slave = &am33xx_wd_timer1_hwmod, | |
3263 | .clk = "dpll_core_m4_div2_ck", | |
3264 | .addr = am33xx_wd_timer1_addrs, | |
3265 | .user = OCP_USER_MPU, | |
3266 | }; | |
3267 | ||
3268 | /* usbss */ | |
3269 | /* l3 s -> USBSS interface */ | |
3270 | static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { | |
3271 | { | |
3272 | .name = "usbss", | |
3273 | .pa_start = 0x47400000, | |
3274 | .pa_end = 0x47400000 + SZ_4K - 1, | |
3275 | .flags = ADDR_TYPE_RT | |
3276 | }, | |
3277 | { | |
3278 | .name = "musb0", | |
3279 | .pa_start = 0x47401000, | |
3280 | .pa_end = 0x47401000 + SZ_2K - 1, | |
3281 | .flags = ADDR_TYPE_RT | |
3282 | }, | |
3283 | { | |
3284 | .name = "musb1", | |
3285 | .pa_start = 0x47401800, | |
3286 | .pa_end = 0x47401800 + SZ_2K - 1, | |
3287 | .flags = ADDR_TYPE_RT | |
3288 | }, | |
3289 | { } | |
3290 | }; | |
3291 | ||
3292 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { | |
3293 | .master = &am33xx_l3_s_hwmod, | |
3294 | .slave = &am33xx_usbss_hwmod, | |
3295 | .clk = "l3s_gclk", | |
3296 | .addr = am33xx_usbss_addr_space, | |
3297 | .user = OCP_USER_MPU, | |
3298 | .flags = OCPIF_SWSUP_IDLE, | |
3299 | }; | |
3300 | ||
3301 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | |
3302 | &am33xx_l4_fw__emif_fw, | |
3303 | &am33xx_l3_main__emif, | |
3304 | &am33xx_mpu__l3_main, | |
3305 | &am33xx_mpu__prcm, | |
3306 | &am33xx_l3_s__l4_ls, | |
3307 | &am33xx_l3_s__l4_wkup, | |
3308 | &am33xx_l3_s__l4_fw, | |
3309 | &am33xx_l3_main__l4_hs, | |
3310 | &am33xx_l3_main__l3_s, | |
3311 | &am33xx_l3_main__l3_instr, | |
3312 | &am33xx_l3_main__gfx, | |
3313 | &am33xx_l3_s__l3_main, | |
3314 | &am33xx_pruss__l3_main, | |
3315 | &am33xx_wkup_m3__l4_wkup, | |
3316 | &am33xx_gfx__l3_main, | |
3317 | &am33xx_l4_wkup__wkup_m3, | |
3318 | &am33xx_l4_wkup__control, | |
3319 | &am33xx_l4_wkup__smartreflex0, | |
3320 | &am33xx_l4_wkup__smartreflex1, | |
3321 | &am33xx_l4_wkup__uart1, | |
3322 | &am33xx_l4_wkup__timer1, | |
3323 | &am33xx_l4_wkup__rtc, | |
3324 | &am33xx_l4_wkup__i2c1, | |
3325 | &am33xx_l4_wkup__gpio0, | |
3326 | &am33xx_l4_wkup__adc_tsc, | |
3327 | &am33xx_l4_wkup__wd_timer1, | |
3328 | &am33xx_l4_hs__pruss, | |
3329 | &am33xx_l4_per__dcan0, | |
3330 | &am33xx_l4_per__dcan1, | |
3331 | &am33xx_l4_per__gpio1, | |
3332 | &am33xx_l4_per__gpio2, | |
3333 | &am33xx_l4_per__gpio3, | |
3334 | &am33xx_l4_per__i2c2, | |
3335 | &am33xx_l4_per__i2c3, | |
3336 | &am33xx_l4_per__mailbox, | |
3337 | &am33xx_l4_ls__mcasp0, | |
3338 | &am33xx_l3_s__mcasp0_data, | |
3339 | &am33xx_l4_ls__mcasp1, | |
3340 | &am33xx_l3_s__mcasp1_data, | |
3341 | &am33xx_l4_ls__mmc0, | |
3342 | &am33xx_l4_ls__mmc1, | |
3343 | &am33xx_l3_s__mmc2, | |
3344 | &am33xx_l4_ls__timer2, | |
3345 | &am33xx_l4_ls__timer3, | |
3346 | &am33xx_l4_ls__timer4, | |
3347 | &am33xx_l4_ls__timer5, | |
3348 | &am33xx_l4_ls__timer6, | |
3349 | &am33xx_l4_ls__timer7, | |
3350 | &am33xx_l3_main__tpcc, | |
3351 | &am33xx_l4_ls__uart2, | |
3352 | &am33xx_l4_ls__uart3, | |
3353 | &am33xx_l4_ls__uart4, | |
3354 | &am33xx_l4_ls__uart5, | |
3355 | &am33xx_l4_ls__uart6, | |
3356 | &am33xx_l4_ls__spinlock, | |
3357 | &am33xx_l4_ls__elm, | |
3358 | &am33xx_l4_ls__ehrpwm0, | |
3359 | &am33xx_l4_ls__ehrpwm1, | |
3360 | &am33xx_l4_ls__ehrpwm2, | |
3361 | &am33xx_l4_ls__ecap0, | |
3362 | &am33xx_l4_ls__ecap1, | |
3363 | &am33xx_l4_ls__ecap2, | |
3364 | &am33xx_l3_s__gpmc, | |
3365 | &am33xx_l3_main__lcdc, | |
3366 | &am33xx_l4_ls__mcspi0, | |
3367 | &am33xx_l4_ls__mcspi1, | |
3368 | &am33xx_l3_main__tptc0, | |
3369 | &am33xx_l3_main__tptc1, | |
3370 | &am33xx_l3_main__tptc2, | |
3371 | &am33xx_l3_s__usbss, | |
3372 | &am33xx_l4_hs__cpgmac0, | |
3373 | NULL, | |
3374 | }; | |
3375 | ||
3376 | int __init am33xx_hwmod_init(void) | |
3377 | { | |
3378 | omap_hwmod_init(); | |
3379 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); | |
3380 | } |