[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c

/*
 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
 *
 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is automatically generated from the AM33XX hardware databases.
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"

#include "control.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
#include "wd_timer.h"
#include "omap_hwmod_33xx_43xx_common_data.h"

/*
 * IP blocks
 */

/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
	.name		= "emif",
	.class		= &am33xx_emif_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "dpll_ddr_m2_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* l4_hs */
static struct omap_hwmod am33xx_l4_hs_hwmod = {
	.name		= "l4_hs",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4hs_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "l4hs_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};

/* wkup_m3  */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
	.name		= "wkup_m3",
	.class		= &am33xx_wkup_m3_hwmod_class,
	.clkdm_name	= "l4_wkup_aon_clkdm",
	/* Keep hardreset asserted */
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
			.rstst_offs	= AM33XX_RM_WKUP_RSTST_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_wkup_m3_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
};

/*
 * 'adc/tsc' class
 * TouchScreen Controller (Anolog-To-Digital Converter)
 */
static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x10,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
	.name		= "adc_tsc",
	.sysc		= &am33xx_adc_tsc_sysc,
};

static struct omap_hwmod am33xx_adc_tsc_hwmod = {
	.name		= "adc_tsc",
	.class		= &am33xx_adc_tsc_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.main_clk	= "adc_tsc_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *    - cEFUSE (doesn't fall under any ocp_if)
 *    - clkdiv32k
 *    - ocp watch point
 */
#if 0
/*
 * 'cefuse' class
 */
static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
	.name		= "cefuse",
};

static struct omap_hwmod am33xx_cefuse_hwmod = {
	.name		= "cefuse",
	.class		= &am33xx_cefuse_hwmod_class,
	.clkdm_name	= "l4_cefuse_clkdm",
	.main_clk	= "cefuse_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'clkdiv32k' class
 */
static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
	.name		= "clkdiv32k",
};

static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
	.name		= "clkdiv32k",
	.class		= &am33xx_clkdiv32k_hwmod_class,
	.clkdm_name	= "clk_24mhz_clkdm",
	.main_clk	= "clkdiv32k_ick",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
	.name		= "ocpwp",
};

static struct omap_hwmod am33xx_ocpwp_hwmod = {
	.name		= "ocpwp",
	.class		= &am33xx_ocpwp_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};
#endif

/*
 * 'debugss' class
 * debug sub system
 */
static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
	{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
	{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
};

static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
	.name		= "debugss",
};

static struct omap_hwmod am33xx_debugss_hwmod = {
	.name		= "debugss",
	.class		= &am33xx_debugss_hwmod_class,
	.clkdm_name	= "l3_aon_clkdm",
	.main_clk	= "trace_clk_div_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= debugss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(debugss_opt_clks),
};

static struct omap_hwmod am33xx_control_hwmod = {
	.name		= "control",
	.class		= &am33xx_control_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* lcdc */
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x54,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
	.name		= "lcdc",
	.sysc		= &lcdc_sysc,
};

static struct omap_hwmod am33xx_lcdc_hwmod = {
	.name		= "lcdc",
	.class		= &am33xx_lcdc_hwmod_class,
	.clkdm_name	= "lcdc_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.main_clk	= "lcd_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'usb_otg' class
 * high-speed on-the-go universal serial bus (usb_otg) controller
 */
static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_usbotg_class = {
	.name		= "usbotg",
	.sysc		= &am33xx_usbhsotg_sysc,
};

static struct omap_hwmod am33xx_usbss_hwmod = {
	.name		= "usb_otg_hs",
	.class		= &am33xx_usbotg_class,
	.clkdm_name	= "l3s_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.main_clk	= "usbotg_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};


/*
 * Interfaces
 */

/* l3 main -> emif */
static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_emif_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3 main -> l4 hs */
static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_l4_hs_hwmod,
	.clk		= "l3s_gclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* wkup m3 -> l4 wkup */
static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
	.master		= &am33xx_wkup_m3_hwmod,
	.slave		= &am33xx_l4_wkup_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 wkup -> wkup m3 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_wkup_m3_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 hs -> pru-icss */
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
	.master		= &am33xx_l4_hs_hwmod,
	.slave		= &am33xx_pruss_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main -> debugss */
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_debugss_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> smartreflex0 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex0_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> smartreflex1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> control */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_control_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* L4 WKUP -> ADC_TSC */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_adc_tsc_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
	.master		= &am33xx_l4_hs_hwmod,
	.slave		= &am33xx_cpgmac0_hwmod,
	.clk		= "cpsw_125mhz_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_lcdc_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_timer1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> wd_timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_wd_timer1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* usbss */
/* l3 s -> USBSS interface */
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
	.master		= &am33xx_l3_s_hwmod,
	.slave		= &am33xx_usbss_hwmod,
	.clk		= "l3s_gclk",
	.user		= OCP_USER_MPU,
	.flags		= OCPIF_SWSUP_IDLE,
};

static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
	&am33xx_l3_main__emif,
	&am33xx_mpu__l3_main,
	&am33xx_mpu__prcm,
	&am33xx_l3_s__l4_ls,
	&am33xx_l3_s__l4_wkup,
	&am33xx_l3_main__l4_hs,
	&am33xx_l3_main__l3_s,
	&am33xx_l3_main__l3_instr,
	&am33xx_l3_main__gfx,
	&am33xx_l3_s__l3_main,
	&am33xx_pruss__l3_main,
	&am33xx_wkup_m3__l4_wkup,
	&am33xx_gfx__l3_main,
	&am33xx_l3_main__debugss,
	&am33xx_l4_wkup__wkup_m3,
	&am33xx_l4_wkup__control,
	&am33xx_l4_wkup__smartreflex0,
	&am33xx_l4_wkup__smartreflex1,
	&am33xx_l4_wkup__timer1,
	&am33xx_l4_wkup__rtc,
	&am33xx_l4_wkup__adc_tsc,
	&am33xx_l4_wkup__wd_timer1,
	&am33xx_l4_hs__pruss,
	&am33xx_l4_per__dcan0,
	&am33xx_l4_per__dcan1,
	&am33xx_l4_per__mailbox,
	&am33xx_l4_ls__mcasp0,
	&am33xx_l4_ls__mcasp1,
	&am33xx_l4_ls__timer2,
	&am33xx_l4_ls__timer3,
	&am33xx_l4_ls__timer4,
	&am33xx_l4_ls__timer5,
	&am33xx_l4_ls__timer6,
	&am33xx_l4_ls__timer7,
	&am33xx_l3_main__tpcc,
	&am33xx_l4_ls__spinlock,
	&am33xx_l4_ls__elm,
	&am33xx_l4_ls__epwmss0,
	&am33xx_l4_ls__epwmss1,
	&am33xx_l4_ls__epwmss2,
	&am33xx_l3_s__gpmc,
	&am33xx_l3_main__lcdc,
	&am33xx_l4_ls__mcspi0,
	&am33xx_l4_ls__mcspi1,
	&am33xx_l3_main__tptc0,
	&am33xx_l3_main__tptc1,
	&am33xx_l3_main__tptc2,
	&am33xx_l3_main__ocmc,
	&am33xx_l3_s__usbss,
	&am33xx_l4_hs__cpgmac0,
	&am33xx_cpgmac0__mdio,
	&am33xx_l3_main__sha0,
	&am33xx_l3_main__aes0,
	&am33xx_l4_per__rng,
	NULL,
};

int __init am33xx_hwmod_init(void)
{
	omap_hwmod_am33xx_reg();
	omap_hwmod_init();
	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
}
Commit	Line	Data
a2cfc509 VH	1	/*
	2	* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
	3	*
	4	* Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is automatically generated from the AM33XX hardware databases.
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
2a296c8f	17	#include "omap_hwmod.h"
a2cfc509 VH	18	#include "omap_hwmod_common_data.h"
	19
	20	#include "control.h"
	21	#include "cm33xx.h"
	22	#include "prm33xx.h"
	23	#include "prm-regbits-33xx.h"
05cf03b6	24	#include "wd_timer.h"
26649467	25	#include "omap_hwmod_33xx_43xx_common_data.h"
a2cfc509	26
a2cfc509 VH	27	/*
	28	* IP blocks
	29	*/
	30
a2cfc509 VH	31	/* emif */
	32	static struct omap_hwmod am33xx_emif_hwmod = {
	33	.name = "emif",
	34	.class = &am33xx_emif_hwmod_class,
	35	.clkdm_name = "l3_clkdm",
b2eb0002	36	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	37	.main_clk = "dpll_ddr_m2_div2_ck",
	38	.prcm = {
	39	.omap4 = {
	40	.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
	41	.modulemode = MODULEMODE_SWCTRL,
	42	},
	43	},
	44	};
	45
a2cfc509 VH	46	/* l4_hs */
	47	static struct omap_hwmod am33xx_l4_hs_hwmod = {
	48	.name = "l4_hs",
	49	.class = &am33xx_l4_hwmod_class,
	50	.clkdm_name = "l4hs_clkdm",
b2eb0002	51	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	52	.main_clk = "l4hs_gclk",
	53	.prcm = {
	54	.omap4 = {
	55	.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
	56	.modulemode = MODULEMODE_SWCTRL,
	57	},
	58	},
	59	};
	60
a2cfc509 VH	61	static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	62	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
	63	};
	64
a2cfc509 VH	65	/* wkup_m3 */
	66	static struct omap_hwmod am33xx_wkup_m3_hwmod = {
	67	.name = "wkup_m3",
	68	.class = &am33xx_wkup_m3_hwmod_class,
	69	.clkdm_name = "l4_wkup_aon_clkdm",
092bda62 HG	70	/* Keep hardreset asserted */
092bda62 HG	71	.flags = HWMOD_INIT_NO_RESET \| HWMOD_NO_IDLEST,
a2cfc509 VH	72	.main_clk = "dpll_core_m4_div2_ck",
	73	.prcm = {
	74	.omap4 = {
	75	.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
	76	.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
3077fe69	77	.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
a2cfc509 VH	78	.modulemode = MODULEMODE_SWCTRL,
	79	},
	80	},
	81	.rst_lines = am33xx_wkup_m3_resets,
	82	.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
	83	};
	84
a2cfc509 VH	85	/*
	86	* 'adc/tsc' class
	87	* TouchScreen Controller (Anolog-To-Digital Converter)
	88	*/
	89	static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
	90	.rev_offs = 0x00,
	91	.sysc_offs = 0x10,
	92	.sysc_flags = SYSC_HAS_SIDLEMODE,
	93	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	94	SIDLE_SMART_WKUP),
	95	.sysc_fields = &omap_hwmod_sysc_type2,
	96	};
	97
	98	static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
	99	.name = "adc_tsc",
	100	.sysc = &am33xx_adc_tsc_sysc,
	101	};
	102
a2cfc509 VH	103	static struct omap_hwmod am33xx_adc_tsc_hwmod = {
	104	.name = "adc_tsc",
	105	.class = &am33xx_adc_tsc_hwmod_class,
	106	.clkdm_name = "l4_wkup_clkdm",
a2cfc509 VH	107	.main_clk = "adc_tsc_fck",
	108	.prcm = {
	109	.omap4 = {
	110	.clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
	111	.modulemode = MODULEMODE_SWCTRL,
	112	},
	113	},
	114	};
	115
	116	/*
	117	* Modules omap_hwmod structures
	118	*
	119	* The following IPs are excluded for the moment because:
	120	* - They do not need an explicit SW control using omap_hwmod API.
	121	* - They still need to be validated with the driver
	122	* properly adapted to omap_hwmod / omap_device
	123	*
	124	* - cEFUSE (doesn't fall under any ocp_if)
	125	* - clkdiv32k
a2cfc509	126	* - ocp watch point
a2cfc509 VH	127	*/
	128	#if 0
	129	/*
	130	* 'cefuse' class
	131	*/
	132	static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
	133	.name = "cefuse",
	134	};
	135
	136	static struct omap_hwmod am33xx_cefuse_hwmod = {
	137	.name = "cefuse",
	138	.class = &am33xx_cefuse_hwmod_class,
	139	.clkdm_name = "l4_cefuse_clkdm",
	140	.main_clk = "cefuse_fck",
	141	.prcm = {
	142	.omap4 = {
	143	.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
	144	.modulemode = MODULEMODE_SWCTRL,
	145	},
	146	},
	147	};
	148
	149	/*
	150	* 'clkdiv32k' class
	151	*/
	152	static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
	153	.name = "clkdiv32k",
	154	};
	155
	156	static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
	157	.name = "clkdiv32k",
	158	.class = &am33xx_clkdiv32k_hwmod_class,
	159	.clkdm_name = "clk_24mhz_clkdm",
	160	.main_clk = "clkdiv32k_ick",
	161	.prcm = {
	162	.omap4 = {
	163	.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
	164	.modulemode = MODULEMODE_SWCTRL,
	165	},
	166	},
	167	};
	168
a2cfc509 VH	169	/* ocpwp */
	170	static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
	171	.name = "ocpwp",
	172	};
	173
	174	static struct omap_hwmod am33xx_ocpwp_hwmod = {
	175	.name = "ocpwp",
	176	.class = &am33xx_ocpwp_hwmod_class,
	177	.clkdm_name = "l4ls_clkdm",
	178	.main_clk = "l4ls_gclk",
	179	.prcm = {
	180	.omap4 = {
	181	.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
	182	.modulemode = MODULEMODE_SWCTRL,
	183	},
	184	},
	185	};
1cb804b9	186	#endif
a2cfc509	187
1721c702 VH	188	/*
	189	* 'debugss' class
	190	* debug sub system
	191	*/
	192	static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
	193	{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
	194	{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
	195	};
	196
	197	static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
	198	.name = "debugss",
	199	};
	200
	201	static struct omap_hwmod am33xx_debugss_hwmod = {
	202	.name = "debugss",
	203	.class = &am33xx_debugss_hwmod_class,
	204	.clkdm_name = "l3_aon_clkdm",
	205	.main_clk = "trace_clk_div_ck",
	206	.prcm = {
	207	.omap4 = {
	208	.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
	209	.modulemode = MODULEMODE_SWCTRL,
	210	},
	211	},
	212	.opt_clks = debugss_opt_clks,
	213	.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
	214	};
	215
a2cfc509 VH	216	static struct omap_hwmod am33xx_control_hwmod = {
	217	.name = "control",
	218	.class = &am33xx_control_hwmod_class,
	219	.clkdm_name = "l4_wkup_clkdm",
b2eb0002	220	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	221	.main_clk = "dpll_core_m4_div2_ck",
	222	.prcm = {
	223	.omap4 = {
	224	.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
	225	.modulemode = MODULEMODE_SWCTRL,
	226	},
	227	},
	228	};
	229
26649467 AM	230	/* lcdc */
	231	static struct omap_hwmod_class_sysconfig lcdc_sysc = {
	232	.rev_offs = 0x0,
	233	.sysc_offs = 0x54,
	234	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE),
a2cfc509	235	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
26649467	236	.sysc_fields = &omap_hwmod_sysc_type2,
a2cfc509 VH	237	};
a2cfc509 VH	238
26649467 AM	239	static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
	240	.name = "lcdc",
	241	.sysc = &lcdc_sysc,
a2cfc509 VH	242	};
a2cfc509 VH	243
26649467 AM	244	static struct omap_hwmod am33xx_lcdc_hwmod = {
	245	.name = "lcdc",
	246	.class = &am33xx_lcdc_hwmod_class,
	247	.clkdm_name = "lcdc_clkdm",
	248	.flags = HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY,
	249	.main_clk = "lcd_gclk",
a2cfc509 VH	250	.prcm = {
a2cfc509 VH	251	.omap4 = {
26649467	252	.clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
a2cfc509 VH	253	.modulemode = MODULEMODE_SWCTRL,
	254	},
	255	},
	256	};
	257
26649467 AM	258	/*
	259	* 'usb_otg' class
	260	* high-speed on-the-go universal serial bus (usb_otg) controller
	261	*/
	262	static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
a2cfc509	263	.rev_offs = 0x0,
26649467	264	.sysc_offs = 0x10,
a2cfc509 VH	265	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE),
a2cfc509 VH	266	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
26649467	267	MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
a2cfc509 VH	268	.sysc_fields = &omap_hwmod_sysc_type2,
	269	};
	270
26649467 AM	271	static struct omap_hwmod_class am33xx_usbotg_class = {
	272	.name = "usbotg",
	273	.sysc = &am33xx_usbhsotg_sysc,
a2cfc509 VH	274	};
a2cfc509 VH	275
26649467 AM	276	static struct omap_hwmod am33xx_usbss_hwmod = {
	277	.name = "usb_otg_hs",
	278	.class = &am33xx_usbotg_class,
	279	.clkdm_name = "l3s_clkdm",
	280	.flags = HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY,
	281	.main_clk = "usbotg_fck",
a2cfc509 VH	282	.prcm = {
a2cfc509 VH	283	.omap4 = {
26649467	284	.clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
a2cfc509 VH	285	.modulemode = MODULEMODE_SWCTRL,
	286	},
	287	},
	288	};
	289
bee76659	290
26649467 AM	291	/*
	292	* Interfaces
	293	*/
a2cfc509	294
26649467 AM	295	/* l3 main -> emif */
	296	static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
	297	.master = &am33xx_l3_main_hwmod,
	298	.slave = &am33xx_emif_hwmod,
	299	.clk = "dpll_core_m4_ck",
26649467	300	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	301	};
a2cfc509 VH	302
26649467 AM	303	/* l3 main -> l4 hs */
	304	static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
	305	.master = &am33xx_l3_main_hwmod,
	306	.slave = &am33xx_l4_hs_hwmod,
	307	.clk = "l3s_gclk",
	308	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	309	};
a2cfc509 VH	310
26649467 AM	311	/* wkup m3 -> l4 wkup */
	312	static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
	313	.master = &am33xx_wkup_m3_hwmod,
	314	.slave = &am33xx_l4_wkup_hwmod,
	315	.clk = "dpll_core_m4_div2_ck",
	316	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	317	};
a2cfc509 VH	318
26649467 AM	319	/* l4 wkup -> wkup m3 */
	320	static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
	321	.master = &am33xx_l4_wkup_hwmod,
	322	.slave = &am33xx_wkup_m3_hwmod,
	323	.clk = "dpll_core_m4_div2_ck",
	324	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	325	};
a2cfc509 VH	326
26649467 AM	327	/* l4 hs -> pru-icss */
	328	static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
	329	.master = &am33xx_l4_hs_hwmod,
	330	.slave = &am33xx_pruss_hwmod,
a2cfc509	331	.clk = "dpll_core_m4_ck",
26649467	332	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	333	};
a2cfc509 VH	334
26649467	335	/* l3_main -> debugss */
26649467 AM	336	static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
	337	.master = &am33xx_l3_main_hwmod,
	338	.slave = &am33xx_debugss_hwmod,
	339	.clk = "dpll_core_m4_ck",
a2cfc509 VH	340	.user = OCP_USER_MPU,
	341	};
	342
26649467 AM	343	/* l4 wkup -> smartreflex0 */
	344	static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
	345	.master = &am33xx_l4_wkup_hwmod,
	346	.slave = &am33xx_smartreflex0_hwmod,
	347	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	348	.user = OCP_USER_MPU,
	349	};
	350
26649467 AM	351	/* l4 wkup -> smartreflex1 */
	352	static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
	353	.master = &am33xx_l4_wkup_hwmod,
	354	.slave = &am33xx_smartreflex1_hwmod,
	355	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	356	.user = OCP_USER_MPU,
	357	};
	358
26649467 AM	359	/* l4 wkup -> control */
	360	static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
	361	.master = &am33xx_l4_wkup_hwmod,
	362	.slave = &am33xx_control_hwmod,
	363	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	364	.user = OCP_USER_MPU,
	365	};
	366
26649467	367	/* L4 WKUP -> ADC_TSC */
26649467	368	static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
a2cfc509	369	.master = &am33xx_l4_wkup_hwmod,
26649467	370	.slave = &am33xx_adc_tsc_hwmod,
a2cfc509	371	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	372	.user = OCP_USER_MPU,
	373	};
	374
26649467 AM	375	static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
	376	.master = &am33xx_l4_hs_hwmod,
	377	.slave = &am33xx_cpgmac0_hwmod,
	378	.clk = "cpsw_125mhz_gclk",
a2cfc509 VH	379	.user = OCP_USER_MPU,
	380	};
	381
26649467	382	static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
a2cfc509	383	.master = &am33xx_l3_main_hwmod,
26649467 AM	384	.slave = &am33xx_lcdc_hwmod,
26649467 AM	385	.clk = "dpll_core_m4_ck",
a2cfc509 VH	386	.user = OCP_USER_MPU,
	387	};
	388
26649467 AM	389	/* l4 wkup -> timer1 */
	390	static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
	391	.master = &am33xx_l4_wkup_hwmod,
	392	.slave = &am33xx_timer1_hwmod,
	393	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	394	.user = OCP_USER_MPU,
	395	};
	396
a2cfc509	397	/* l4 wkup -> wd_timer1 */
a2cfc509 VH	398	static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
	399	.master = &am33xx_l4_wkup_hwmod,
	400	.slave = &am33xx_wd_timer1_hwmod,
	401	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	402	.user = OCP_USER_MPU,
	403	};
	404
	405	/* usbss */
	406	/* l3 s -> USBSS interface */
a2cfc509 VH	407	static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
	408	.master = &am33xx_l3_s_hwmod,
	409	.slave = &am33xx_usbss_hwmod,
	410	.clk = "l3s_gclk",
a2cfc509 VH	411	.user = OCP_USER_MPU,
	412	.flags = OCPIF_SWSUP_IDLE,
	413	};
	414
	415	static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
a2cfc509 VH	416	&am33xx_l3_main__emif,
	417	&am33xx_mpu__l3_main,
	418	&am33xx_mpu__prcm,
	419	&am33xx_l3_s__l4_ls,
	420	&am33xx_l3_s__l4_wkup,
a2cfc509 VH	421	&am33xx_l3_main__l4_hs,
	422	&am33xx_l3_main__l3_s,
	423	&am33xx_l3_main__l3_instr,
	424	&am33xx_l3_main__gfx,
	425	&am33xx_l3_s__l3_main,
	426	&am33xx_pruss__l3_main,
	427	&am33xx_wkup_m3__l4_wkup,
	428	&am33xx_gfx__l3_main,
1721c702	429	&am33xx_l3_main__debugss,
a2cfc509 VH	430	&am33xx_l4_wkup__wkup_m3,
	431	&am33xx_l4_wkup__control,
	432	&am33xx_l4_wkup__smartreflex0,
	433	&am33xx_l4_wkup__smartreflex1,
a2cfc509 VH	434	&am33xx_l4_wkup__timer1,
a2cfc509 VH	435	&am33xx_l4_wkup__rtc,
a2cfc509 VH	436	&am33xx_l4_wkup__adc_tsc,
	437	&am33xx_l4_wkup__wd_timer1,
	438	&am33xx_l4_hs__pruss,
	439	&am33xx_l4_per__dcan0,
	440	&am33xx_l4_per__dcan1,
a2cfc509 VH	441	&am33xx_l4_per__mailbox,
a2cfc509 VH	442	&am33xx_l4_ls__mcasp0,
a2cfc509	443	&am33xx_l4_ls__mcasp1,
a2cfc509 VH	444	&am33xx_l4_ls__timer2,
	445	&am33xx_l4_ls__timer3,
	446	&am33xx_l4_ls__timer4,
	447	&am33xx_l4_ls__timer5,
	448	&am33xx_l4_ls__timer6,
	449	&am33xx_l4_ls__timer7,
	450	&am33xx_l3_main__tpcc,
a2cfc509 VH	451	&am33xx_l4_ls__spinlock,
a2cfc509 VH	452	&am33xx_l4_ls__elm,
9652d19a	453	&am33xx_l4_ls__epwmss0,
9652d19a	454	&am33xx_l4_ls__epwmss1,
9652d19a	455	&am33xx_l4_ls__epwmss2,
a2cfc509 VH	456	&am33xx_l3_s__gpmc,
	457	&am33xx_l3_main__lcdc,
	458	&am33xx_l4_ls__mcspi0,
	459	&am33xx_l4_ls__mcspi1,
	460	&am33xx_l3_main__tptc0,
	461	&am33xx_l3_main__tptc1,
	462	&am33xx_l3_main__tptc2,
ca903b6f	463	&am33xx_l3_main__ocmc,
a2cfc509 VH	464	&am33xx_l3_s__usbss,
a2cfc509 VH	465	&am33xx_l4_hs__cpgmac0,
70384a6a	466	&am33xx_cpgmac0__mdio,
aec94bf5	467	&am33xx_l3_main__sha0,
1cb804b9	468	&am33xx_l3_main__aes0,
ace1e3ec	469	&am33xx_l4_per__rng,
a2cfc509 VH	470	NULL,
	471	};
	472
	473	int __init am33xx_hwmod_init(void)
	474	{
1c7e224d	475	omap_hwmod_am33xx_reg();
a2cfc509 VH	476	omap_hwmod_init();
	477	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
	478	}