Commit | Line | Data |
---|---|---|
26649467 AM |
1 | /* |
2 | * | |
3 | * Copyright (C) 2013 Texas Instruments Incorporated | |
4 | * | |
5 | * Hwmod common for AM335x and AM43x | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/platform_data/gpio-omap.h> | |
55143438 | 18 | #include <linux/platform_data/hsmmc-omap.h> |
26649467 AM |
19 | #include <linux/platform_data/spi-omap2-mcspi.h> |
20 | #include "omap_hwmod.h" | |
21 | #include "i2c.h" | |
26649467 AM |
22 | #include "wd_timer.h" |
23 | #include "cm33xx.h" | |
24 | #include "prm33xx.h" | |
25 | #include "omap_hwmod_33xx_43xx_common_data.h" | |
6913952f | 26 | #include "prcm43xx.h" |
4794208c | 27 | #include "common.h" |
26649467 | 28 | |
1c7e224d AM |
29 | #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) |
30 | #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) | |
31 | #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) | |
ddb0d99d | 32 | #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag)) |
1c7e224d | 33 | |
26649467 AM |
34 | /* |
35 | * 'l3' class | |
36 | * instance(s): l3_main, l3_s, l3_instr | |
37 | */ | |
38 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | |
39 | .name = "l3", | |
40 | }; | |
41 | ||
42 | struct omap_hwmod am33xx_l3_main_hwmod = { | |
43 | .name = "l3_main", | |
44 | .class = &am33xx_l3_hwmod_class, | |
45 | .clkdm_name = "l3_clkdm", | |
46 | .flags = HWMOD_INIT_NO_IDLE, | |
47 | .main_clk = "l3_gclk", | |
48 | .prcm = { | |
49 | .omap4 = { | |
26649467 AM |
50 | .modulemode = MODULEMODE_SWCTRL, |
51 | }, | |
52 | }, | |
53 | }; | |
54 | ||
55 | /* l3_s */ | |
56 | struct omap_hwmod am33xx_l3_s_hwmod = { | |
57 | .name = "l3_s", | |
58 | .class = &am33xx_l3_hwmod_class, | |
59 | .clkdm_name = "l3s_clkdm", | |
60 | }; | |
61 | ||
62 | /* l3_instr */ | |
63 | struct omap_hwmod am33xx_l3_instr_hwmod = { | |
64 | .name = "l3_instr", | |
65 | .class = &am33xx_l3_hwmod_class, | |
66 | .clkdm_name = "l3_clkdm", | |
67 | .flags = HWMOD_INIT_NO_IDLE, | |
68 | .main_clk = "l3_gclk", | |
69 | .prcm = { | |
70 | .omap4 = { | |
26649467 AM |
71 | .modulemode = MODULEMODE_SWCTRL, |
72 | }, | |
73 | }, | |
74 | }; | |
75 | ||
76 | /* | |
77 | * 'l4' class | |
78 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | |
79 | */ | |
80 | struct omap_hwmod_class am33xx_l4_hwmod_class = { | |
81 | .name = "l4", | |
82 | }; | |
83 | ||
84 | /* l4_ls */ | |
85 | struct omap_hwmod am33xx_l4_ls_hwmod = { | |
86 | .name = "l4_ls", | |
87 | .class = &am33xx_l4_hwmod_class, | |
88 | .clkdm_name = "l4ls_clkdm", | |
89 | .flags = HWMOD_INIT_NO_IDLE, | |
90 | .main_clk = "l4ls_gclk", | |
91 | .prcm = { | |
92 | .omap4 = { | |
26649467 AM |
93 | .modulemode = MODULEMODE_SWCTRL, |
94 | }, | |
95 | }, | |
96 | }; | |
97 | ||
98 | /* l4_wkup */ | |
99 | struct omap_hwmod am33xx_l4_wkup_hwmod = { | |
100 | .name = "l4_wkup", | |
101 | .class = &am33xx_l4_hwmod_class, | |
102 | .clkdm_name = "l4_wkup_clkdm", | |
103 | .flags = HWMOD_INIT_NO_IDLE, | |
104 | .prcm = { | |
105 | .omap4 = { | |
26649467 AM |
106 | .modulemode = MODULEMODE_SWCTRL, |
107 | }, | |
108 | }, | |
109 | }; | |
110 | ||
111 | /* | |
112 | * 'mpu' class | |
113 | */ | |
114 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | |
115 | .name = "mpu", | |
116 | }; | |
117 | ||
118 | struct omap_hwmod am33xx_mpu_hwmod = { | |
119 | .name = "mpu", | |
120 | .class = &am33xx_mpu_hwmod_class, | |
121 | .clkdm_name = "mpu_clkdm", | |
122 | .flags = HWMOD_INIT_NO_IDLE, | |
123 | .main_clk = "dpll_mpu_m2_ck", | |
124 | .prcm = { | |
125 | .omap4 = { | |
26649467 AM |
126 | .modulemode = MODULEMODE_SWCTRL, |
127 | }, | |
128 | }, | |
129 | }; | |
130 | ||
131 | /* | |
132 | * 'wakeup m3' class | |
133 | * Wakeup controller sub-system under wakeup domain | |
134 | */ | |
135 | struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | |
136 | .name = "wkup_m3", | |
137 | }; | |
138 | ||
139 | /* | |
140 | * 'pru-icss' class | |
141 | * Programmable Real-Time Unit and Industrial Communication Subsystem | |
142 | */ | |
143 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | |
144 | .name = "pruss", | |
145 | }; | |
146 | ||
147 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | |
148 | { .name = "pruss", .rst_shift = 1 }, | |
149 | }; | |
150 | ||
151 | /* pru-icss */ | |
152 | /* Pseudo hwmod for reset control purpose only */ | |
153 | struct omap_hwmod am33xx_pruss_hwmod = { | |
154 | .name = "pruss", | |
155 | .class = &am33xx_pruss_hwmod_class, | |
156 | .clkdm_name = "pruss_ocp_clkdm", | |
157 | .main_clk = "pruss_ocp_gclk", | |
158 | .prcm = { | |
159 | .omap4 = { | |
26649467 AM |
160 | .modulemode = MODULEMODE_SWCTRL, |
161 | }, | |
162 | }, | |
163 | .rst_lines = am33xx_pruss_resets, | |
164 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | |
165 | }; | |
166 | ||
167 | /* gfx */ | |
168 | /* Pseudo hwmod for reset control purpose only */ | |
169 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | |
170 | .name = "gfx", | |
171 | }; | |
172 | ||
173 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | |
174 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, | |
175 | }; | |
176 | ||
177 | struct omap_hwmod am33xx_gfx_hwmod = { | |
178 | .name = "gfx", | |
179 | .class = &am33xx_gfx_hwmod_class, | |
180 | .clkdm_name = "gfx_l3_clkdm", | |
181 | .main_clk = "gfx_fck_div_ck", | |
182 | .prcm = { | |
183 | .omap4 = { | |
26649467 AM |
184 | .modulemode = MODULEMODE_SWCTRL, |
185 | }, | |
186 | }, | |
187 | .rst_lines = am33xx_gfx_resets, | |
188 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | |
189 | }; | |
190 | ||
191 | /* | |
192 | * 'prcm' class | |
193 | * power and reset manager (whole prcm infrastructure) | |
194 | */ | |
195 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | |
196 | .name = "prcm", | |
197 | }; | |
198 | ||
199 | /* prcm */ | |
200 | struct omap_hwmod am33xx_prcm_hwmod = { | |
201 | .name = "prcm", | |
202 | .class = &am33xx_prcm_hwmod_class, | |
203 | .clkdm_name = "l4_wkup_clkdm", | |
204 | }; | |
205 | ||
fabbe6df DG |
206 | /* |
207 | * 'emif' class | |
208 | * instance(s): emif | |
209 | */ | |
210 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { | |
211 | .rev_offs = 0x0000, | |
212 | }; | |
213 | ||
214 | struct omap_hwmod_class am33xx_emif_hwmod_class = { | |
215 | .name = "emif", | |
216 | .sysc = &am33xx_emif_sysc, | |
217 | }; | |
218 | ||
26649467 AM |
219 | /* |
220 | * 'aes0' class | |
221 | */ | |
222 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { | |
223 | .rev_offs = 0x80, | |
224 | .sysc_offs = 0x84, | |
225 | .syss_offs = 0x88, | |
226 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
227 | }; | |
228 | ||
229 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | |
230 | .name = "aes0", | |
231 | .sysc = &am33xx_aes0_sysc, | |
232 | }; | |
233 | ||
234 | struct omap_hwmod am33xx_aes0_hwmod = { | |
235 | .name = "aes", | |
236 | .class = &am33xx_aes0_hwmod_class, | |
237 | .clkdm_name = "l3_clkdm", | |
238 | .main_clk = "aes0_fck", | |
239 | .prcm = { | |
240 | .omap4 = { | |
26649467 AM |
241 | .modulemode = MODULEMODE_SWCTRL, |
242 | }, | |
243 | }, | |
244 | }; | |
245 | ||
246 | /* sha0 HIB2 (the 'P' (public) device) */ | |
247 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | |
248 | .rev_offs = 0x100, | |
249 | .sysc_offs = 0x110, | |
250 | .syss_offs = 0x114, | |
251 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
252 | }; | |
253 | ||
254 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | |
255 | .name = "sha0", | |
256 | .sysc = &am33xx_sha0_sysc, | |
257 | }; | |
258 | ||
259 | struct omap_hwmod am33xx_sha0_hwmod = { | |
260 | .name = "sham", | |
261 | .class = &am33xx_sha0_hwmod_class, | |
262 | .clkdm_name = "l3_clkdm", | |
263 | .main_clk = "l3_gclk", | |
264 | .prcm = { | |
265 | .omap4 = { | |
26649467 AM |
266 | .modulemode = MODULEMODE_SWCTRL, |
267 | }, | |
268 | }, | |
269 | }; | |
270 | ||
d88d30e7 LV |
271 | /* rng */ |
272 | static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { | |
273 | .rev_offs = 0x1fe0, | |
274 | .sysc_offs = 0x1fe4, | |
275 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, | |
276 | .idlemodes = SIDLE_FORCE | SIDLE_NO, | |
277 | .sysc_fields = &omap_hwmod_sysc_type1, | |
278 | }; | |
279 | ||
280 | static struct omap_hwmod_class am33xx_rng_hwmod_class = { | |
281 | .name = "rng", | |
282 | .sysc = &am33xx_rng_sysc, | |
283 | }; | |
284 | ||
285 | struct omap_hwmod am33xx_rng_hwmod = { | |
286 | .name = "rng", | |
287 | .class = &am33xx_rng_hwmod_class, | |
288 | .clkdm_name = "l4ls_clkdm", | |
289 | .flags = HWMOD_SWSUP_SIDLE, | |
290 | .main_clk = "rng_fck", | |
291 | .prcm = { | |
292 | .omap4 = { | |
293 | .modulemode = MODULEMODE_SWCTRL, | |
294 | }, | |
295 | }, | |
296 | }; | |
297 | ||
26649467 AM |
298 | /* ocmcram */ |
299 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | |
300 | .name = "ocmcram", | |
301 | }; | |
302 | ||
303 | struct omap_hwmod am33xx_ocmcram_hwmod = { | |
304 | .name = "ocmcram", | |
305 | .class = &am33xx_ocmcram_hwmod_class, | |
306 | .clkdm_name = "l3_clkdm", | |
307 | .flags = HWMOD_INIT_NO_IDLE, | |
308 | .main_clk = "l3_gclk", | |
309 | .prcm = { | |
310 | .omap4 = { | |
26649467 AM |
311 | .modulemode = MODULEMODE_SWCTRL, |
312 | }, | |
313 | }, | |
314 | }; | |
315 | ||
316 | /* 'smartreflex' class */ | |
317 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | |
318 | .name = "smartreflex", | |
319 | }; | |
320 | ||
321 | /* smartreflex0 */ | |
322 | struct omap_hwmod am33xx_smartreflex0_hwmod = { | |
323 | .name = "smartreflex0", | |
324 | .class = &am33xx_smartreflex_hwmod_class, | |
325 | .clkdm_name = "l4_wkup_clkdm", | |
326 | .main_clk = "smartreflex0_fck", | |
327 | .prcm = { | |
328 | .omap4 = { | |
26649467 AM |
329 | .modulemode = MODULEMODE_SWCTRL, |
330 | }, | |
331 | }, | |
332 | }; | |
333 | ||
334 | /* smartreflex1 */ | |
335 | struct omap_hwmod am33xx_smartreflex1_hwmod = { | |
336 | .name = "smartreflex1", | |
337 | .class = &am33xx_smartreflex_hwmod_class, | |
338 | .clkdm_name = "l4_wkup_clkdm", | |
339 | .main_clk = "smartreflex1_fck", | |
340 | .prcm = { | |
341 | .omap4 = { | |
26649467 AM |
342 | .modulemode = MODULEMODE_SWCTRL, |
343 | }, | |
344 | }, | |
345 | }; | |
346 | ||
347 | /* | |
348 | * 'control' module class | |
349 | */ | |
350 | struct omap_hwmod_class am33xx_control_hwmod_class = { | |
351 | .name = "control", | |
352 | }; | |
353 | ||
354 | /* | |
355 | * 'cpgmac' class | |
356 | * cpsw/cpgmac sub system | |
357 | */ | |
358 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | |
359 | .rev_offs = 0x0, | |
360 | .sysc_offs = 0x8, | |
361 | .syss_offs = 0x4, | |
362 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
363 | SYSS_HAS_RESET_STATUS), | |
364 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
365 | MSTANDBY_NO), | |
366 | .sysc_fields = &omap_hwmod_sysc_type3, | |
367 | }; | |
368 | ||
369 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | |
370 | .name = "cpgmac0", | |
371 | .sysc = &am33xx_cpgmac_sysc, | |
372 | }; | |
373 | ||
374 | struct omap_hwmod am33xx_cpgmac0_hwmod = { | |
375 | .name = "cpgmac0", | |
376 | .class = &am33xx_cpgmac0_hwmod_class, | |
377 | .clkdm_name = "cpsw_125mhz_clkdm", | |
378 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
379 | .main_clk = "cpsw_125mhz_gclk", | |
380 | .mpu_rt_idx = 1, | |
381 | .prcm = { | |
382 | .omap4 = { | |
26649467 AM |
383 | .modulemode = MODULEMODE_SWCTRL, |
384 | }, | |
385 | }, | |
386 | }; | |
387 | ||
388 | /* | |
389 | * mdio class | |
390 | */ | |
391 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { | |
392 | .name = "davinci_mdio", | |
393 | }; | |
394 | ||
395 | struct omap_hwmod am33xx_mdio_hwmod = { | |
396 | .name = "davinci_mdio", | |
397 | .class = &am33xx_mdio_hwmod_class, | |
398 | .clkdm_name = "cpsw_125mhz_clkdm", | |
399 | .main_clk = "cpsw_125mhz_gclk", | |
400 | }; | |
401 | ||
402 | /* | |
403 | * dcan class | |
404 | */ | |
405 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | |
406 | .name = "d_can", | |
407 | }; | |
408 | ||
409 | /* dcan0 */ | |
410 | struct omap_hwmod am33xx_dcan0_hwmod = { | |
411 | .name = "d_can0", | |
412 | .class = &am33xx_dcan_hwmod_class, | |
413 | .clkdm_name = "l4ls_clkdm", | |
414 | .main_clk = "dcan0_fck", | |
415 | .prcm = { | |
416 | .omap4 = { | |
26649467 AM |
417 | .modulemode = MODULEMODE_SWCTRL, |
418 | }, | |
419 | }, | |
420 | }; | |
421 | ||
422 | /* dcan1 */ | |
423 | struct omap_hwmod am33xx_dcan1_hwmod = { | |
424 | .name = "d_can1", | |
425 | .class = &am33xx_dcan_hwmod_class, | |
426 | .clkdm_name = "l4ls_clkdm", | |
427 | .main_clk = "dcan1_fck", | |
428 | .prcm = { | |
429 | .omap4 = { | |
26649467 AM |
430 | .modulemode = MODULEMODE_SWCTRL, |
431 | }, | |
432 | }, | |
433 | }; | |
434 | ||
435 | /* elm */ | |
436 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | |
437 | .rev_offs = 0x0000, | |
438 | .sysc_offs = 0x0010, | |
439 | .syss_offs = 0x0014, | |
440 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
441 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
442 | SYSS_HAS_RESET_STATUS), | |
443 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
444 | .sysc_fields = &omap_hwmod_sysc_type1, | |
445 | }; | |
446 | ||
447 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | |
448 | .name = "elm", | |
449 | .sysc = &am33xx_elm_sysc, | |
450 | }; | |
451 | ||
452 | struct omap_hwmod am33xx_elm_hwmod = { | |
453 | .name = "elm", | |
454 | .class = &am33xx_elm_hwmod_class, | |
455 | .clkdm_name = "l4ls_clkdm", | |
456 | .main_clk = "l4ls_gclk", | |
457 | .prcm = { | |
458 | .omap4 = { | |
26649467 AM |
459 | .modulemode = MODULEMODE_SWCTRL, |
460 | }, | |
461 | }, | |
462 | }; | |
463 | ||
464 | /* pwmss */ | |
465 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { | |
466 | .rev_offs = 0x0, | |
467 | .sysc_offs = 0x4, | |
468 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
469 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
470 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
471 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
472 | .sysc_fields = &omap_hwmod_sysc_type2, | |
473 | }; | |
474 | ||
475 | struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | |
476 | .name = "epwmss", | |
477 | .sysc = &am33xx_epwmss_sysc, | |
478 | }; | |
479 | ||
26649467 AM |
480 | /* epwmss0 */ |
481 | struct omap_hwmod am33xx_epwmss0_hwmod = { | |
482 | .name = "epwmss0", | |
483 | .class = &am33xx_epwmss_hwmod_class, | |
484 | .clkdm_name = "l4ls_clkdm", | |
485 | .main_clk = "l4ls_gclk", | |
486 | .prcm = { | |
487 | .omap4 = { | |
26649467 AM |
488 | .modulemode = MODULEMODE_SWCTRL, |
489 | }, | |
490 | }, | |
491 | }; | |
492 | ||
26649467 AM |
493 | /* epwmss1 */ |
494 | struct omap_hwmod am33xx_epwmss1_hwmod = { | |
495 | .name = "epwmss1", | |
496 | .class = &am33xx_epwmss_hwmod_class, | |
497 | .clkdm_name = "l4ls_clkdm", | |
498 | .main_clk = "l4ls_gclk", | |
499 | .prcm = { | |
500 | .omap4 = { | |
26649467 AM |
501 | .modulemode = MODULEMODE_SWCTRL, |
502 | }, | |
503 | }, | |
504 | }; | |
505 | ||
26649467 AM |
506 | /* epwmss2 */ |
507 | struct omap_hwmod am33xx_epwmss2_hwmod = { | |
508 | .name = "epwmss2", | |
509 | .class = &am33xx_epwmss_hwmod_class, | |
510 | .clkdm_name = "l4ls_clkdm", | |
511 | .main_clk = "l4ls_gclk", | |
512 | .prcm = { | |
513 | .omap4 = { | |
26649467 AM |
514 | .modulemode = MODULEMODE_SWCTRL, |
515 | }, | |
516 | }, | |
517 | }; | |
518 | ||
26649467 AM |
519 | /* |
520 | * 'gpio' class: for gpio 0,1,2,3 | |
521 | */ | |
522 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | |
523 | .rev_offs = 0x0000, | |
524 | .sysc_offs = 0x0010, | |
525 | .syss_offs = 0x0114, | |
526 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
527 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
528 | SYSS_HAS_RESET_STATUS), | |
529 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
530 | SIDLE_SMART_WKUP), | |
531 | .sysc_fields = &omap_hwmod_sysc_type1, | |
532 | }; | |
533 | ||
534 | struct omap_hwmod_class am33xx_gpio_hwmod_class = { | |
535 | .name = "gpio", | |
536 | .sysc = &am33xx_gpio_sysc, | |
537 | .rev = 2, | |
538 | }; | |
539 | ||
540 | struct omap_gpio_dev_attr gpio_dev_attr = { | |
541 | .bank_width = 32, | |
542 | .dbck_flag = true, | |
543 | }; | |
544 | ||
545 | /* gpio1 */ | |
546 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
547 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
548 | }; | |
549 | ||
550 | struct omap_hwmod am33xx_gpio1_hwmod = { | |
551 | .name = "gpio2", | |
552 | .class = &am33xx_gpio_hwmod_class, | |
553 | .clkdm_name = "l4ls_clkdm", | |
554 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
555 | .main_clk = "l4ls_gclk", | |
556 | .prcm = { | |
557 | .omap4 = { | |
26649467 AM |
558 | .modulemode = MODULEMODE_SWCTRL, |
559 | }, | |
560 | }, | |
561 | .opt_clks = gpio1_opt_clks, | |
562 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
563 | .dev_attr = &gpio_dev_attr, | |
564 | }; | |
565 | ||
566 | /* gpio2 */ | |
567 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
568 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
569 | }; | |
570 | ||
571 | struct omap_hwmod am33xx_gpio2_hwmod = { | |
572 | .name = "gpio3", | |
573 | .class = &am33xx_gpio_hwmod_class, | |
574 | .clkdm_name = "l4ls_clkdm", | |
575 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
576 | .main_clk = "l4ls_gclk", | |
577 | .prcm = { | |
578 | .omap4 = { | |
26649467 AM |
579 | .modulemode = MODULEMODE_SWCTRL, |
580 | }, | |
581 | }, | |
582 | .opt_clks = gpio2_opt_clks, | |
583 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
584 | .dev_attr = &gpio_dev_attr, | |
585 | }; | |
586 | ||
587 | /* gpio3 */ | |
588 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
589 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
590 | }; | |
591 | ||
592 | struct omap_hwmod am33xx_gpio3_hwmod = { | |
593 | .name = "gpio4", | |
594 | .class = &am33xx_gpio_hwmod_class, | |
595 | .clkdm_name = "l4ls_clkdm", | |
596 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
597 | .main_clk = "l4ls_gclk", | |
598 | .prcm = { | |
599 | .omap4 = { | |
26649467 AM |
600 | .modulemode = MODULEMODE_SWCTRL, |
601 | }, | |
602 | }, | |
603 | .opt_clks = gpio3_opt_clks, | |
604 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
605 | .dev_attr = &gpio_dev_attr, | |
606 | }; | |
607 | ||
608 | /* gpmc */ | |
609 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | |
610 | .rev_offs = 0x0, | |
611 | .sysc_offs = 0x10, | |
612 | .syss_offs = 0x14, | |
613 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
614 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
615 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
616 | .sysc_fields = &omap_hwmod_sysc_type1, | |
617 | }; | |
618 | ||
619 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | |
620 | .name = "gpmc", | |
621 | .sysc = &gpmc_sysc, | |
622 | }; | |
623 | ||
624 | struct omap_hwmod am33xx_gpmc_hwmod = { | |
625 | .name = "gpmc", | |
626 | .class = &am33xx_gpmc_hwmod_class, | |
627 | .clkdm_name = "l3s_clkdm", | |
63aa945b TL |
628 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
629 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
26649467 AM |
630 | .main_clk = "l3s_gclk", |
631 | .prcm = { | |
632 | .omap4 = { | |
26649467 AM |
633 | .modulemode = MODULEMODE_SWCTRL, |
634 | }, | |
635 | }, | |
636 | }; | |
637 | ||
638 | /* 'i2c' class */ | |
639 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | |
640 | .sysc_offs = 0x0010, | |
641 | .syss_offs = 0x0090, | |
642 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
643 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
644 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
645 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
646 | SIDLE_SMART_WKUP), | |
647 | .sysc_fields = &omap_hwmod_sysc_type1, | |
648 | }; | |
649 | ||
650 | static struct omap_hwmod_class i2c_class = { | |
651 | .name = "i2c", | |
652 | .sysc = &am33xx_i2c_sysc, | |
653 | .rev = OMAP_I2C_IP_VERSION_2, | |
654 | .reset = &omap_i2c_reset, | |
655 | }; | |
656 | ||
657 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
658 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
659 | }; | |
660 | ||
661 | /* i2c1 */ | |
662 | struct omap_hwmod am33xx_i2c1_hwmod = { | |
663 | .name = "i2c1", | |
664 | .class = &i2c_class, | |
665 | .clkdm_name = "l4_wkup_clkdm", | |
666 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
667 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
668 | .prcm = { | |
669 | .omap4 = { | |
26649467 AM |
670 | .modulemode = MODULEMODE_SWCTRL, |
671 | }, | |
672 | }, | |
673 | .dev_attr = &i2c_dev_attr, | |
674 | }; | |
675 | ||
676 | /* i2c1 */ | |
677 | struct omap_hwmod am33xx_i2c2_hwmod = { | |
678 | .name = "i2c2", | |
679 | .class = &i2c_class, | |
680 | .clkdm_name = "l4ls_clkdm", | |
681 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
682 | .main_clk = "dpll_per_m2_div4_ck", | |
683 | .prcm = { | |
684 | .omap4 = { | |
26649467 AM |
685 | .modulemode = MODULEMODE_SWCTRL, |
686 | }, | |
687 | }, | |
688 | .dev_attr = &i2c_dev_attr, | |
689 | }; | |
690 | ||
691 | /* i2c3 */ | |
692 | struct omap_hwmod am33xx_i2c3_hwmod = { | |
693 | .name = "i2c3", | |
694 | .class = &i2c_class, | |
695 | .clkdm_name = "l4ls_clkdm", | |
696 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
697 | .main_clk = "dpll_per_m2_div4_ck", | |
698 | .prcm = { | |
699 | .omap4 = { | |
26649467 AM |
700 | .modulemode = MODULEMODE_SWCTRL, |
701 | }, | |
702 | }, | |
703 | .dev_attr = &i2c_dev_attr, | |
704 | }; | |
705 | ||
706 | /* | |
707 | * 'mailbox' class | |
708 | * mailbox module allowing communication between the on-chip processors using a | |
709 | * queued mailbox-interrupt mechanism. | |
710 | */ | |
711 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | |
712 | .rev_offs = 0x0000, | |
713 | .sysc_offs = 0x0010, | |
714 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
715 | SYSC_HAS_SOFTRESET), | |
716 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
717 | .sysc_fields = &omap_hwmod_sysc_type2, | |
718 | }; | |
719 | ||
720 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | |
721 | .name = "mailbox", | |
722 | .sysc = &am33xx_mailbox_sysc, | |
723 | }; | |
724 | ||
725 | struct omap_hwmod am33xx_mailbox_hwmod = { | |
726 | .name = "mailbox", | |
727 | .class = &am33xx_mailbox_hwmod_class, | |
728 | .clkdm_name = "l4ls_clkdm", | |
729 | .main_clk = "l4ls_gclk", | |
730 | .prcm = { | |
731 | .omap4 = { | |
26649467 AM |
732 | .modulemode = MODULEMODE_SWCTRL, |
733 | }, | |
734 | }, | |
735 | }; | |
736 | ||
737 | /* | |
738 | * 'mcasp' class | |
739 | */ | |
740 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | |
741 | .rev_offs = 0x0, | |
742 | .sysc_offs = 0x4, | |
743 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
744 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
745 | .sysc_fields = &omap_hwmod_sysc_type3, | |
746 | }; | |
747 | ||
748 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | |
749 | .name = "mcasp", | |
750 | .sysc = &am33xx_mcasp_sysc, | |
751 | }; | |
752 | ||
753 | /* mcasp0 */ | |
754 | struct omap_hwmod am33xx_mcasp0_hwmod = { | |
755 | .name = "mcasp0", | |
756 | .class = &am33xx_mcasp_hwmod_class, | |
757 | .clkdm_name = "l3s_clkdm", | |
758 | .main_clk = "mcasp0_fck", | |
759 | .prcm = { | |
760 | .omap4 = { | |
26649467 AM |
761 | .modulemode = MODULEMODE_SWCTRL, |
762 | }, | |
763 | }, | |
764 | }; | |
765 | ||
766 | /* mcasp1 */ | |
767 | struct omap_hwmod am33xx_mcasp1_hwmod = { | |
768 | .name = "mcasp1", | |
769 | .class = &am33xx_mcasp_hwmod_class, | |
770 | .clkdm_name = "l3s_clkdm", | |
771 | .main_clk = "mcasp1_fck", | |
772 | .prcm = { | |
773 | .omap4 = { | |
26649467 AM |
774 | .modulemode = MODULEMODE_SWCTRL, |
775 | }, | |
776 | }, | |
777 | }; | |
778 | ||
779 | /* 'mmc' class */ | |
780 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | |
781 | .rev_offs = 0x1fc, | |
782 | .sysc_offs = 0x10, | |
783 | .syss_offs = 0x14, | |
784 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
785 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
786 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
787 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
788 | .sysc_fields = &omap_hwmod_sysc_type1, | |
789 | }; | |
790 | ||
791 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | |
792 | .name = "mmc", | |
793 | .sysc = &am33xx_mmc_sysc, | |
794 | }; | |
795 | ||
796 | /* mmc0 */ | |
55143438 | 797 | static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = { |
26649467 AM |
798 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
799 | }; | |
800 | ||
801 | struct omap_hwmod am33xx_mmc0_hwmod = { | |
802 | .name = "mmc1", | |
803 | .class = &am33xx_mmc_hwmod_class, | |
804 | .clkdm_name = "l4ls_clkdm", | |
805 | .main_clk = "mmc_clk", | |
806 | .prcm = { | |
807 | .omap4 = { | |
26649467 AM |
808 | .modulemode = MODULEMODE_SWCTRL, |
809 | }, | |
810 | }, | |
811 | .dev_attr = &am33xx_mmc0_dev_attr, | |
812 | }; | |
813 | ||
814 | /* mmc1 */ | |
55143438 | 815 | static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = { |
26649467 AM |
816 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
817 | }; | |
818 | ||
819 | struct omap_hwmod am33xx_mmc1_hwmod = { | |
820 | .name = "mmc2", | |
821 | .class = &am33xx_mmc_hwmod_class, | |
822 | .clkdm_name = "l4ls_clkdm", | |
823 | .main_clk = "mmc_clk", | |
824 | .prcm = { | |
825 | .omap4 = { | |
26649467 AM |
826 | .modulemode = MODULEMODE_SWCTRL, |
827 | }, | |
828 | }, | |
829 | .dev_attr = &am33xx_mmc1_dev_attr, | |
830 | }; | |
831 | ||
832 | /* mmc2 */ | |
55143438 | 833 | static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = { |
26649467 AM |
834 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
835 | }; | |
836 | struct omap_hwmod am33xx_mmc2_hwmod = { | |
837 | .name = "mmc3", | |
838 | .class = &am33xx_mmc_hwmod_class, | |
839 | .clkdm_name = "l3s_clkdm", | |
840 | .main_clk = "mmc_clk", | |
841 | .prcm = { | |
842 | .omap4 = { | |
26649467 AM |
843 | .modulemode = MODULEMODE_SWCTRL, |
844 | }, | |
845 | }, | |
846 | .dev_attr = &am33xx_mmc2_dev_attr, | |
847 | }; | |
848 | ||
849 | /* | |
850 | * 'rtc' class | |
851 | * rtc subsystem | |
852 | */ | |
853 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | |
854 | .rev_offs = 0x0074, | |
855 | .sysc_offs = 0x0078, | |
856 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
857 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | |
858 | SIDLE_SMART | SIDLE_SMART_WKUP), | |
859 | .sysc_fields = &omap_hwmod_sysc_type3, | |
860 | }; | |
861 | ||
862 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | |
863 | .name = "rtc", | |
864 | .sysc = &am33xx_rtc_sysc, | |
b5a553c0 LV |
865 | .unlock = &omap_hwmod_rtc_unlock, |
866 | .lock = &omap_hwmod_rtc_lock, | |
26649467 AM |
867 | }; |
868 | ||
869 | struct omap_hwmod am33xx_rtc_hwmod = { | |
870 | .name = "rtc", | |
871 | .class = &am33xx_rtc_hwmod_class, | |
872 | .clkdm_name = "l4_rtc_clkdm", | |
873 | .main_clk = "clk_32768_ck", | |
874 | .prcm = { | |
875 | .omap4 = { | |
26649467 AM |
876 | .modulemode = MODULEMODE_SWCTRL, |
877 | }, | |
878 | }, | |
879 | }; | |
880 | ||
881 | /* 'spi' class */ | |
882 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | |
883 | .rev_offs = 0x0000, | |
884 | .sysc_offs = 0x0110, | |
885 | .syss_offs = 0x0114, | |
886 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
887 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
888 | SYSS_HAS_RESET_STATUS), | |
889 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
890 | .sysc_fields = &omap_hwmod_sysc_type1, | |
891 | }; | |
892 | ||
893 | struct omap_hwmod_class am33xx_spi_hwmod_class = { | |
894 | .name = "mcspi", | |
895 | .sysc = &am33xx_mcspi_sysc, | |
896 | .rev = OMAP4_MCSPI_REV, | |
897 | }; | |
898 | ||
899 | /* spi0 */ | |
900 | struct omap2_mcspi_dev_attr mcspi_attrib = { | |
901 | .num_chipselect = 2, | |
902 | }; | |
903 | struct omap_hwmod am33xx_spi0_hwmod = { | |
904 | .name = "spi0", | |
905 | .class = &am33xx_spi_hwmod_class, | |
906 | .clkdm_name = "l4ls_clkdm", | |
907 | .main_clk = "dpll_per_m2_div4_ck", | |
908 | .prcm = { | |
909 | .omap4 = { | |
26649467 AM |
910 | .modulemode = MODULEMODE_SWCTRL, |
911 | }, | |
912 | }, | |
913 | .dev_attr = &mcspi_attrib, | |
914 | }; | |
915 | ||
916 | /* spi1 */ | |
917 | struct omap_hwmod am33xx_spi1_hwmod = { | |
918 | .name = "spi1", | |
919 | .class = &am33xx_spi_hwmod_class, | |
920 | .clkdm_name = "l4ls_clkdm", | |
921 | .main_clk = "dpll_per_m2_div4_ck", | |
922 | .prcm = { | |
923 | .omap4 = { | |
26649467 AM |
924 | .modulemode = MODULEMODE_SWCTRL, |
925 | }, | |
926 | }, | |
927 | .dev_attr = &mcspi_attrib, | |
928 | }; | |
929 | ||
930 | /* | |
931 | * 'spinlock' class | |
932 | * spinlock provides hardware assistance for synchronizing the | |
933 | * processes running on multiple processors | |
934 | */ | |
935 | ||
936 | static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = { | |
937 | .rev_offs = 0x0000, | |
938 | .sysc_offs = 0x0010, | |
939 | .syss_offs = 0x0014, | |
940 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
941 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
942 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
943 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
944 | .sysc_fields = &omap_hwmod_sysc_type1, | |
945 | }; | |
946 | ||
947 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { | |
948 | .name = "spinlock", | |
949 | .sysc = &am33xx_spinlock_sysc, | |
950 | }; | |
951 | ||
952 | struct omap_hwmod am33xx_spinlock_hwmod = { | |
953 | .name = "spinlock", | |
954 | .class = &am33xx_spinlock_hwmod_class, | |
955 | .clkdm_name = "l4ls_clkdm", | |
956 | .main_clk = "l4ls_gclk", | |
957 | .prcm = { | |
958 | .omap4 = { | |
26649467 AM |
959 | .modulemode = MODULEMODE_SWCTRL, |
960 | }, | |
961 | }, | |
962 | }; | |
963 | ||
964 | /* 'timer 2-7' class */ | |
965 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | |
966 | .rev_offs = 0x0000, | |
967 | .sysc_offs = 0x0010, | |
968 | .syss_offs = 0x0014, | |
969 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
970 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
971 | SIDLE_SMART_WKUP), | |
972 | .sysc_fields = &omap_hwmod_sysc_type2, | |
973 | }; | |
974 | ||
975 | struct omap_hwmod_class am33xx_timer_hwmod_class = { | |
976 | .name = "timer", | |
977 | .sysc = &am33xx_timer_sysc, | |
978 | }; | |
979 | ||
980 | /* timer1 1ms */ | |
981 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | |
982 | .rev_offs = 0x0000, | |
983 | .sysc_offs = 0x0010, | |
984 | .syss_offs = 0x0014, | |
985 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
986 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
987 | SYSS_HAS_RESET_STATUS), | |
988 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
989 | .sysc_fields = &omap_hwmod_sysc_type1, | |
990 | }; | |
991 | ||
992 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | |
993 | .name = "timer", | |
994 | .sysc = &am33xx_timer1ms_sysc, | |
995 | }; | |
996 | ||
997 | struct omap_hwmod am33xx_timer1_hwmod = { | |
998 | .name = "timer1", | |
999 | .class = &am33xx_timer1ms_hwmod_class, | |
1000 | .clkdm_name = "l4_wkup_clkdm", | |
1001 | .main_clk = "timer1_fck", | |
1002 | .prcm = { | |
1003 | .omap4 = { | |
26649467 AM |
1004 | .modulemode = MODULEMODE_SWCTRL, |
1005 | }, | |
1006 | }, | |
1007 | }; | |
1008 | ||
1009 | struct omap_hwmod am33xx_timer2_hwmod = { | |
1010 | .name = "timer2", | |
1011 | .class = &am33xx_timer_hwmod_class, | |
1012 | .clkdm_name = "l4ls_clkdm", | |
1013 | .main_clk = "timer2_fck", | |
1014 | .prcm = { | |
1015 | .omap4 = { | |
26649467 AM |
1016 | .modulemode = MODULEMODE_SWCTRL, |
1017 | }, | |
1018 | }, | |
1019 | }; | |
1020 | ||
1021 | struct omap_hwmod am33xx_timer3_hwmod = { | |
1022 | .name = "timer3", | |
1023 | .class = &am33xx_timer_hwmod_class, | |
1024 | .clkdm_name = "l4ls_clkdm", | |
1025 | .main_clk = "timer3_fck", | |
1026 | .prcm = { | |
1027 | .omap4 = { | |
26649467 AM |
1028 | .modulemode = MODULEMODE_SWCTRL, |
1029 | }, | |
1030 | }, | |
1031 | }; | |
1032 | ||
1033 | struct omap_hwmod am33xx_timer4_hwmod = { | |
1034 | .name = "timer4", | |
1035 | .class = &am33xx_timer_hwmod_class, | |
1036 | .clkdm_name = "l4ls_clkdm", | |
1037 | .main_clk = "timer4_fck", | |
1038 | .prcm = { | |
1039 | .omap4 = { | |
26649467 AM |
1040 | .modulemode = MODULEMODE_SWCTRL, |
1041 | }, | |
1042 | }, | |
1043 | }; | |
1044 | ||
1045 | struct omap_hwmod am33xx_timer5_hwmod = { | |
1046 | .name = "timer5", | |
1047 | .class = &am33xx_timer_hwmod_class, | |
1048 | .clkdm_name = "l4ls_clkdm", | |
1049 | .main_clk = "timer5_fck", | |
1050 | .prcm = { | |
1051 | .omap4 = { | |
26649467 AM |
1052 | .modulemode = MODULEMODE_SWCTRL, |
1053 | }, | |
1054 | }, | |
1055 | }; | |
1056 | ||
1057 | struct omap_hwmod am33xx_timer6_hwmod = { | |
1058 | .name = "timer6", | |
1059 | .class = &am33xx_timer_hwmod_class, | |
1060 | .clkdm_name = "l4ls_clkdm", | |
1061 | .main_clk = "timer6_fck", | |
1062 | .prcm = { | |
1063 | .omap4 = { | |
26649467 AM |
1064 | .modulemode = MODULEMODE_SWCTRL, |
1065 | }, | |
1066 | }, | |
1067 | }; | |
1068 | ||
1069 | struct omap_hwmod am33xx_timer7_hwmod = { | |
1070 | .name = "timer7", | |
1071 | .class = &am33xx_timer_hwmod_class, | |
1072 | .clkdm_name = "l4ls_clkdm", | |
1073 | .main_clk = "timer7_fck", | |
1074 | .prcm = { | |
1075 | .omap4 = { | |
26649467 AM |
1076 | .modulemode = MODULEMODE_SWCTRL, |
1077 | }, | |
1078 | }, | |
1079 | }; | |
1080 | ||
1081 | /* tpcc */ | |
1082 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | |
1083 | .name = "tpcc", | |
1084 | }; | |
1085 | ||
1086 | struct omap_hwmod am33xx_tpcc_hwmod = { | |
1087 | .name = "tpcc", | |
1088 | .class = &am33xx_tpcc_hwmod_class, | |
1089 | .clkdm_name = "l3_clkdm", | |
1090 | .main_clk = "l3_gclk", | |
1091 | .prcm = { | |
1092 | .omap4 = { | |
26649467 AM |
1093 | .modulemode = MODULEMODE_SWCTRL, |
1094 | }, | |
1095 | }, | |
1096 | }; | |
1097 | ||
1098 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | |
1099 | .rev_offs = 0x0, | |
1100 | .sysc_offs = 0x10, | |
1101 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1102 | SYSC_HAS_MIDLEMODE), | |
1103 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | |
1104 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1105 | }; | |
1106 | ||
1107 | /* 'tptc' class */ | |
1108 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | |
1109 | .name = "tptc", | |
1110 | .sysc = &am33xx_tptc_sysc, | |
1111 | }; | |
1112 | ||
1113 | /* tptc0 */ | |
1114 | struct omap_hwmod am33xx_tptc0_hwmod = { | |
1115 | .name = "tptc0", | |
1116 | .class = &am33xx_tptc_hwmod_class, | |
1117 | .clkdm_name = "l3_clkdm", | |
1118 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
1119 | .main_clk = "l3_gclk", | |
1120 | .prcm = { | |
1121 | .omap4 = { | |
26649467 AM |
1122 | .modulemode = MODULEMODE_SWCTRL, |
1123 | }, | |
1124 | }, | |
1125 | }; | |
1126 | ||
1127 | /* tptc1 */ | |
1128 | struct omap_hwmod am33xx_tptc1_hwmod = { | |
1129 | .name = "tptc1", | |
1130 | .class = &am33xx_tptc_hwmod_class, | |
1131 | .clkdm_name = "l3_clkdm", | |
1132 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
1133 | .main_clk = "l3_gclk", | |
1134 | .prcm = { | |
1135 | .omap4 = { | |
26649467 AM |
1136 | .modulemode = MODULEMODE_SWCTRL, |
1137 | }, | |
1138 | }, | |
1139 | }; | |
1140 | ||
1141 | /* tptc2 */ | |
1142 | struct omap_hwmod am33xx_tptc2_hwmod = { | |
1143 | .name = "tptc2", | |
1144 | .class = &am33xx_tptc_hwmod_class, | |
1145 | .clkdm_name = "l3_clkdm", | |
1146 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
1147 | .main_clk = "l3_gclk", | |
1148 | .prcm = { | |
1149 | .omap4 = { | |
26649467 AM |
1150 | .modulemode = MODULEMODE_SWCTRL, |
1151 | }, | |
1152 | }, | |
1153 | }; | |
1154 | ||
1155 | /* 'uart' class */ | |
1156 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
1157 | .rev_offs = 0x50, | |
1158 | .sysc_offs = 0x54, | |
1159 | .syss_offs = 0x58, | |
1160 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1161 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1162 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1163 | SIDLE_SMART_WKUP), | |
1164 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1165 | }; | |
1166 | ||
1167 | static struct omap_hwmod_class uart_class = { | |
1168 | .name = "uart", | |
1169 | .sysc = &uart_sysc, | |
1170 | }; | |
1171 | ||
1172 | struct omap_hwmod am33xx_uart1_hwmod = { | |
1173 | .name = "uart1", | |
1174 | .class = &uart_class, | |
1175 | .clkdm_name = "l4_wkup_clkdm", | |
1176 | .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, | |
1177 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
1178 | .prcm = { | |
1179 | .omap4 = { | |
26649467 AM |
1180 | .modulemode = MODULEMODE_SWCTRL, |
1181 | }, | |
1182 | }, | |
1183 | }; | |
1184 | ||
1185 | struct omap_hwmod am33xx_uart2_hwmod = { | |
1186 | .name = "uart2", | |
1187 | .class = &uart_class, | |
1188 | .clkdm_name = "l4ls_clkdm", | |
1189 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
1190 | .main_clk = "dpll_per_m2_div4_ck", | |
1191 | .prcm = { | |
1192 | .omap4 = { | |
26649467 AM |
1193 | .modulemode = MODULEMODE_SWCTRL, |
1194 | }, | |
1195 | }, | |
1196 | }; | |
1197 | ||
1198 | /* uart3 */ | |
1199 | struct omap_hwmod am33xx_uart3_hwmod = { | |
1200 | .name = "uart3", | |
1201 | .class = &uart_class, | |
1202 | .clkdm_name = "l4ls_clkdm", | |
1203 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
1204 | .main_clk = "dpll_per_m2_div4_ck", | |
1205 | .prcm = { | |
1206 | .omap4 = { | |
26649467 AM |
1207 | .modulemode = MODULEMODE_SWCTRL, |
1208 | }, | |
1209 | }, | |
1210 | }; | |
1211 | ||
1212 | struct omap_hwmod am33xx_uart4_hwmod = { | |
1213 | .name = "uart4", | |
1214 | .class = &uart_class, | |
1215 | .clkdm_name = "l4ls_clkdm", | |
1216 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
1217 | .main_clk = "dpll_per_m2_div4_ck", | |
1218 | .prcm = { | |
1219 | .omap4 = { | |
26649467 AM |
1220 | .modulemode = MODULEMODE_SWCTRL, |
1221 | }, | |
1222 | }, | |
1223 | }; | |
1224 | ||
1225 | struct omap_hwmod am33xx_uart5_hwmod = { | |
1226 | .name = "uart5", | |
1227 | .class = &uart_class, | |
1228 | .clkdm_name = "l4ls_clkdm", | |
1229 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
1230 | .main_clk = "dpll_per_m2_div4_ck", | |
1231 | .prcm = { | |
1232 | .omap4 = { | |
26649467 AM |
1233 | .modulemode = MODULEMODE_SWCTRL, |
1234 | }, | |
1235 | }, | |
1236 | }; | |
1237 | ||
1238 | struct omap_hwmod am33xx_uart6_hwmod = { | |
1239 | .name = "uart6", | |
1240 | .class = &uart_class, | |
1241 | .clkdm_name = "l4ls_clkdm", | |
1242 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
1243 | .main_clk = "dpll_per_m2_div4_ck", | |
1244 | .prcm = { | |
1245 | .omap4 = { | |
26649467 AM |
1246 | .modulemode = MODULEMODE_SWCTRL, |
1247 | }, | |
1248 | }, | |
1249 | }; | |
1250 | ||
1251 | /* 'wd_timer' class */ | |
1252 | static struct omap_hwmod_class_sysconfig wdt_sysc = { | |
1253 | .rev_offs = 0x0, | |
1254 | .sysc_offs = 0x10, | |
1255 | .syss_offs = 0x14, | |
1256 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
1257 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1258 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1259 | SIDLE_SMART_WKUP), | |
1260 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1261 | }; | |
1262 | ||
1263 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { | |
1264 | .name = "wd_timer", | |
1265 | .sysc = &wdt_sysc, | |
1266 | .pre_shutdown = &omap2_wd_timer_disable, | |
1267 | }; | |
1268 | ||
1269 | /* | |
1270 | * XXX: device.c file uses hardcoded name for watchdog timer | |
1271 | * driver "wd_timer2, so we are also using same name as of now... | |
1272 | */ | |
1273 | struct omap_hwmod am33xx_wd_timer1_hwmod = { | |
1274 | .name = "wd_timer2", | |
1275 | .class = &am33xx_wd_timer_hwmod_class, | |
1276 | .clkdm_name = "l4_wkup_clkdm", | |
1277 | .flags = HWMOD_SWSUP_SIDLE, | |
1278 | .main_clk = "wdt1_fck", | |
1279 | .prcm = { | |
1280 | .omap4 = { | |
26649467 AM |
1281 | .modulemode = MODULEMODE_SWCTRL, |
1282 | }, | |
1283 | }, | |
1284 | }; | |
1c7e224d AM |
1285 | |
1286 | static void omap_hwmod_am33xx_clkctrl(void) | |
1287 | { | |
1288 | CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET); | |
1289 | CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET); | |
1290 | CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET); | |
1291 | CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET); | |
1292 | CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET); | |
1293 | CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET); | |
1294 | CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET); | |
1295 | CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET); | |
1296 | CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); | |
1297 | CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); | |
1298 | CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); | |
1299 | CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET); | |
1300 | CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET); | |
1301 | CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET); | |
1302 | CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET); | |
1303 | CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET); | |
1304 | CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); | |
1305 | CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET); | |
1306 | CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET); | |
1307 | CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET); | |
1308 | CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET); | |
1309 | CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET); | |
1310 | CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET); | |
1311 | CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); | |
1312 | CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); | |
1313 | CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET); | |
1314 | CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET); | |
1315 | CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET); | |
1316 | CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET); | |
1317 | CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET); | |
1318 | CLKCTRL(am33xx_smartreflex0_hwmod, | |
1319 | AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); | |
1320 | CLKCTRL(am33xx_smartreflex1_hwmod, | |
1321 | AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); | |
1322 | CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET); | |
1323 | CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); | |
1324 | CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); | |
1325 | CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); | |
1326 | CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); | |
ddb0d99d | 1327 | PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET); |
1c7e224d AM |
1328 | CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET); |
1329 | CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); | |
1330 | CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); | |
1331 | CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); | |
1332 | CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); | |
1333 | CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET); | |
1334 | CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET); | |
1335 | CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET); | |
1336 | CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET); | |
1337 | CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); | |
1338 | CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); | |
1339 | CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET); | |
1340 | CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); | |
1341 | CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); | |
1342 | CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); | |
1343 | CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); | |
1344 | CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); | |
d88d30e7 | 1345 | CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET); |
1c7e224d AM |
1346 | } |
1347 | ||
1348 | static void omap_hwmod_am33xx_rst(void) | |
1349 | { | |
1350 | RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET); | |
1351 | RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); | |
1352 | RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); | |
1353 | } | |
1354 | ||
1355 | void omap_hwmod_am33xx_reg(void) | |
1356 | { | |
1357 | omap_hwmod_am33xx_clkctrl(); | |
1358 | omap_hwmod_am33xx_rst(); | |
1359 | } | |
6913952f AM |
1360 | |
1361 | static void omap_hwmod_am43xx_clkctrl(void) | |
1362 | { | |
1363 | CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET); | |
1364 | CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET); | |
1365 | CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET); | |
1366 | CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET); | |
1367 | CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET); | |
1368 | CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET); | |
1369 | CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET); | |
1370 | CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET); | |
1371 | CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); | |
1372 | CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); | |
1373 | CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); | |
1374 | CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET); | |
1375 | CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET); | |
1376 | CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET); | |
1377 | CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET); | |
1378 | CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET); | |
1379 | CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); | |
1380 | CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET); | |
1381 | CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET); | |
1382 | CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET); | |
1383 | CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET); | |
1384 | CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET); | |
1385 | CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET); | |
1386 | CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); | |
1387 | CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET); | |
1388 | CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET); | |
1389 | CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET); | |
1390 | CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET); | |
1391 | CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET); | |
1392 | CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET); | |
1393 | CLKCTRL(am33xx_smartreflex0_hwmod, | |
1394 | AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); | |
1395 | CLKCTRL(am33xx_smartreflex1_hwmod, | |
1396 | AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); | |
1397 | CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET); | |
1398 | CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); | |
1399 | CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); | |
1400 | CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); | |
1401 | CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET); | |
1402 | CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET); | |
1403 | CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); | |
1404 | CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); | |
1405 | CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); | |
1406 | CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); | |
1407 | CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET); | |
1408 | CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET); | |
1409 | CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET); | |
1410 | CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET); | |
1411 | CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); | |
1412 | CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); | |
1413 | CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET); | |
1414 | CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); | |
1415 | CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); | |
1416 | CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); | |
1417 | CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); | |
1418 | CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); | |
d88d30e7 | 1419 | CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET); |
6913952f AM |
1420 | } |
1421 | ||
1422 | static void omap_hwmod_am43xx_rst(void) | |
1423 | { | |
1424 | RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET); | |
1425 | RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); | |
b00ccf5b | 1426 | RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET); |
6913952f AM |
1427 | RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); |
1428 | } | |
1429 | ||
1430 | void omap_hwmod_am43xx_reg(void) | |
1431 | { | |
1432 | omap_hwmod_am43xx_clkctrl(); | |
1433 | omap_hwmod_am43xx_rst(); | |
1434 | } |