Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
7359154e | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
7f904c78 | 21 | #include <plat/mcspi.h> |
de56dbb6 | 22 | #include <plat/l3_2xxx.h> |
02bfc030 | 23 | |
43b40992 PW |
24 | #include "omap_hwmod_common_data.h" |
25 | ||
02bfc030 | 26 | #include "prm-regbits-24xx.h" |
165e2161 | 27 | #include "cm-regbits-24xx.h" |
ff2516fb | 28 | #include "wd_timer.h" |
02bfc030 | 29 | |
7359154e PW |
30 | /* |
31 | * OMAP2430 hardware module integration data | |
32 | * | |
33 | * ALl of the data in this section should be autogeneratable from the | |
34 | * TI hardware database or other technical documentation. Data that | |
35 | * is driver-specific or driver-kernel integration-specific belongs | |
36 | * elsewhere. | |
37 | */ | |
38 | ||
02bfc030 | 39 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 40 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 41 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 42 | static struct omap_hwmod omap2430_l4_core_hwmod; |
de56dbb6 SG |
43 | static struct omap_hwmod omap2430_dss_core_hwmod; |
44 | static struct omap_hwmod omap2430_dss_dispc_hwmod; | |
45 | static struct omap_hwmod omap2430_dss_rfbi_hwmod; | |
46 | static struct omap_hwmod omap2430_dss_venc_hwmod; | |
165e2161 | 47 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
48 | static struct omap_hwmod omap2430_gpio1_hwmod; |
49 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
50 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
51 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
52 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 53 | static struct omap_hwmod omap2430_dma_system_hwmod; |
7f904c78 C |
54 | static struct omap_hwmod omap2430_mcspi1_hwmod; |
55 | static struct omap_hwmod omap2430_mcspi2_hwmod; | |
56 | static struct omap_hwmod omap2430_mcspi3_hwmod; | |
02bfc030 PW |
57 | |
58 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
59 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
60 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
61 | .slave = &omap2430_l4_core_hwmod, |
62 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
63 | }; | |
64 | ||
65 | /* MPU -> L3 interface */ | |
4a7cf90a | 66 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 67 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 68 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
69 | .user = OCP_USER_MPU, |
70 | }; | |
71 | ||
72 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
73 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
74 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
75 | }; |
76 | ||
de56dbb6 SG |
77 | /* DSS -> l3 */ |
78 | static struct omap_hwmod_ocp_if omap2430_dss__l3 = { | |
79 | .master = &omap2430_dss_core_hwmod, | |
80 | .slave = &omap2430_l3_main_hwmod, | |
81 | .fw = { | |
82 | .omap2 = { | |
83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
84 | .flags = OMAP_FIREWALL_L3, | |
85 | } | |
86 | }, | |
87 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
88 | }; | |
89 | ||
02bfc030 | 90 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
91 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
92 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
93 | }; |
94 | ||
95 | /* L3 */ | |
4a7cf90a | 96 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 97 | .name = "l3_main", |
43b40992 | 98 | .class = &l3_hwmod_class, |
4a7cf90a KH |
99 | .masters = omap2430_l3_main_masters, |
100 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
101 | .slaves = omap2430_l3_main_slaves, | |
102 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
104 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
105 | }; |
106 | ||
107 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
108 | static struct omap_hwmod omap2430_uart1_hwmod; |
109 | static struct omap_hwmod omap2430_uart2_hwmod; | |
110 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
111 | static struct omap_hwmod omap2430_i2c1_hwmod; |
112 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
113 | ||
44d02acf HH |
114 | static struct omap_hwmod omap2430_usbhsotg_hwmod; |
115 | ||
116 | /* l3_core -> usbhsotg interface */ | |
117 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
118 | .master = &omap2430_usbhsotg_hwmod, | |
119 | .slave = &omap2430_l3_main_hwmod, | |
120 | .clk = "core_l3_ck", | |
121 | .user = OCP_USER_MPU, | |
122 | }; | |
123 | ||
2004290f PW |
124 | /* I2C IP block address space length (in bytes) */ |
125 | #define OMAP2_I2C_AS_LEN 128 | |
126 | ||
127 | /* L4 CORE -> I2C1 interface */ | |
128 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | |
129 | { | |
130 | .pa_start = 0x48070000, | |
131 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
132 | .flags = ADDR_TYPE_RT, | |
133 | }, | |
134 | }; | |
135 | ||
136 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
137 | .master = &omap2430_l4_core_hwmod, | |
138 | .slave = &omap2430_i2c1_hwmod, | |
139 | .clk = "i2c1_ick", | |
140 | .addr = omap2430_i2c1_addr_space, | |
141 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | |
142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
143 | }; | |
144 | ||
145 | /* L4 CORE -> I2C2 interface */ | |
146 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | |
147 | { | |
148 | .pa_start = 0x48072000, | |
149 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
150 | .flags = ADDR_TYPE_RT, | |
151 | }, | |
152 | }; | |
153 | ||
154 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
155 | .master = &omap2430_l4_core_hwmod, | |
156 | .slave = &omap2430_i2c2_hwmod, | |
157 | .clk = "i2c2_ick", | |
158 | .addr = omap2430_i2c2_addr_space, | |
159 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | |
160 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
161 | }; | |
02bfc030 PW |
162 | |
163 | /* L4_CORE -> L4_WKUP interface */ | |
164 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
165 | .master = &omap2430_l4_core_hwmod, | |
166 | .slave = &omap2430_l4_wkup_hwmod, | |
167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
168 | }; | |
169 | ||
046465b7 KH |
170 | /* L4 CORE -> UART1 interface */ |
171 | static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { | |
172 | { | |
173 | .pa_start = OMAP2_UART1_BASE, | |
174 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, | |
175 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
180 | .master = &omap2430_l4_core_hwmod, | |
181 | .slave = &omap2430_uart1_hwmod, | |
182 | .clk = "uart1_ick", | |
183 | .addr = omap2430_uart1_addr_space, | |
184 | .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), | |
185 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
186 | }; | |
187 | ||
188 | /* L4 CORE -> UART2 interface */ | |
189 | static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { | |
190 | { | |
191 | .pa_start = OMAP2_UART2_BASE, | |
192 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, | |
193 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
194 | }, | |
195 | }; | |
196 | ||
197 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
198 | .master = &omap2430_l4_core_hwmod, | |
199 | .slave = &omap2430_uart2_hwmod, | |
200 | .clk = "uart2_ick", | |
201 | .addr = omap2430_uart2_addr_space, | |
202 | .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), | |
203 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
204 | }; | |
205 | ||
206 | /* L4 PER -> UART3 interface */ | |
207 | static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { | |
208 | { | |
209 | .pa_start = OMAP2_UART3_BASE, | |
210 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, | |
211 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
212 | }, | |
213 | }; | |
214 | ||
215 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
216 | .master = &omap2430_l4_core_hwmod, | |
217 | .slave = &omap2430_uart3_hwmod, | |
218 | .clk = "uart3_ick", | |
219 | .addr = omap2430_uart3_addr_space, | |
220 | .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), | |
221 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
222 | }; | |
223 | ||
44d02acf HH |
224 | /* |
225 | * usbhsotg interface data | |
226 | */ | |
227 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { | |
228 | { | |
229 | .pa_start = OMAP243X_HS_BASE, | |
230 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
231 | .flags = ADDR_TYPE_RT | |
232 | }, | |
233 | }; | |
234 | ||
235 | /* l4_core ->usbhsotg interface */ | |
236 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
237 | .master = &omap2430_l4_core_hwmod, | |
238 | .slave = &omap2430_usbhsotg_hwmod, | |
239 | .clk = "usb_l4_ick", | |
240 | .addr = omap2430_usbhsotg_addrs, | |
241 | .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), | |
242 | .user = OCP_USER_MPU, | |
243 | }; | |
244 | ||
245 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { | |
246 | &omap2430_usbhsotg__l3, | |
247 | }; | |
248 | ||
249 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { | |
250 | &omap2430_l4_core__usbhsotg, | |
251 | }; | |
252 | ||
02bfc030 PW |
253 | /* Slave interfaces on the L4_CORE interconnect */ |
254 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 255 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
256 | }; |
257 | ||
258 | /* Master interfaces on the L4_CORE interconnect */ | |
259 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
260 | &omap2430_l4_core__l4_wkup, | |
261 | }; | |
262 | ||
263 | /* L4 CORE */ | |
264 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 265 | .name = "l4_core", |
43b40992 | 266 | .class = &l4_hwmod_class, |
02bfc030 PW |
267 | .masters = omap2430_l4_core_masters, |
268 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
269 | .slaves = omap2430_l4_core_slaves, | |
270 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
271 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
272 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
273 | }; |
274 | ||
275 | /* Slave interfaces on the L4_WKUP interconnect */ | |
276 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
277 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
278 | &omap2_l4_core__uart1, |
279 | &omap2_l4_core__uart2, | |
280 | &omap2_l4_core__uart3, | |
02bfc030 PW |
281 | }; |
282 | ||
283 | /* Master interfaces on the L4_WKUP interconnect */ | |
284 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
285 | }; | |
286 | ||
7f904c78 C |
287 | /* l4 core -> mcspi1 interface */ |
288 | static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { | |
289 | { | |
290 | .pa_start = 0x48098000, | |
291 | .pa_end = 0x480980ff, | |
292 | .flags = ADDR_TYPE_RT, | |
293 | }, | |
294 | }; | |
295 | ||
296 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { | |
297 | .master = &omap2430_l4_core_hwmod, | |
298 | .slave = &omap2430_mcspi1_hwmod, | |
299 | .clk = "mcspi1_ick", | |
300 | .addr = omap2430_mcspi1_addr_space, | |
301 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), | |
302 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
303 | }; | |
304 | ||
305 | /* l4 core -> mcspi2 interface */ | |
306 | static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { | |
307 | { | |
308 | .pa_start = 0x4809a000, | |
309 | .pa_end = 0x4809a0ff, | |
310 | .flags = ADDR_TYPE_RT, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { | |
315 | .master = &omap2430_l4_core_hwmod, | |
316 | .slave = &omap2430_mcspi2_hwmod, | |
317 | .clk = "mcspi2_ick", | |
318 | .addr = omap2430_mcspi2_addr_space, | |
319 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), | |
320 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
321 | }; | |
322 | ||
323 | /* l4 core -> mcspi3 interface */ | |
324 | static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { | |
325 | { | |
326 | .pa_start = 0x480b8000, | |
327 | .pa_end = 0x480b80ff, | |
328 | .flags = ADDR_TYPE_RT, | |
329 | }, | |
330 | }; | |
331 | ||
332 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
333 | .master = &omap2430_l4_core_hwmod, | |
334 | .slave = &omap2430_mcspi3_hwmod, | |
335 | .clk = "mcspi3_ick", | |
336 | .addr = omap2430_mcspi3_addr_space, | |
337 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), | |
338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
339 | }; | |
340 | ||
02bfc030 PW |
341 | /* L4 WKUP */ |
342 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 343 | .name = "l4_wkup", |
43b40992 | 344 | .class = &l4_hwmod_class, |
02bfc030 PW |
345 | .masters = omap2430_l4_wkup_masters, |
346 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
347 | .slaves = omap2430_l4_wkup_slaves, | |
348 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
349 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
350 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
351 | }; |
352 | ||
353 | /* Master interfaces on the MPU device */ | |
354 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 355 | &omap2430_mpu__l3_main, |
02bfc030 PW |
356 | }; |
357 | ||
358 | /* MPU */ | |
359 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 360 | .name = "mpu", |
43b40992 | 361 | .class = &mpu_hwmod_class, |
50ebdac2 | 362 | .main_clk = "mpu_ck", |
02bfc030 PW |
363 | .masters = omap2430_mpu_masters, |
364 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
365 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
366 | }; | |
367 | ||
08072acf PW |
368 | /* |
369 | * IVA2_1 interface data | |
370 | */ | |
371 | ||
372 | /* IVA2 <- L3 interface */ | |
373 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
374 | .master = &omap2430_l3_main_hwmod, | |
375 | .slave = &omap2430_iva_hwmod, | |
376 | .clk = "dsp_fck", | |
377 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
378 | }; | |
379 | ||
380 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
381 | &omap2430_l3__iva, | |
382 | }; | |
383 | ||
384 | /* | |
385 | * IVA2 (IVA2) | |
386 | */ | |
387 | ||
388 | static struct omap_hwmod omap2430_iva_hwmod = { | |
389 | .name = "iva", | |
390 | .class = &iva_hwmod_class, | |
391 | .masters = omap2430_iva_masters, | |
392 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
393 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
394 | }; | |
395 | ||
165e2161 VC |
396 | /* l4_wkup -> wd_timer2 */ |
397 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
398 | { | |
399 | .pa_start = 0x49016000, | |
400 | .pa_end = 0x4901607f, | |
401 | .flags = ADDR_TYPE_RT | |
402 | }, | |
403 | }; | |
404 | ||
405 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
406 | .master = &omap2430_l4_wkup_hwmod, | |
407 | .slave = &omap2430_wd_timer2_hwmod, | |
408 | .clk = "mpu_wdt_ick", | |
409 | .addr = omap2430_wd_timer2_addrs, | |
410 | .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), | |
411 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
412 | }; | |
413 | ||
414 | /* | |
415 | * 'wd_timer' class | |
416 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
417 | * overflow condition | |
418 | */ | |
419 | ||
420 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
421 | .rev_offs = 0x0, | |
422 | .sysc_offs = 0x0010, | |
423 | .syss_offs = 0x0014, | |
424 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
425 | SYSC_HAS_AUTOIDLE), | |
426 | .sysc_fields = &omap_hwmod_sysc_type1, | |
427 | }; | |
428 | ||
429 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
ff2516fb PW |
430 | .name = "wd_timer", |
431 | .sysc = &omap2430_wd_timer_sysc, | |
432 | .pre_shutdown = &omap2_wd_timer_disable | |
165e2161 VC |
433 | }; |
434 | ||
435 | /* wd_timer2 */ | |
436 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
437 | &omap2430_l4_wkup__wd_timer2, | |
438 | }; | |
439 | ||
440 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
441 | .name = "wd_timer2", | |
442 | .class = &omap2430_wd_timer_hwmod_class, | |
443 | .main_clk = "mpu_wdt_fck", | |
444 | .prcm = { | |
445 | .omap2 = { | |
446 | .prcm_reg_id = 1, | |
447 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
448 | .module_offs = WKUP_MOD, | |
449 | .idlest_reg_id = 1, | |
450 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
451 | }, | |
452 | }, | |
453 | .slaves = omap2430_wd_timer2_slaves, | |
454 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
455 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
456 | }; | |
457 | ||
046465b7 KH |
458 | /* UART */ |
459 | ||
460 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
461 | .rev_offs = 0x50, | |
462 | .sysc_offs = 0x54, | |
463 | .syss_offs = 0x58, | |
464 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
465 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
466 | SYSC_HAS_AUTOIDLE), | |
467 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
468 | .sysc_fields = &omap_hwmod_sysc_type1, | |
469 | }; | |
470 | ||
471 | static struct omap_hwmod_class uart_class = { | |
472 | .name = "uart", | |
473 | .sysc = &uart_sysc, | |
474 | }; | |
475 | ||
476 | /* UART1 */ | |
477 | ||
478 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
479 | { .irq = INT_24XX_UART1_IRQ, }, | |
480 | }; | |
481 | ||
482 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
483 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
484 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
485 | }; | |
486 | ||
487 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { | |
488 | &omap2_l4_core__uart1, | |
489 | }; | |
490 | ||
491 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
492 | .name = "uart1", | |
493 | .mpu_irqs = uart1_mpu_irqs, | |
494 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
495 | .sdma_reqs = uart1_sdma_reqs, | |
496 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
497 | .main_clk = "uart1_fck", | |
498 | .prcm = { | |
499 | .omap2 = { | |
500 | .module_offs = CORE_MOD, | |
501 | .prcm_reg_id = 1, | |
502 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
503 | .idlest_reg_id = 1, | |
504 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
505 | }, | |
506 | }, | |
507 | .slaves = omap2430_uart1_slaves, | |
508 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
509 | .class = &uart_class, | |
510 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
511 | }; | |
512 | ||
513 | /* UART2 */ | |
514 | ||
515 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
516 | { .irq = INT_24XX_UART2_IRQ, }, | |
517 | }; | |
518 | ||
519 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
520 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
521 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
522 | }; | |
523 | ||
524 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { | |
525 | &omap2_l4_core__uart2, | |
526 | }; | |
527 | ||
528 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
529 | .name = "uart2", | |
530 | .mpu_irqs = uart2_mpu_irqs, | |
531 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
532 | .sdma_reqs = uart2_sdma_reqs, | |
533 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
534 | .main_clk = "uart2_fck", | |
535 | .prcm = { | |
536 | .omap2 = { | |
537 | .module_offs = CORE_MOD, | |
538 | .prcm_reg_id = 1, | |
539 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
540 | .idlest_reg_id = 1, | |
541 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
542 | }, | |
543 | }, | |
544 | .slaves = omap2430_uart2_slaves, | |
545 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
546 | .class = &uart_class, | |
547 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
548 | }; | |
549 | ||
550 | /* UART3 */ | |
551 | ||
552 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
553 | { .irq = INT_24XX_UART3_IRQ, }, | |
554 | }; | |
555 | ||
556 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
557 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
558 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
559 | }; | |
560 | ||
561 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { | |
562 | &omap2_l4_core__uart3, | |
563 | }; | |
564 | ||
565 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
566 | .name = "uart3", | |
567 | .mpu_irqs = uart3_mpu_irqs, | |
568 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
569 | .sdma_reqs = uart3_sdma_reqs, | |
570 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
571 | .main_clk = "uart3_fck", | |
572 | .prcm = { | |
573 | .omap2 = { | |
574 | .module_offs = CORE_MOD, | |
575 | .prcm_reg_id = 2, | |
576 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
577 | .idlest_reg_id = 2, | |
578 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
579 | }, | |
580 | }, | |
581 | .slaves = omap2430_uart3_slaves, | |
582 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
583 | .class = &uart_class, | |
584 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
585 | }; | |
586 | ||
de56dbb6 SG |
587 | /* |
588 | * 'dss' class | |
589 | * display sub-system | |
590 | */ | |
591 | ||
592 | static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { | |
593 | .rev_offs = 0x0000, | |
594 | .sysc_offs = 0x0010, | |
595 | .syss_offs = 0x0014, | |
596 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
597 | .sysc_fields = &omap_hwmod_sysc_type1, | |
598 | }; | |
599 | ||
600 | static struct omap_hwmod_class omap2430_dss_hwmod_class = { | |
601 | .name = "dss", | |
602 | .sysc = &omap2430_dss_sysc, | |
603 | }; | |
604 | ||
605 | /* dss */ | |
606 | static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { | |
607 | { .irq = 25 }, | |
608 | }; | |
609 | static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { | |
610 | { .name = "dispc", .dma_req = 5 }, | |
611 | }; | |
612 | ||
613 | /* dss */ | |
614 | /* dss master ports */ | |
615 | static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { | |
616 | &omap2430_dss__l3, | |
617 | }; | |
618 | ||
619 | static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { | |
620 | { | |
621 | .pa_start = 0x48050000, | |
622 | .pa_end = 0x480503FF, | |
623 | .flags = ADDR_TYPE_RT | |
624 | }, | |
625 | }; | |
626 | ||
627 | /* l4_core -> dss */ | |
628 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { | |
629 | .master = &omap2430_l4_core_hwmod, | |
630 | .slave = &omap2430_dss_core_hwmod, | |
631 | .clk = "dss_ick", | |
632 | .addr = omap2430_dss_addrs, | |
633 | .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), | |
634 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
635 | }; | |
636 | ||
637 | /* dss slave ports */ | |
638 | static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { | |
639 | &omap2430_l4_core__dss, | |
640 | }; | |
641 | ||
642 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
643 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
644 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
645 | }; | |
646 | ||
647 | static struct omap_hwmod omap2430_dss_core_hwmod = { | |
648 | .name = "dss_core", | |
649 | .class = &omap2430_dss_hwmod_class, | |
650 | .main_clk = "dss1_fck", /* instead of dss_fck */ | |
651 | .mpu_irqs = omap2430_dss_irqs, | |
652 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), | |
653 | .sdma_reqs = omap2430_dss_sdma_chs, | |
654 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), | |
655 | .prcm = { | |
656 | .omap2 = { | |
657 | .prcm_reg_id = 1, | |
658 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
659 | .module_offs = CORE_MOD, | |
660 | .idlest_reg_id = 1, | |
661 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
662 | }, | |
663 | }, | |
664 | .opt_clks = dss_opt_clks, | |
665 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
666 | .slaves = omap2430_dss_slaves, | |
667 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), | |
668 | .masters = omap2430_dss_masters, | |
669 | .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), | |
670 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
671 | .flags = HWMOD_NO_IDLEST, | |
672 | }; | |
673 | ||
674 | /* | |
675 | * 'dispc' class | |
676 | * display controller | |
677 | */ | |
678 | ||
679 | static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { | |
680 | .rev_offs = 0x0000, | |
681 | .sysc_offs = 0x0010, | |
682 | .syss_offs = 0x0014, | |
683 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
684 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
685 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
686 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
687 | .sysc_fields = &omap_hwmod_sysc_type1, | |
688 | }; | |
689 | ||
690 | static struct omap_hwmod_class omap2430_dispc_hwmod_class = { | |
691 | .name = "dispc", | |
692 | .sysc = &omap2430_dispc_sysc, | |
693 | }; | |
694 | ||
695 | static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { | |
696 | { | |
697 | .pa_start = 0x48050400, | |
698 | .pa_end = 0x480507FF, | |
699 | .flags = ADDR_TYPE_RT | |
700 | }, | |
701 | }; | |
702 | ||
703 | /* l4_core -> dss_dispc */ | |
704 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { | |
705 | .master = &omap2430_l4_core_hwmod, | |
706 | .slave = &omap2430_dss_dispc_hwmod, | |
707 | .clk = "dss_ick", | |
708 | .addr = omap2430_dss_dispc_addrs, | |
709 | .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), | |
710 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
711 | }; | |
712 | ||
713 | /* dss_dispc slave ports */ | |
714 | static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { | |
715 | &omap2430_l4_core__dss_dispc, | |
716 | }; | |
717 | ||
718 | static struct omap_hwmod omap2430_dss_dispc_hwmod = { | |
719 | .name = "dss_dispc", | |
720 | .class = &omap2430_dispc_hwmod_class, | |
721 | .main_clk = "dss1_fck", | |
722 | .prcm = { | |
723 | .omap2 = { | |
724 | .prcm_reg_id = 1, | |
725 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
726 | .module_offs = CORE_MOD, | |
727 | .idlest_reg_id = 1, | |
728 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
729 | }, | |
730 | }, | |
731 | .slaves = omap2430_dss_dispc_slaves, | |
732 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), | |
733 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
734 | .flags = HWMOD_NO_IDLEST, | |
735 | }; | |
736 | ||
737 | /* | |
738 | * 'rfbi' class | |
739 | * remote frame buffer interface | |
740 | */ | |
741 | ||
742 | static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { | |
743 | .rev_offs = 0x0000, | |
744 | .sysc_offs = 0x0010, | |
745 | .syss_offs = 0x0014, | |
746 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
747 | SYSC_HAS_AUTOIDLE), | |
748 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
749 | .sysc_fields = &omap_hwmod_sysc_type1, | |
750 | }; | |
751 | ||
752 | static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { | |
753 | .name = "rfbi", | |
754 | .sysc = &omap2430_rfbi_sysc, | |
755 | }; | |
756 | ||
757 | static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { | |
758 | { | |
759 | .pa_start = 0x48050800, | |
760 | .pa_end = 0x48050BFF, | |
761 | .flags = ADDR_TYPE_RT | |
762 | }, | |
763 | }; | |
764 | ||
765 | /* l4_core -> dss_rfbi */ | |
766 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { | |
767 | .master = &omap2430_l4_core_hwmod, | |
768 | .slave = &omap2430_dss_rfbi_hwmod, | |
769 | .clk = "dss_ick", | |
770 | .addr = omap2430_dss_rfbi_addrs, | |
771 | .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), | |
772 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
773 | }; | |
774 | ||
775 | /* dss_rfbi slave ports */ | |
776 | static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { | |
777 | &omap2430_l4_core__dss_rfbi, | |
778 | }; | |
779 | ||
780 | static struct omap_hwmod omap2430_dss_rfbi_hwmod = { | |
781 | .name = "dss_rfbi", | |
782 | .class = &omap2430_rfbi_hwmod_class, | |
783 | .main_clk = "dss1_fck", | |
784 | .prcm = { | |
785 | .omap2 = { | |
786 | .prcm_reg_id = 1, | |
787 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
788 | .module_offs = CORE_MOD, | |
789 | }, | |
790 | }, | |
791 | .slaves = omap2430_dss_rfbi_slaves, | |
792 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), | |
793 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
794 | .flags = HWMOD_NO_IDLEST, | |
795 | }; | |
796 | ||
797 | /* | |
798 | * 'venc' class | |
799 | * video encoder | |
800 | */ | |
801 | ||
802 | static struct omap_hwmod_class omap2430_venc_hwmod_class = { | |
803 | .name = "venc", | |
804 | }; | |
805 | ||
806 | /* dss_venc */ | |
807 | static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { | |
808 | { | |
809 | .pa_start = 0x48050C00, | |
810 | .pa_end = 0x48050FFF, | |
811 | .flags = ADDR_TYPE_RT | |
812 | }, | |
813 | }; | |
814 | ||
815 | /* l4_core -> dss_venc */ | |
816 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { | |
817 | .master = &omap2430_l4_core_hwmod, | |
818 | .slave = &omap2430_dss_venc_hwmod, | |
819 | .clk = "dss_54m_fck", | |
820 | .addr = omap2430_dss_venc_addrs, | |
821 | .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), | |
822 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
823 | }; | |
824 | ||
825 | /* dss_venc slave ports */ | |
826 | static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { | |
827 | &omap2430_l4_core__dss_venc, | |
828 | }; | |
829 | ||
830 | static struct omap_hwmod omap2430_dss_venc_hwmod = { | |
831 | .name = "dss_venc", | |
832 | .class = &omap2430_venc_hwmod_class, | |
833 | .main_clk = "dss1_fck", | |
834 | .prcm = { | |
835 | .omap2 = { | |
836 | .prcm_reg_id = 1, | |
837 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
838 | .module_offs = CORE_MOD, | |
839 | }, | |
840 | }, | |
841 | .slaves = omap2430_dss_venc_slaves, | |
842 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), | |
843 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
844 | .flags = HWMOD_NO_IDLEST, | |
845 | }; | |
846 | ||
2004290f PW |
847 | /* I2C common */ |
848 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
849 | .rev_offs = 0x00, | |
850 | .sysc_offs = 0x20, | |
851 | .syss_offs = 0x10, | |
852 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
853 | .sysc_fields = &omap_hwmod_sysc_type1, | |
854 | }; | |
855 | ||
856 | static struct omap_hwmod_class i2c_class = { | |
857 | .name = "i2c", | |
858 | .sysc = &i2c_sysc, | |
859 | }; | |
860 | ||
50ebb777 | 861 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f PW |
862 | .fifo_depth = 8, /* bytes */ |
863 | }; | |
864 | ||
50ebb777 BC |
865 | /* I2C1 */ |
866 | ||
2004290f PW |
867 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
868 | { .irq = INT_24XX_I2C1_IRQ, }, | |
869 | }; | |
870 | ||
871 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
872 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
873 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
874 | }; | |
875 | ||
876 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | |
877 | &omap2430_l4_core__i2c1, | |
878 | }; | |
879 | ||
880 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
881 | .name = "i2c1", | |
882 | .mpu_irqs = i2c1_mpu_irqs, | |
883 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
884 | .sdma_reqs = i2c1_sdma_reqs, | |
885 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
886 | .main_clk = "i2chs1_fck", | |
887 | .prcm = { | |
888 | .omap2 = { | |
889 | /* | |
890 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
891 | * I2CHS IP's do not follow the usual pattern. | |
892 | * prcm_reg_id alone cannot be used to program | |
893 | * the iclk and fclk. Needs to be handled using | |
894 | * additonal flags when clk handling is moved | |
895 | * to hwmod framework. | |
896 | */ | |
897 | .module_offs = CORE_MOD, | |
898 | .prcm_reg_id = 1, | |
899 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
900 | .idlest_reg_id = 1, | |
901 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
902 | }, | |
903 | }, | |
904 | .slaves = omap2430_i2c1_slaves, | |
905 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
906 | .class = &i2c_class, | |
50ebb777 | 907 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
908 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
909 | }; | |
910 | ||
911 | /* I2C2 */ | |
912 | ||
2004290f PW |
913 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
914 | { .irq = INT_24XX_I2C2_IRQ, }, | |
915 | }; | |
916 | ||
917 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
918 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
919 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
920 | }; | |
921 | ||
922 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | |
923 | &omap2430_l4_core__i2c2, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
927 | .name = "i2c2", | |
928 | .mpu_irqs = i2c2_mpu_irqs, | |
929 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
930 | .sdma_reqs = i2c2_sdma_reqs, | |
931 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
932 | .main_clk = "i2chs2_fck", | |
933 | .prcm = { | |
934 | .omap2 = { | |
935 | .module_offs = CORE_MOD, | |
936 | .prcm_reg_id = 1, | |
937 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
938 | .idlest_reg_id = 1, | |
939 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
940 | }, | |
941 | }, | |
942 | .slaves = omap2430_i2c2_slaves, | |
943 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
944 | .class = &i2c_class, | |
50ebb777 | 945 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
946 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
947 | }; | |
948 | ||
aeac0e44 VC |
949 | /* l4_wkup -> gpio1 */ |
950 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
951 | { | |
952 | .pa_start = 0x4900C000, | |
953 | .pa_end = 0x4900C1ff, | |
954 | .flags = ADDR_TYPE_RT | |
955 | }, | |
956 | }; | |
957 | ||
958 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
959 | .master = &omap2430_l4_wkup_hwmod, | |
960 | .slave = &omap2430_gpio1_hwmod, | |
961 | .clk = "gpios_ick", | |
962 | .addr = omap2430_gpio1_addr_space, | |
963 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | |
964 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
965 | }; | |
966 | ||
967 | /* l4_wkup -> gpio2 */ | |
968 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
969 | { | |
970 | .pa_start = 0x4900E000, | |
971 | .pa_end = 0x4900E1ff, | |
972 | .flags = ADDR_TYPE_RT | |
973 | }, | |
974 | }; | |
975 | ||
976 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
977 | .master = &omap2430_l4_wkup_hwmod, | |
978 | .slave = &omap2430_gpio2_hwmod, | |
979 | .clk = "gpios_ick", | |
980 | .addr = omap2430_gpio2_addr_space, | |
981 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | |
982 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
983 | }; | |
984 | ||
985 | /* l4_wkup -> gpio3 */ | |
986 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
987 | { | |
988 | .pa_start = 0x49010000, | |
989 | .pa_end = 0x490101ff, | |
990 | .flags = ADDR_TYPE_RT | |
991 | }, | |
992 | }; | |
993 | ||
994 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
995 | .master = &omap2430_l4_wkup_hwmod, | |
996 | .slave = &omap2430_gpio3_hwmod, | |
997 | .clk = "gpios_ick", | |
998 | .addr = omap2430_gpio3_addr_space, | |
999 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | |
1000 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1001 | }; | |
1002 | ||
1003 | /* l4_wkup -> gpio4 */ | |
1004 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
1005 | { | |
1006 | .pa_start = 0x49012000, | |
1007 | .pa_end = 0x490121ff, | |
1008 | .flags = ADDR_TYPE_RT | |
1009 | }, | |
1010 | }; | |
1011 | ||
1012 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
1013 | .master = &omap2430_l4_wkup_hwmod, | |
1014 | .slave = &omap2430_gpio4_hwmod, | |
1015 | .clk = "gpios_ick", | |
1016 | .addr = omap2430_gpio4_addr_space, | |
1017 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | |
1018 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1019 | }; | |
1020 | ||
1021 | /* l4_core -> gpio5 */ | |
1022 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
1023 | { | |
1024 | .pa_start = 0x480B6000, | |
1025 | .pa_end = 0x480B61ff, | |
1026 | .flags = ADDR_TYPE_RT | |
1027 | }, | |
1028 | }; | |
1029 | ||
1030 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
1031 | .master = &omap2430_l4_core_hwmod, | |
1032 | .slave = &omap2430_gpio5_hwmod, | |
1033 | .clk = "gpio5_ick", | |
1034 | .addr = omap2430_gpio5_addr_space, | |
1035 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | |
1036 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1037 | }; | |
1038 | ||
1039 | /* gpio dev_attr */ | |
1040 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1041 | .bank_width = 32, | |
1042 | .dbck_flag = false, | |
1043 | }; | |
1044 | ||
1045 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
1046 | .rev_offs = 0x0000, | |
1047 | .sysc_offs = 0x0010, | |
1048 | .syss_offs = 0x0014, | |
1049 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1050 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1051 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1052 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1053 | }; | |
1054 | ||
1055 | /* | |
1056 | * 'gpio' class | |
1057 | * general purpose io module | |
1058 | */ | |
1059 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
1060 | .name = "gpio", | |
1061 | .sysc = &omap243x_gpio_sysc, | |
1062 | .rev = 0, | |
1063 | }; | |
1064 | ||
1065 | /* gpio1 */ | |
1066 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | |
1067 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
1068 | }; | |
1069 | ||
1070 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | |
1071 | &omap2430_l4_wkup__gpio1, | |
1072 | }; | |
1073 | ||
1074 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
1075 | .name = "gpio1", | |
1076 | .mpu_irqs = omap243x_gpio1_irqs, | |
1077 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | |
1078 | .main_clk = "gpios_fck", | |
1079 | .prcm = { | |
1080 | .omap2 = { | |
1081 | .prcm_reg_id = 1, | |
1082 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1083 | .module_offs = WKUP_MOD, | |
1084 | .idlest_reg_id = 1, | |
1085 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1086 | }, | |
1087 | }, | |
1088 | .slaves = omap2430_gpio1_slaves, | |
1089 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
1090 | .class = &omap243x_gpio_hwmod_class, | |
1091 | .dev_attr = &gpio_dev_attr, | |
1092 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1093 | }; | |
1094 | ||
1095 | /* gpio2 */ | |
1096 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | |
1097 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
1098 | }; | |
1099 | ||
1100 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | |
1101 | &omap2430_l4_wkup__gpio2, | |
1102 | }; | |
1103 | ||
1104 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
1105 | .name = "gpio2", | |
1106 | .mpu_irqs = omap243x_gpio2_irqs, | |
1107 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | |
1108 | .main_clk = "gpios_fck", | |
1109 | .prcm = { | |
1110 | .omap2 = { | |
1111 | .prcm_reg_id = 1, | |
1112 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1113 | .module_offs = WKUP_MOD, | |
1114 | .idlest_reg_id = 1, | |
1115 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1116 | }, | |
1117 | }, | |
1118 | .slaves = omap2430_gpio2_slaves, | |
1119 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
1120 | .class = &omap243x_gpio_hwmod_class, | |
1121 | .dev_attr = &gpio_dev_attr, | |
1122 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1123 | }; | |
1124 | ||
1125 | /* gpio3 */ | |
1126 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | |
1127 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
1128 | }; | |
1129 | ||
1130 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | |
1131 | &omap2430_l4_wkup__gpio3, | |
1132 | }; | |
1133 | ||
1134 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
1135 | .name = "gpio3", | |
1136 | .mpu_irqs = omap243x_gpio3_irqs, | |
1137 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | |
1138 | .main_clk = "gpios_fck", | |
1139 | .prcm = { | |
1140 | .omap2 = { | |
1141 | .prcm_reg_id = 1, | |
1142 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1143 | .module_offs = WKUP_MOD, | |
1144 | .idlest_reg_id = 1, | |
1145 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1146 | }, | |
1147 | }, | |
1148 | .slaves = omap2430_gpio3_slaves, | |
1149 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
1150 | .class = &omap243x_gpio_hwmod_class, | |
1151 | .dev_attr = &gpio_dev_attr, | |
1152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1153 | }; | |
1154 | ||
1155 | /* gpio4 */ | |
1156 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | |
1157 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
1158 | }; | |
1159 | ||
1160 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | |
1161 | &omap2430_l4_wkup__gpio4, | |
1162 | }; | |
1163 | ||
1164 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
1165 | .name = "gpio4", | |
1166 | .mpu_irqs = omap243x_gpio4_irqs, | |
1167 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | |
1168 | .main_clk = "gpios_fck", | |
1169 | .prcm = { | |
1170 | .omap2 = { | |
1171 | .prcm_reg_id = 1, | |
1172 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1173 | .module_offs = WKUP_MOD, | |
1174 | .idlest_reg_id = 1, | |
1175 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1176 | }, | |
1177 | }, | |
1178 | .slaves = omap2430_gpio4_slaves, | |
1179 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
1180 | .class = &omap243x_gpio_hwmod_class, | |
1181 | .dev_attr = &gpio_dev_attr, | |
1182 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1183 | }; | |
1184 | ||
1185 | /* gpio5 */ | |
1186 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
1187 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
1188 | }; | |
1189 | ||
1190 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
1191 | &omap2430_l4_core__gpio5, | |
1192 | }; | |
1193 | ||
1194 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
1195 | .name = "gpio5", | |
1196 | .mpu_irqs = omap243x_gpio5_irqs, | |
1197 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | |
1198 | .main_clk = "gpio5_fck", | |
1199 | .prcm = { | |
1200 | .omap2 = { | |
1201 | .prcm_reg_id = 2, | |
1202 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1203 | .module_offs = CORE_MOD, | |
1204 | .idlest_reg_id = 2, | |
1205 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
1206 | }, | |
1207 | }, | |
1208 | .slaves = omap2430_gpio5_slaves, | |
1209 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
1210 | .class = &omap243x_gpio_hwmod_class, | |
1211 | .dev_attr = &gpio_dev_attr, | |
1212 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1213 | }; | |
1214 | ||
82cbd1ae MK |
1215 | /* dma_system */ |
1216 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
1217 | .rev_offs = 0x0000, | |
1218 | .sysc_offs = 0x002c, | |
1219 | .syss_offs = 0x0028, | |
1220 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
1221 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
1222 | SYSC_HAS_AUTOIDLE), | |
1223 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1224 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1225 | }; | |
1226 | ||
1227 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
1228 | .name = "dma", | |
1229 | .sysc = &omap2430_dma_sysc, | |
1230 | }; | |
1231 | ||
1232 | /* dma attributes */ | |
1233 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1234 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1235 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1236 | .lch_count = 32, | |
1237 | }; | |
1238 | ||
1239 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | |
1240 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
1241 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
1242 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
1243 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
1244 | }; | |
1245 | ||
1246 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | |
1247 | { | |
1248 | .pa_start = 0x48056000, | |
1249 | .pa_end = 0x4a0560ff, | |
1250 | .flags = ADDR_TYPE_RT | |
1251 | }, | |
1252 | }; | |
1253 | ||
1254 | /* dma_system -> L3 */ | |
1255 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
1256 | .master = &omap2430_dma_system_hwmod, | |
1257 | .slave = &omap2430_l3_main_hwmod, | |
1258 | .clk = "core_l3_ck", | |
1259 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1260 | }; | |
1261 | ||
1262 | /* dma_system master ports */ | |
1263 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
1264 | &omap2430_dma_system__l3, | |
1265 | }; | |
1266 | ||
1267 | /* l4_core -> dma_system */ | |
1268 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
1269 | .master = &omap2430_l4_core_hwmod, | |
1270 | .slave = &omap2430_dma_system_hwmod, | |
1271 | .clk = "sdma_ick", | |
1272 | .addr = omap2430_dma_system_addrs, | |
1273 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | |
1274 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1275 | }; | |
1276 | ||
1277 | /* dma_system slave ports */ | |
1278 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
1279 | &omap2430_l4_core__dma_system, | |
1280 | }; | |
1281 | ||
1282 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
1283 | .name = "dma", | |
1284 | .class = &omap2430_dma_hwmod_class, | |
1285 | .mpu_irqs = omap2430_dma_system_irqs, | |
1286 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | |
1287 | .main_clk = "core_l3_ck", | |
1288 | .slaves = omap2430_dma_system_slaves, | |
1289 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
1290 | .masters = omap2430_dma_system_masters, | |
1291 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
1292 | .dev_attr = &dma_dev_attr, | |
1293 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1294 | .flags = HWMOD_NO_IDLEST, | |
1295 | }; | |
1296 | ||
7f904c78 C |
1297 | /* |
1298 | * 'mcspi' class | |
1299 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1300 | * bus | |
1301 | */ | |
1302 | ||
1303 | static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { | |
1304 | .rev_offs = 0x0000, | |
1305 | .sysc_offs = 0x0010, | |
1306 | .syss_offs = 0x0014, | |
1307 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1308 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1309 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1310 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1311 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1312 | }; | |
1313 | ||
1314 | static struct omap_hwmod_class omap2430_mcspi_class = { | |
1315 | .name = "mcspi", | |
1316 | .sysc = &omap2430_mcspi_sysc, | |
1317 | .rev = OMAP2_MCSPI_REV, | |
1318 | }; | |
1319 | ||
1320 | /* mcspi1 */ | |
1321 | static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { | |
1322 | { .irq = 65 }, | |
1323 | }; | |
1324 | ||
1325 | static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { | |
1326 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ | |
1327 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ | |
1328 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ | |
1329 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ | |
1330 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ | |
1331 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ | |
1332 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ | |
1333 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ | |
1334 | }; | |
1335 | ||
1336 | static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { | |
1337 | &omap2430_l4_core__mcspi1, | |
1338 | }; | |
1339 | ||
1340 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1341 | .num_chipselect = 4, | |
1342 | }; | |
1343 | ||
1344 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
1345 | .name = "mcspi1_hwmod", | |
1346 | .mpu_irqs = omap2430_mcspi1_mpu_irqs, | |
1347 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), | |
1348 | .sdma_reqs = omap2430_mcspi1_sdma_reqs, | |
1349 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), | |
1350 | .main_clk = "mcspi1_fck", | |
1351 | .prcm = { | |
1352 | .omap2 = { | |
1353 | .module_offs = CORE_MOD, | |
1354 | .prcm_reg_id = 1, | |
1355 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1356 | .idlest_reg_id = 1, | |
1357 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1358 | }, | |
1359 | }, | |
1360 | .slaves = omap2430_mcspi1_slaves, | |
1361 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), | |
1362 | .class = &omap2430_mcspi_class, | |
1363 | .dev_attr = &omap_mcspi1_dev_attr, | |
1364 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1365 | }; | |
1366 | ||
1367 | /* mcspi2 */ | |
1368 | static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { | |
1369 | { .irq = 66 }, | |
1370 | }; | |
1371 | ||
1372 | static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { | |
1373 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ | |
1374 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ | |
1375 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ | |
1376 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ | |
1377 | }; | |
1378 | ||
1379 | static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { | |
1380 | &omap2430_l4_core__mcspi2, | |
1381 | }; | |
1382 | ||
1383 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1384 | .num_chipselect = 2, | |
1385 | }; | |
1386 | ||
1387 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
1388 | .name = "mcspi2_hwmod", | |
1389 | .mpu_irqs = omap2430_mcspi2_mpu_irqs, | |
1390 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), | |
1391 | .sdma_reqs = omap2430_mcspi2_sdma_reqs, | |
1392 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), | |
1393 | .main_clk = "mcspi2_fck", | |
1394 | .prcm = { | |
1395 | .omap2 = { | |
1396 | .module_offs = CORE_MOD, | |
1397 | .prcm_reg_id = 1, | |
1398 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1399 | .idlest_reg_id = 1, | |
1400 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1401 | }, | |
1402 | }, | |
1403 | .slaves = omap2430_mcspi2_slaves, | |
1404 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), | |
1405 | .class = &omap2430_mcspi_class, | |
1406 | .dev_attr = &omap_mcspi2_dev_attr, | |
1407 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1408 | }; | |
1409 | ||
1410 | /* mcspi3 */ | |
1411 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
1412 | { .irq = 91 }, | |
1413 | }; | |
1414 | ||
1415 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
1416 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
1417 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
1418 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
1419 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
1420 | }; | |
1421 | ||
1422 | static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { | |
1423 | &omap2430_l4_core__mcspi3, | |
1424 | }; | |
1425 | ||
1426 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1427 | .num_chipselect = 2, | |
1428 | }; | |
1429 | ||
1430 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
1431 | .name = "mcspi3_hwmod", | |
1432 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, | |
1433 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), | |
1434 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, | |
1435 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), | |
1436 | .main_clk = "mcspi3_fck", | |
1437 | .prcm = { | |
1438 | .omap2 = { | |
1439 | .module_offs = CORE_MOD, | |
1440 | .prcm_reg_id = 2, | |
1441 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1442 | .idlest_reg_id = 2, | |
1443 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
1444 | }, | |
1445 | }, | |
1446 | .slaves = omap2430_mcspi3_slaves, | |
1447 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), | |
1448 | .class = &omap2430_mcspi_class, | |
1449 | .dev_attr = &omap_mcspi3_dev_attr, | |
1450 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1451 | }; | |
1452 | ||
44d02acf HH |
1453 | /* |
1454 | * usbhsotg | |
1455 | */ | |
1456 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { | |
1457 | .rev_offs = 0x0400, | |
1458 | .sysc_offs = 0x0404, | |
1459 | .syss_offs = 0x0408, | |
1460 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1461 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1462 | SYSC_HAS_AUTOIDLE), | |
1463 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1464 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1465 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1466 | }; | |
1467 | ||
1468 | static struct omap_hwmod_class usbotg_class = { | |
1469 | .name = "usbotg", | |
1470 | .sysc = &omap2430_usbhsotg_sysc, | |
1471 | }; | |
1472 | ||
1473 | /* usb_otg_hs */ | |
1474 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
1475 | ||
1476 | { .name = "mc", .irq = 92 }, | |
1477 | { .name = "dma", .irq = 93 }, | |
1478 | }; | |
1479 | ||
1480 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
1481 | .name = "usb_otg_hs", | |
1482 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
1483 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), | |
1484 | .main_clk = "usbhs_ick", | |
1485 | .prcm = { | |
1486 | .omap2 = { | |
1487 | .prcm_reg_id = 1, | |
1488 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
1489 | .module_offs = CORE_MOD, | |
1490 | .idlest_reg_id = 1, | |
1491 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
1492 | }, | |
1493 | }, | |
1494 | .masters = omap2430_usbhsotg_masters, | |
1495 | .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), | |
1496 | .slaves = omap2430_usbhsotg_slaves, | |
1497 | .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), | |
1498 | .class = &usbotg_class, | |
1499 | /* | |
1500 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1501 | * broken when autoidle is enabled | |
1502 | * workaround is to disable the autoidle bit at module level. | |
1503 | */ | |
1504 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1505 | | HWMOD_SWSUP_MSTANDBY, | |
1506 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
1507 | }; | |
1508 | ||
04aa67de TL |
1509 | |
1510 | ||
02bfc030 | 1511 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 1512 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
1513 | &omap2430_l4_core_hwmod, |
1514 | &omap2430_l4_wkup_hwmod, | |
1515 | &omap2430_mpu_hwmod, | |
08072acf | 1516 | &omap2430_iva_hwmod, |
165e2161 | 1517 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
1518 | &omap2430_uart1_hwmod, |
1519 | &omap2430_uart2_hwmod, | |
1520 | &omap2430_uart3_hwmod, | |
de56dbb6 SG |
1521 | /* dss class */ |
1522 | &omap2430_dss_core_hwmod, | |
1523 | &omap2430_dss_dispc_hwmod, | |
1524 | &omap2430_dss_rfbi_hwmod, | |
1525 | &omap2430_dss_venc_hwmod, | |
1526 | /* i2c class */ | |
2004290f PW |
1527 | &omap2430_i2c1_hwmod, |
1528 | &omap2430_i2c2_hwmod, | |
aeac0e44 VC |
1529 | |
1530 | /* gpio class */ | |
1531 | &omap2430_gpio1_hwmod, | |
1532 | &omap2430_gpio2_hwmod, | |
1533 | &omap2430_gpio3_hwmod, | |
1534 | &omap2430_gpio4_hwmod, | |
1535 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
1536 | |
1537 | /* dma_system class*/ | |
1538 | &omap2430_dma_system_hwmod, | |
7f904c78 C |
1539 | |
1540 | /* mcspi class */ | |
1541 | &omap2430_mcspi1_hwmod, | |
1542 | &omap2430_mcspi2_hwmod, | |
1543 | &omap2430_mcspi3_hwmod, | |
04aa67de | 1544 | |
44d02acf HH |
1545 | /* usbotg class*/ |
1546 | &omap2430_usbhsotg_hwmod, | |
04aa67de | 1547 | |
02bfc030 PW |
1548 | NULL, |
1549 | }; | |
1550 | ||
7359154e PW |
1551 | int __init omap2430_hwmod_init(void) |
1552 | { | |
1553 | return omap_hwmod_init(omap2430_hwmods); | |
1554 | } |