Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
7359154e | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
7f904c78 | 21 | #include <plat/mcspi.h> |
02bfc030 | 22 | |
43b40992 PW |
23 | #include "omap_hwmod_common_data.h" |
24 | ||
02bfc030 | 25 | #include "prm-regbits-24xx.h" |
165e2161 | 26 | #include "cm-regbits-24xx.h" |
ff2516fb | 27 | #include "wd_timer.h" |
02bfc030 | 28 | |
7359154e PW |
29 | /* |
30 | * OMAP2430 hardware module integration data | |
31 | * | |
32 | * ALl of the data in this section should be autogeneratable from the | |
33 | * TI hardware database or other technical documentation. Data that | |
34 | * is driver-specific or driver-kernel integration-specific belongs | |
35 | * elsewhere. | |
36 | */ | |
37 | ||
02bfc030 | 38 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 39 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 40 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 41 | static struct omap_hwmod omap2430_l4_core_hwmod; |
165e2161 | 42 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
43 | static struct omap_hwmod omap2430_gpio1_hwmod; |
44 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
45 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
46 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
47 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 48 | static struct omap_hwmod omap2430_dma_system_hwmod; |
7f904c78 C |
49 | static struct omap_hwmod omap2430_mcspi1_hwmod; |
50 | static struct omap_hwmod omap2430_mcspi2_hwmod; | |
51 | static struct omap_hwmod omap2430_mcspi3_hwmod; | |
02bfc030 PW |
52 | |
53 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
54 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
55 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
56 | .slave = &omap2430_l4_core_hwmod, |
57 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
58 | }; | |
59 | ||
60 | /* MPU -> L3 interface */ | |
4a7cf90a | 61 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 62 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 63 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
64 | .user = OCP_USER_MPU, |
65 | }; | |
66 | ||
67 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
68 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
69 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
70 | }; |
71 | ||
72 | /* Master interfaces on the L3 interconnect */ | |
4a7cf90a KH |
73 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
74 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
75 | }; |
76 | ||
77 | /* L3 */ | |
4a7cf90a | 78 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 79 | .name = "l3_main", |
43b40992 | 80 | .class = &l3_hwmod_class, |
4a7cf90a KH |
81 | .masters = omap2430_l3_main_masters, |
82 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
83 | .slaves = omap2430_l3_main_slaves, | |
84 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
85 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
86 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
87 | }; |
88 | ||
89 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
90 | static struct omap_hwmod omap2430_uart1_hwmod; |
91 | static struct omap_hwmod omap2430_uart2_hwmod; | |
92 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
93 | static struct omap_hwmod omap2430_i2c1_hwmod; |
94 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
95 | ||
44d02acf HH |
96 | static struct omap_hwmod omap2430_usbhsotg_hwmod; |
97 | ||
98 | /* l3_core -> usbhsotg interface */ | |
99 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
100 | .master = &omap2430_usbhsotg_hwmod, | |
101 | .slave = &omap2430_l3_main_hwmod, | |
102 | .clk = "core_l3_ck", | |
103 | .user = OCP_USER_MPU, | |
104 | }; | |
105 | ||
2004290f PW |
106 | /* I2C IP block address space length (in bytes) */ |
107 | #define OMAP2_I2C_AS_LEN 128 | |
108 | ||
109 | /* L4 CORE -> I2C1 interface */ | |
110 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | |
111 | { | |
112 | .pa_start = 0x48070000, | |
113 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
114 | .flags = ADDR_TYPE_RT, | |
115 | }, | |
116 | }; | |
117 | ||
118 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
119 | .master = &omap2430_l4_core_hwmod, | |
120 | .slave = &omap2430_i2c1_hwmod, | |
121 | .clk = "i2c1_ick", | |
122 | .addr = omap2430_i2c1_addr_space, | |
123 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | |
124 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
125 | }; | |
126 | ||
127 | /* L4 CORE -> I2C2 interface */ | |
128 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | |
129 | { | |
130 | .pa_start = 0x48072000, | |
131 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
132 | .flags = ADDR_TYPE_RT, | |
133 | }, | |
134 | }; | |
135 | ||
136 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
137 | .master = &omap2430_l4_core_hwmod, | |
138 | .slave = &omap2430_i2c2_hwmod, | |
139 | .clk = "i2c2_ick", | |
140 | .addr = omap2430_i2c2_addr_space, | |
141 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | |
142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
143 | }; | |
02bfc030 PW |
144 | |
145 | /* L4_CORE -> L4_WKUP interface */ | |
146 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
147 | .master = &omap2430_l4_core_hwmod, | |
148 | .slave = &omap2430_l4_wkup_hwmod, | |
149 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
150 | }; | |
151 | ||
046465b7 KH |
152 | /* L4 CORE -> UART1 interface */ |
153 | static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { | |
154 | { | |
155 | .pa_start = OMAP2_UART1_BASE, | |
156 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, | |
157 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
158 | }, | |
159 | }; | |
160 | ||
161 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
162 | .master = &omap2430_l4_core_hwmod, | |
163 | .slave = &omap2430_uart1_hwmod, | |
164 | .clk = "uart1_ick", | |
165 | .addr = omap2430_uart1_addr_space, | |
166 | .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), | |
167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
168 | }; | |
169 | ||
170 | /* L4 CORE -> UART2 interface */ | |
171 | static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { | |
172 | { | |
173 | .pa_start = OMAP2_UART2_BASE, | |
174 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, | |
175 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
180 | .master = &omap2430_l4_core_hwmod, | |
181 | .slave = &omap2430_uart2_hwmod, | |
182 | .clk = "uart2_ick", | |
183 | .addr = omap2430_uart2_addr_space, | |
184 | .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), | |
185 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
186 | }; | |
187 | ||
188 | /* L4 PER -> UART3 interface */ | |
189 | static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { | |
190 | { | |
191 | .pa_start = OMAP2_UART3_BASE, | |
192 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, | |
193 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
194 | }, | |
195 | }; | |
196 | ||
197 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
198 | .master = &omap2430_l4_core_hwmod, | |
199 | .slave = &omap2430_uart3_hwmod, | |
200 | .clk = "uart3_ick", | |
201 | .addr = omap2430_uart3_addr_space, | |
202 | .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), | |
203 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
204 | }; | |
205 | ||
44d02acf HH |
206 | /* |
207 | * usbhsotg interface data | |
208 | */ | |
209 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { | |
210 | { | |
211 | .pa_start = OMAP243X_HS_BASE, | |
212 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
213 | .flags = ADDR_TYPE_RT | |
214 | }, | |
215 | }; | |
216 | ||
217 | /* l4_core ->usbhsotg interface */ | |
218 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
219 | .master = &omap2430_l4_core_hwmod, | |
220 | .slave = &omap2430_usbhsotg_hwmod, | |
221 | .clk = "usb_l4_ick", | |
222 | .addr = omap2430_usbhsotg_addrs, | |
223 | .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), | |
224 | .user = OCP_USER_MPU, | |
225 | }; | |
226 | ||
227 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { | |
228 | &omap2430_usbhsotg__l3, | |
229 | }; | |
230 | ||
231 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { | |
232 | &omap2430_l4_core__usbhsotg, | |
233 | }; | |
234 | ||
02bfc030 PW |
235 | /* Slave interfaces on the L4_CORE interconnect */ |
236 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 237 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
238 | }; |
239 | ||
240 | /* Master interfaces on the L4_CORE interconnect */ | |
241 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
242 | &omap2430_l4_core__l4_wkup, | |
243 | }; | |
244 | ||
245 | /* L4 CORE */ | |
246 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 247 | .name = "l4_core", |
43b40992 | 248 | .class = &l4_hwmod_class, |
02bfc030 PW |
249 | .masters = omap2430_l4_core_masters, |
250 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
251 | .slaves = omap2430_l4_core_slaves, | |
252 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
253 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
254 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
255 | }; |
256 | ||
257 | /* Slave interfaces on the L4_WKUP interconnect */ | |
258 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
259 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
260 | &omap2_l4_core__uart1, |
261 | &omap2_l4_core__uart2, | |
262 | &omap2_l4_core__uart3, | |
02bfc030 PW |
263 | }; |
264 | ||
265 | /* Master interfaces on the L4_WKUP interconnect */ | |
266 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
267 | }; | |
268 | ||
7f904c78 C |
269 | /* l4 core -> mcspi1 interface */ |
270 | static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { | |
271 | { | |
272 | .pa_start = 0x48098000, | |
273 | .pa_end = 0x480980ff, | |
274 | .flags = ADDR_TYPE_RT, | |
275 | }, | |
276 | }; | |
277 | ||
278 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { | |
279 | .master = &omap2430_l4_core_hwmod, | |
280 | .slave = &omap2430_mcspi1_hwmod, | |
281 | .clk = "mcspi1_ick", | |
282 | .addr = omap2430_mcspi1_addr_space, | |
283 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), | |
284 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
285 | }; | |
286 | ||
287 | /* l4 core -> mcspi2 interface */ | |
288 | static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { | |
289 | { | |
290 | .pa_start = 0x4809a000, | |
291 | .pa_end = 0x4809a0ff, | |
292 | .flags = ADDR_TYPE_RT, | |
293 | }, | |
294 | }; | |
295 | ||
296 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { | |
297 | .master = &omap2430_l4_core_hwmod, | |
298 | .slave = &omap2430_mcspi2_hwmod, | |
299 | .clk = "mcspi2_ick", | |
300 | .addr = omap2430_mcspi2_addr_space, | |
301 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), | |
302 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
303 | }; | |
304 | ||
305 | /* l4 core -> mcspi3 interface */ | |
306 | static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { | |
307 | { | |
308 | .pa_start = 0x480b8000, | |
309 | .pa_end = 0x480b80ff, | |
310 | .flags = ADDR_TYPE_RT, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
315 | .master = &omap2430_l4_core_hwmod, | |
316 | .slave = &omap2430_mcspi3_hwmod, | |
317 | .clk = "mcspi3_ick", | |
318 | .addr = omap2430_mcspi3_addr_space, | |
319 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), | |
320 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
321 | }; | |
322 | ||
02bfc030 PW |
323 | /* L4 WKUP */ |
324 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 325 | .name = "l4_wkup", |
43b40992 | 326 | .class = &l4_hwmod_class, |
02bfc030 PW |
327 | .masters = omap2430_l4_wkup_masters, |
328 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
329 | .slaves = omap2430_l4_wkup_slaves, | |
330 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
331 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
332 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
333 | }; |
334 | ||
335 | /* Master interfaces on the MPU device */ | |
336 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 337 | &omap2430_mpu__l3_main, |
02bfc030 PW |
338 | }; |
339 | ||
340 | /* MPU */ | |
341 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 342 | .name = "mpu", |
43b40992 | 343 | .class = &mpu_hwmod_class, |
50ebdac2 | 344 | .main_clk = "mpu_ck", |
02bfc030 PW |
345 | .masters = omap2430_mpu_masters, |
346 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
347 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
348 | }; | |
349 | ||
08072acf PW |
350 | /* |
351 | * IVA2_1 interface data | |
352 | */ | |
353 | ||
354 | /* IVA2 <- L3 interface */ | |
355 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
356 | .master = &omap2430_l3_main_hwmod, | |
357 | .slave = &omap2430_iva_hwmod, | |
358 | .clk = "dsp_fck", | |
359 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
360 | }; | |
361 | ||
362 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
363 | &omap2430_l3__iva, | |
364 | }; | |
365 | ||
366 | /* | |
367 | * IVA2 (IVA2) | |
368 | */ | |
369 | ||
370 | static struct omap_hwmod omap2430_iva_hwmod = { | |
371 | .name = "iva", | |
372 | .class = &iva_hwmod_class, | |
373 | .masters = omap2430_iva_masters, | |
374 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
375 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
376 | }; | |
377 | ||
165e2161 VC |
378 | /* l4_wkup -> wd_timer2 */ |
379 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
380 | { | |
381 | .pa_start = 0x49016000, | |
382 | .pa_end = 0x4901607f, | |
383 | .flags = ADDR_TYPE_RT | |
384 | }, | |
385 | }; | |
386 | ||
387 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
388 | .master = &omap2430_l4_wkup_hwmod, | |
389 | .slave = &omap2430_wd_timer2_hwmod, | |
390 | .clk = "mpu_wdt_ick", | |
391 | .addr = omap2430_wd_timer2_addrs, | |
392 | .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), | |
393 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
394 | }; | |
395 | ||
396 | /* | |
397 | * 'wd_timer' class | |
398 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
399 | * overflow condition | |
400 | */ | |
401 | ||
402 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
403 | .rev_offs = 0x0, | |
404 | .sysc_offs = 0x0010, | |
405 | .syss_offs = 0x0014, | |
406 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
407 | SYSC_HAS_AUTOIDLE), | |
408 | .sysc_fields = &omap_hwmod_sysc_type1, | |
409 | }; | |
410 | ||
411 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
ff2516fb PW |
412 | .name = "wd_timer", |
413 | .sysc = &omap2430_wd_timer_sysc, | |
414 | .pre_shutdown = &omap2_wd_timer_disable | |
165e2161 VC |
415 | }; |
416 | ||
417 | /* wd_timer2 */ | |
418 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
419 | &omap2430_l4_wkup__wd_timer2, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
423 | .name = "wd_timer2", | |
424 | .class = &omap2430_wd_timer_hwmod_class, | |
425 | .main_clk = "mpu_wdt_fck", | |
426 | .prcm = { | |
427 | .omap2 = { | |
428 | .prcm_reg_id = 1, | |
429 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
430 | .module_offs = WKUP_MOD, | |
431 | .idlest_reg_id = 1, | |
432 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
433 | }, | |
434 | }, | |
435 | .slaves = omap2430_wd_timer2_slaves, | |
436 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
437 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
438 | }; | |
439 | ||
046465b7 KH |
440 | /* UART */ |
441 | ||
442 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
443 | .rev_offs = 0x50, | |
444 | .sysc_offs = 0x54, | |
445 | .syss_offs = 0x58, | |
446 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
447 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
448 | SYSC_HAS_AUTOIDLE), | |
449 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
450 | .sysc_fields = &omap_hwmod_sysc_type1, | |
451 | }; | |
452 | ||
453 | static struct omap_hwmod_class uart_class = { | |
454 | .name = "uart", | |
455 | .sysc = &uart_sysc, | |
456 | }; | |
457 | ||
458 | /* UART1 */ | |
459 | ||
460 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
461 | { .irq = INT_24XX_UART1_IRQ, }, | |
462 | }; | |
463 | ||
464 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
465 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
466 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
467 | }; | |
468 | ||
469 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { | |
470 | &omap2_l4_core__uart1, | |
471 | }; | |
472 | ||
473 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
474 | .name = "uart1", | |
475 | .mpu_irqs = uart1_mpu_irqs, | |
476 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
477 | .sdma_reqs = uart1_sdma_reqs, | |
478 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
479 | .main_clk = "uart1_fck", | |
480 | .prcm = { | |
481 | .omap2 = { | |
482 | .module_offs = CORE_MOD, | |
483 | .prcm_reg_id = 1, | |
484 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
485 | .idlest_reg_id = 1, | |
486 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
487 | }, | |
488 | }, | |
489 | .slaves = omap2430_uart1_slaves, | |
490 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
491 | .class = &uart_class, | |
492 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
493 | }; | |
494 | ||
495 | /* UART2 */ | |
496 | ||
497 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
498 | { .irq = INT_24XX_UART2_IRQ, }, | |
499 | }; | |
500 | ||
501 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
502 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
503 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
504 | }; | |
505 | ||
506 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { | |
507 | &omap2_l4_core__uart2, | |
508 | }; | |
509 | ||
510 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
511 | .name = "uart2", | |
512 | .mpu_irqs = uart2_mpu_irqs, | |
513 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
514 | .sdma_reqs = uart2_sdma_reqs, | |
515 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
516 | .main_clk = "uart2_fck", | |
517 | .prcm = { | |
518 | .omap2 = { | |
519 | .module_offs = CORE_MOD, | |
520 | .prcm_reg_id = 1, | |
521 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
522 | .idlest_reg_id = 1, | |
523 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
524 | }, | |
525 | }, | |
526 | .slaves = omap2430_uart2_slaves, | |
527 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
528 | .class = &uart_class, | |
529 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
530 | }; | |
531 | ||
532 | /* UART3 */ | |
533 | ||
534 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
535 | { .irq = INT_24XX_UART3_IRQ, }, | |
536 | }; | |
537 | ||
538 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
539 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
540 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
541 | }; | |
542 | ||
543 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { | |
544 | &omap2_l4_core__uart3, | |
545 | }; | |
546 | ||
547 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
548 | .name = "uart3", | |
549 | .mpu_irqs = uart3_mpu_irqs, | |
550 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
551 | .sdma_reqs = uart3_sdma_reqs, | |
552 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
553 | .main_clk = "uart3_fck", | |
554 | .prcm = { | |
555 | .omap2 = { | |
556 | .module_offs = CORE_MOD, | |
557 | .prcm_reg_id = 2, | |
558 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
559 | .idlest_reg_id = 2, | |
560 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
561 | }, | |
562 | }, | |
563 | .slaves = omap2430_uart3_slaves, | |
564 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
565 | .class = &uart_class, | |
566 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
567 | }; | |
568 | ||
2004290f PW |
569 | /* I2C common */ |
570 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
571 | .rev_offs = 0x00, | |
572 | .sysc_offs = 0x20, | |
573 | .syss_offs = 0x10, | |
574 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
575 | .sysc_fields = &omap_hwmod_sysc_type1, | |
576 | }; | |
577 | ||
578 | static struct omap_hwmod_class i2c_class = { | |
579 | .name = "i2c", | |
580 | .sysc = &i2c_sysc, | |
581 | }; | |
582 | ||
50ebb777 | 583 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f PW |
584 | .fifo_depth = 8, /* bytes */ |
585 | }; | |
586 | ||
50ebb777 BC |
587 | /* I2C1 */ |
588 | ||
2004290f PW |
589 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
590 | { .irq = INT_24XX_I2C1_IRQ, }, | |
591 | }; | |
592 | ||
593 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
594 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
595 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
596 | }; | |
597 | ||
598 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | |
599 | &omap2430_l4_core__i2c1, | |
600 | }; | |
601 | ||
602 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
603 | .name = "i2c1", | |
604 | .mpu_irqs = i2c1_mpu_irqs, | |
605 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
606 | .sdma_reqs = i2c1_sdma_reqs, | |
607 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
608 | .main_clk = "i2chs1_fck", | |
609 | .prcm = { | |
610 | .omap2 = { | |
611 | /* | |
612 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
613 | * I2CHS IP's do not follow the usual pattern. | |
614 | * prcm_reg_id alone cannot be used to program | |
615 | * the iclk and fclk. Needs to be handled using | |
616 | * additonal flags when clk handling is moved | |
617 | * to hwmod framework. | |
618 | */ | |
619 | .module_offs = CORE_MOD, | |
620 | .prcm_reg_id = 1, | |
621 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
622 | .idlest_reg_id = 1, | |
623 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
624 | }, | |
625 | }, | |
626 | .slaves = omap2430_i2c1_slaves, | |
627 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
628 | .class = &i2c_class, | |
50ebb777 | 629 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
630 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
631 | }; | |
632 | ||
633 | /* I2C2 */ | |
634 | ||
2004290f PW |
635 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
636 | { .irq = INT_24XX_I2C2_IRQ, }, | |
637 | }; | |
638 | ||
639 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
640 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
641 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
642 | }; | |
643 | ||
644 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | |
645 | &omap2430_l4_core__i2c2, | |
646 | }; | |
647 | ||
648 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
649 | .name = "i2c2", | |
650 | .mpu_irqs = i2c2_mpu_irqs, | |
651 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
652 | .sdma_reqs = i2c2_sdma_reqs, | |
653 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
654 | .main_clk = "i2chs2_fck", | |
655 | .prcm = { | |
656 | .omap2 = { | |
657 | .module_offs = CORE_MOD, | |
658 | .prcm_reg_id = 1, | |
659 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
660 | .idlest_reg_id = 1, | |
661 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
662 | }, | |
663 | }, | |
664 | .slaves = omap2430_i2c2_slaves, | |
665 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
666 | .class = &i2c_class, | |
50ebb777 | 667 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
668 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
669 | }; | |
670 | ||
aeac0e44 VC |
671 | /* l4_wkup -> gpio1 */ |
672 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
673 | { | |
674 | .pa_start = 0x4900C000, | |
675 | .pa_end = 0x4900C1ff, | |
676 | .flags = ADDR_TYPE_RT | |
677 | }, | |
678 | }; | |
679 | ||
680 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
681 | .master = &omap2430_l4_wkup_hwmod, | |
682 | .slave = &omap2430_gpio1_hwmod, | |
683 | .clk = "gpios_ick", | |
684 | .addr = omap2430_gpio1_addr_space, | |
685 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | |
686 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
687 | }; | |
688 | ||
689 | /* l4_wkup -> gpio2 */ | |
690 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
691 | { | |
692 | .pa_start = 0x4900E000, | |
693 | .pa_end = 0x4900E1ff, | |
694 | .flags = ADDR_TYPE_RT | |
695 | }, | |
696 | }; | |
697 | ||
698 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
699 | .master = &omap2430_l4_wkup_hwmod, | |
700 | .slave = &omap2430_gpio2_hwmod, | |
701 | .clk = "gpios_ick", | |
702 | .addr = omap2430_gpio2_addr_space, | |
703 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | |
704 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
705 | }; | |
706 | ||
707 | /* l4_wkup -> gpio3 */ | |
708 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
709 | { | |
710 | .pa_start = 0x49010000, | |
711 | .pa_end = 0x490101ff, | |
712 | .flags = ADDR_TYPE_RT | |
713 | }, | |
714 | }; | |
715 | ||
716 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
717 | .master = &omap2430_l4_wkup_hwmod, | |
718 | .slave = &omap2430_gpio3_hwmod, | |
719 | .clk = "gpios_ick", | |
720 | .addr = omap2430_gpio3_addr_space, | |
721 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | |
722 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
723 | }; | |
724 | ||
725 | /* l4_wkup -> gpio4 */ | |
726 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
727 | { | |
728 | .pa_start = 0x49012000, | |
729 | .pa_end = 0x490121ff, | |
730 | .flags = ADDR_TYPE_RT | |
731 | }, | |
732 | }; | |
733 | ||
734 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
735 | .master = &omap2430_l4_wkup_hwmod, | |
736 | .slave = &omap2430_gpio4_hwmod, | |
737 | .clk = "gpios_ick", | |
738 | .addr = omap2430_gpio4_addr_space, | |
739 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | |
740 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
741 | }; | |
742 | ||
743 | /* l4_core -> gpio5 */ | |
744 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
745 | { | |
746 | .pa_start = 0x480B6000, | |
747 | .pa_end = 0x480B61ff, | |
748 | .flags = ADDR_TYPE_RT | |
749 | }, | |
750 | }; | |
751 | ||
752 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
753 | .master = &omap2430_l4_core_hwmod, | |
754 | .slave = &omap2430_gpio5_hwmod, | |
755 | .clk = "gpio5_ick", | |
756 | .addr = omap2430_gpio5_addr_space, | |
757 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | |
758 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
759 | }; | |
760 | ||
761 | /* gpio dev_attr */ | |
762 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
763 | .bank_width = 32, | |
764 | .dbck_flag = false, | |
765 | }; | |
766 | ||
767 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
768 | .rev_offs = 0x0000, | |
769 | .sysc_offs = 0x0010, | |
770 | .syss_offs = 0x0014, | |
771 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
772 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
773 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
774 | .sysc_fields = &omap_hwmod_sysc_type1, | |
775 | }; | |
776 | ||
777 | /* | |
778 | * 'gpio' class | |
779 | * general purpose io module | |
780 | */ | |
781 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
782 | .name = "gpio", | |
783 | .sysc = &omap243x_gpio_sysc, | |
784 | .rev = 0, | |
785 | }; | |
786 | ||
787 | /* gpio1 */ | |
788 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | |
789 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
790 | }; | |
791 | ||
792 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | |
793 | &omap2430_l4_wkup__gpio1, | |
794 | }; | |
795 | ||
796 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
797 | .name = "gpio1", | |
798 | .mpu_irqs = omap243x_gpio1_irqs, | |
799 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | |
800 | .main_clk = "gpios_fck", | |
801 | .prcm = { | |
802 | .omap2 = { | |
803 | .prcm_reg_id = 1, | |
804 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
805 | .module_offs = WKUP_MOD, | |
806 | .idlest_reg_id = 1, | |
807 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
808 | }, | |
809 | }, | |
810 | .slaves = omap2430_gpio1_slaves, | |
811 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
812 | .class = &omap243x_gpio_hwmod_class, | |
813 | .dev_attr = &gpio_dev_attr, | |
814 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
815 | }; | |
816 | ||
817 | /* gpio2 */ | |
818 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | |
819 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
820 | }; | |
821 | ||
822 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | |
823 | &omap2430_l4_wkup__gpio2, | |
824 | }; | |
825 | ||
826 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
827 | .name = "gpio2", | |
828 | .mpu_irqs = omap243x_gpio2_irqs, | |
829 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | |
830 | .main_clk = "gpios_fck", | |
831 | .prcm = { | |
832 | .omap2 = { | |
833 | .prcm_reg_id = 1, | |
834 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
835 | .module_offs = WKUP_MOD, | |
836 | .idlest_reg_id = 1, | |
837 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
838 | }, | |
839 | }, | |
840 | .slaves = omap2430_gpio2_slaves, | |
841 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
842 | .class = &omap243x_gpio_hwmod_class, | |
843 | .dev_attr = &gpio_dev_attr, | |
844 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
845 | }; | |
846 | ||
847 | /* gpio3 */ | |
848 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | |
849 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
850 | }; | |
851 | ||
852 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | |
853 | &omap2430_l4_wkup__gpio3, | |
854 | }; | |
855 | ||
856 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
857 | .name = "gpio3", | |
858 | .mpu_irqs = omap243x_gpio3_irqs, | |
859 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | |
860 | .main_clk = "gpios_fck", | |
861 | .prcm = { | |
862 | .omap2 = { | |
863 | .prcm_reg_id = 1, | |
864 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
865 | .module_offs = WKUP_MOD, | |
866 | .idlest_reg_id = 1, | |
867 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
868 | }, | |
869 | }, | |
870 | .slaves = omap2430_gpio3_slaves, | |
871 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
872 | .class = &omap243x_gpio_hwmod_class, | |
873 | .dev_attr = &gpio_dev_attr, | |
874 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
875 | }; | |
876 | ||
877 | /* gpio4 */ | |
878 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | |
879 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
880 | }; | |
881 | ||
882 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | |
883 | &omap2430_l4_wkup__gpio4, | |
884 | }; | |
885 | ||
886 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
887 | .name = "gpio4", | |
888 | .mpu_irqs = omap243x_gpio4_irqs, | |
889 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | |
890 | .main_clk = "gpios_fck", | |
891 | .prcm = { | |
892 | .omap2 = { | |
893 | .prcm_reg_id = 1, | |
894 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
895 | .module_offs = WKUP_MOD, | |
896 | .idlest_reg_id = 1, | |
897 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
898 | }, | |
899 | }, | |
900 | .slaves = omap2430_gpio4_slaves, | |
901 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
902 | .class = &omap243x_gpio_hwmod_class, | |
903 | .dev_attr = &gpio_dev_attr, | |
904 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
905 | }; | |
906 | ||
907 | /* gpio5 */ | |
908 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
909 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
910 | }; | |
911 | ||
912 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
913 | &omap2430_l4_core__gpio5, | |
914 | }; | |
915 | ||
916 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
917 | .name = "gpio5", | |
918 | .mpu_irqs = omap243x_gpio5_irqs, | |
919 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | |
920 | .main_clk = "gpio5_fck", | |
921 | .prcm = { | |
922 | .omap2 = { | |
923 | .prcm_reg_id = 2, | |
924 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
925 | .module_offs = CORE_MOD, | |
926 | .idlest_reg_id = 2, | |
927 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
928 | }, | |
929 | }, | |
930 | .slaves = omap2430_gpio5_slaves, | |
931 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
932 | .class = &omap243x_gpio_hwmod_class, | |
933 | .dev_attr = &gpio_dev_attr, | |
934 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
935 | }; | |
936 | ||
82cbd1ae MK |
937 | /* dma_system */ |
938 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
939 | .rev_offs = 0x0000, | |
940 | .sysc_offs = 0x002c, | |
941 | .syss_offs = 0x0028, | |
942 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
943 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
944 | SYSC_HAS_AUTOIDLE), | |
945 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
946 | .sysc_fields = &omap_hwmod_sysc_type1, | |
947 | }; | |
948 | ||
949 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
950 | .name = "dma", | |
951 | .sysc = &omap2430_dma_sysc, | |
952 | }; | |
953 | ||
954 | /* dma attributes */ | |
955 | static struct omap_dma_dev_attr dma_dev_attr = { | |
956 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
957 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
958 | .lch_count = 32, | |
959 | }; | |
960 | ||
961 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | |
962 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
963 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
964 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
965 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
966 | }; | |
967 | ||
968 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | |
969 | { | |
970 | .pa_start = 0x48056000, | |
971 | .pa_end = 0x4a0560ff, | |
972 | .flags = ADDR_TYPE_RT | |
973 | }, | |
974 | }; | |
975 | ||
976 | /* dma_system -> L3 */ | |
977 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
978 | .master = &omap2430_dma_system_hwmod, | |
979 | .slave = &omap2430_l3_main_hwmod, | |
980 | .clk = "core_l3_ck", | |
981 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
982 | }; | |
983 | ||
984 | /* dma_system master ports */ | |
985 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
986 | &omap2430_dma_system__l3, | |
987 | }; | |
988 | ||
989 | /* l4_core -> dma_system */ | |
990 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
991 | .master = &omap2430_l4_core_hwmod, | |
992 | .slave = &omap2430_dma_system_hwmod, | |
993 | .clk = "sdma_ick", | |
994 | .addr = omap2430_dma_system_addrs, | |
995 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | |
996 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
997 | }; | |
998 | ||
999 | /* dma_system slave ports */ | |
1000 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
1001 | &omap2430_l4_core__dma_system, | |
1002 | }; | |
1003 | ||
1004 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
1005 | .name = "dma", | |
1006 | .class = &omap2430_dma_hwmod_class, | |
1007 | .mpu_irqs = omap2430_dma_system_irqs, | |
1008 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | |
1009 | .main_clk = "core_l3_ck", | |
1010 | .slaves = omap2430_dma_system_slaves, | |
1011 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
1012 | .masters = omap2430_dma_system_masters, | |
1013 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
1014 | .dev_attr = &dma_dev_attr, | |
1015 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1016 | .flags = HWMOD_NO_IDLEST, | |
1017 | }; | |
1018 | ||
7f904c78 C |
1019 | /* |
1020 | * 'mcspi' class | |
1021 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1022 | * bus | |
1023 | */ | |
1024 | ||
1025 | static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { | |
1026 | .rev_offs = 0x0000, | |
1027 | .sysc_offs = 0x0010, | |
1028 | .syss_offs = 0x0014, | |
1029 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1030 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1031 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1032 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1033 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1034 | }; | |
1035 | ||
1036 | static struct omap_hwmod_class omap2430_mcspi_class = { | |
1037 | .name = "mcspi", | |
1038 | .sysc = &omap2430_mcspi_sysc, | |
1039 | .rev = OMAP2_MCSPI_REV, | |
1040 | }; | |
1041 | ||
1042 | /* mcspi1 */ | |
1043 | static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { | |
1044 | { .irq = 65 }, | |
1045 | }; | |
1046 | ||
1047 | static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { | |
1048 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ | |
1049 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ | |
1050 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ | |
1051 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ | |
1052 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ | |
1053 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ | |
1054 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ | |
1055 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ | |
1056 | }; | |
1057 | ||
1058 | static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { | |
1059 | &omap2430_l4_core__mcspi1, | |
1060 | }; | |
1061 | ||
1062 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1063 | .num_chipselect = 4, | |
1064 | }; | |
1065 | ||
1066 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
1067 | .name = "mcspi1_hwmod", | |
1068 | .mpu_irqs = omap2430_mcspi1_mpu_irqs, | |
1069 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), | |
1070 | .sdma_reqs = omap2430_mcspi1_sdma_reqs, | |
1071 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), | |
1072 | .main_clk = "mcspi1_fck", | |
1073 | .prcm = { | |
1074 | .omap2 = { | |
1075 | .module_offs = CORE_MOD, | |
1076 | .prcm_reg_id = 1, | |
1077 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1078 | .idlest_reg_id = 1, | |
1079 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1080 | }, | |
1081 | }, | |
1082 | .slaves = omap2430_mcspi1_slaves, | |
1083 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), | |
1084 | .class = &omap2430_mcspi_class, | |
1085 | .dev_attr = &omap_mcspi1_dev_attr, | |
1086 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1087 | }; | |
1088 | ||
1089 | /* mcspi2 */ | |
1090 | static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { | |
1091 | { .irq = 66 }, | |
1092 | }; | |
1093 | ||
1094 | static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { | |
1095 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ | |
1096 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ | |
1097 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ | |
1098 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ | |
1099 | }; | |
1100 | ||
1101 | static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { | |
1102 | &omap2430_l4_core__mcspi2, | |
1103 | }; | |
1104 | ||
1105 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1106 | .num_chipselect = 2, | |
1107 | }; | |
1108 | ||
1109 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
1110 | .name = "mcspi2_hwmod", | |
1111 | .mpu_irqs = omap2430_mcspi2_mpu_irqs, | |
1112 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), | |
1113 | .sdma_reqs = omap2430_mcspi2_sdma_reqs, | |
1114 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), | |
1115 | .main_clk = "mcspi2_fck", | |
1116 | .prcm = { | |
1117 | .omap2 = { | |
1118 | .module_offs = CORE_MOD, | |
1119 | .prcm_reg_id = 1, | |
1120 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1121 | .idlest_reg_id = 1, | |
1122 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1123 | }, | |
1124 | }, | |
1125 | .slaves = omap2430_mcspi2_slaves, | |
1126 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), | |
1127 | .class = &omap2430_mcspi_class, | |
1128 | .dev_attr = &omap_mcspi2_dev_attr, | |
1129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1130 | }; | |
1131 | ||
1132 | /* mcspi3 */ | |
1133 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
1134 | { .irq = 91 }, | |
1135 | }; | |
1136 | ||
1137 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
1138 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
1139 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
1140 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
1141 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
1142 | }; | |
1143 | ||
1144 | static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { | |
1145 | &omap2430_l4_core__mcspi3, | |
1146 | }; | |
1147 | ||
1148 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1149 | .num_chipselect = 2, | |
1150 | }; | |
1151 | ||
1152 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
1153 | .name = "mcspi3_hwmod", | |
1154 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, | |
1155 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), | |
1156 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, | |
1157 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), | |
1158 | .main_clk = "mcspi3_fck", | |
1159 | .prcm = { | |
1160 | .omap2 = { | |
1161 | .module_offs = CORE_MOD, | |
1162 | .prcm_reg_id = 2, | |
1163 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1164 | .idlest_reg_id = 2, | |
1165 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
1166 | }, | |
1167 | }, | |
1168 | .slaves = omap2430_mcspi3_slaves, | |
1169 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), | |
1170 | .class = &omap2430_mcspi_class, | |
1171 | .dev_attr = &omap_mcspi3_dev_attr, | |
1172 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1173 | }; | |
1174 | ||
44d02acf HH |
1175 | /* |
1176 | * usbhsotg | |
1177 | */ | |
1178 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { | |
1179 | .rev_offs = 0x0400, | |
1180 | .sysc_offs = 0x0404, | |
1181 | .syss_offs = 0x0408, | |
1182 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1183 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1184 | SYSC_HAS_AUTOIDLE), | |
1185 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1186 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1187 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1188 | }; | |
1189 | ||
1190 | static struct omap_hwmod_class usbotg_class = { | |
1191 | .name = "usbotg", | |
1192 | .sysc = &omap2430_usbhsotg_sysc, | |
1193 | }; | |
1194 | ||
1195 | /* usb_otg_hs */ | |
1196 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
1197 | ||
1198 | { .name = "mc", .irq = 92 }, | |
1199 | { .name = "dma", .irq = 93 }, | |
1200 | }; | |
1201 | ||
1202 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
1203 | .name = "usb_otg_hs", | |
1204 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
1205 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), | |
1206 | .main_clk = "usbhs_ick", | |
1207 | .prcm = { | |
1208 | .omap2 = { | |
1209 | .prcm_reg_id = 1, | |
1210 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
1211 | .module_offs = CORE_MOD, | |
1212 | .idlest_reg_id = 1, | |
1213 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
1214 | }, | |
1215 | }, | |
1216 | .masters = omap2430_usbhsotg_masters, | |
1217 | .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), | |
1218 | .slaves = omap2430_usbhsotg_slaves, | |
1219 | .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), | |
1220 | .class = &usbotg_class, | |
1221 | /* | |
1222 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1223 | * broken when autoidle is enabled | |
1224 | * workaround is to disable the autoidle bit at module level. | |
1225 | */ | |
1226 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1227 | | HWMOD_SWSUP_MSTANDBY, | |
1228 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
1229 | }; | |
1230 | ||
04aa67de TL |
1231 | |
1232 | ||
02bfc030 | 1233 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 1234 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
1235 | &omap2430_l4_core_hwmod, |
1236 | &omap2430_l4_wkup_hwmod, | |
1237 | &omap2430_mpu_hwmod, | |
08072acf | 1238 | &omap2430_iva_hwmod, |
165e2161 | 1239 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
1240 | &omap2430_uart1_hwmod, |
1241 | &omap2430_uart2_hwmod, | |
1242 | &omap2430_uart3_hwmod, | |
2004290f PW |
1243 | &omap2430_i2c1_hwmod, |
1244 | &omap2430_i2c2_hwmod, | |
aeac0e44 VC |
1245 | |
1246 | /* gpio class */ | |
1247 | &omap2430_gpio1_hwmod, | |
1248 | &omap2430_gpio2_hwmod, | |
1249 | &omap2430_gpio3_hwmod, | |
1250 | &omap2430_gpio4_hwmod, | |
1251 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
1252 | |
1253 | /* dma_system class*/ | |
1254 | &omap2430_dma_system_hwmod, | |
7f904c78 C |
1255 | |
1256 | /* mcspi class */ | |
1257 | &omap2430_mcspi1_hwmod, | |
1258 | &omap2430_mcspi2_hwmod, | |
1259 | &omap2430_mcspi3_hwmod, | |
04aa67de | 1260 | |
44d02acf HH |
1261 | /* usbotg class*/ |
1262 | &omap2430_usbhsotg_hwmod, | |
04aa67de | 1263 | |
02bfc030 PW |
1264 | NULL, |
1265 | }; | |
1266 | ||
7359154e PW |
1267 | int __init omap2430_hwmod_init(void) |
1268 | { | |
1269 | return omap_hwmod_init(omap2430_hwmods); | |
1270 | } |