Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
ce491cf8 | 15 | #include <plat/omap_hwmod.h> |
02bfc030 | 16 | #include <mach/irqs.h> |
ce491cf8 TL |
17 | #include <plat/cpu.h> |
18 | #include <plat/dma.h> | |
046465b7 | 19 | #include <plat/serial.h> |
2004290f | 20 | #include <plat/i2c.h> |
59c348c3 | 21 | #include <plat/gpio.h> |
617871de | 22 | #include <plat/mcspi.h> |
eddb1262 | 23 | #include <plat/dmtimer.h> |
996746ca SG |
24 | #include <plat/l3_2xxx.h> |
25 | #include <plat/l4_2xxx.h> | |
02bfc030 | 26 | |
43b40992 PW |
27 | #include "omap_hwmod_common_data.h" |
28 | ||
a714b9cf | 29 | #include "cm-regbits-24xx.h" |
2004290f | 30 | #include "prm-regbits-24xx.h" |
ff2516fb | 31 | #include "wd_timer.h" |
02bfc030 | 32 | |
7359154e PW |
33 | /* |
34 | * OMAP2420 hardware module integration data | |
35 | * | |
36 | * ALl of the data in this section should be autogeneratable from the | |
37 | * TI hardware database or other technical documentation. Data that | |
38 | * is driver-specific or driver-kernel integration-specific belongs | |
39 | * elsewhere. | |
40 | */ | |
41 | ||
02bfc030 | 42 | static struct omap_hwmod omap2420_mpu_hwmod; |
08072acf | 43 | static struct omap_hwmod omap2420_iva_hwmod; |
4a7cf90a | 44 | static struct omap_hwmod omap2420_l3_main_hwmod; |
02bfc030 | 45 | static struct omap_hwmod omap2420_l4_core_hwmod; |
996746ca SG |
46 | static struct omap_hwmod omap2420_dss_core_hwmod; |
47 | static struct omap_hwmod omap2420_dss_dispc_hwmod; | |
48 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; | |
49 | static struct omap_hwmod omap2420_dss_venc_hwmod; | |
a714b9cf | 50 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
59c348c3 VC |
51 | static struct omap_hwmod omap2420_gpio1_hwmod; |
52 | static struct omap_hwmod omap2420_gpio2_hwmod; | |
53 | static struct omap_hwmod omap2420_gpio3_hwmod; | |
54 | static struct omap_hwmod omap2420_gpio4_hwmod; | |
745685df | 55 | static struct omap_hwmod omap2420_dma_system_hwmod; |
617871de C |
56 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
57 | static struct omap_hwmod omap2420_mcspi2_hwmod; | |
02bfc030 PW |
58 | |
59 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
60 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
61 | .master = &omap2420_l3_main_hwmod, | |
02bfc030 PW |
62 | .slave = &omap2420_l4_core_hwmod, |
63 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
64 | }; | |
65 | ||
66 | /* MPU -> L3 interface */ | |
4a7cf90a | 67 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
02bfc030 | 68 | .master = &omap2420_mpu_hwmod, |
4a7cf90a | 69 | .slave = &omap2420_l3_main_hwmod, |
02bfc030 PW |
70 | .user = OCP_USER_MPU, |
71 | }; | |
72 | ||
996746ca SG |
73 | /* DSS -> l3 */ |
74 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { | |
75 | .master = &omap2420_dss_core_hwmod, | |
76 | .slave = &omap2420_l3_main_hwmod, | |
77 | .fw = { | |
78 | .omap2 = { | |
79 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
80 | .flags = OMAP_FIREWALL_L3, | |
81 | } | |
82 | }, | |
83 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
84 | }; | |
85 | ||
02bfc030 | 86 | /* L3 */ |
4a7cf90a | 87 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
fa98347e | 88 | .name = "l3_main", |
43b40992 | 89 | .class = &l3_hwmod_class, |
2eb1875d | 90 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
91 | }; |
92 | ||
93 | static struct omap_hwmod omap2420_l4_wkup_hwmod; | |
046465b7 KH |
94 | static struct omap_hwmod omap2420_uart1_hwmod; |
95 | static struct omap_hwmod omap2420_uart2_hwmod; | |
96 | static struct omap_hwmod omap2420_uart3_hwmod; | |
2004290f PW |
97 | static struct omap_hwmod omap2420_i2c1_hwmod; |
98 | static struct omap_hwmod omap2420_i2c2_hwmod; | |
3cb72fa4 C |
99 | static struct omap_hwmod omap2420_mcbsp1_hwmod; |
100 | static struct omap_hwmod omap2420_mcbsp2_hwmod; | |
02bfc030 | 101 | |
617871de | 102 | /* l4 core -> mcspi1 interface */ |
617871de C |
103 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
104 | .master = &omap2420_l4_core_hwmod, | |
105 | .slave = &omap2420_mcspi1_hwmod, | |
106 | .clk = "mcspi1_ick", | |
ded11383 | 107 | .addr = omap2_mcspi1_addr_space, |
617871de C |
108 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
109 | }; | |
110 | ||
111 | /* l4 core -> mcspi2 interface */ | |
617871de C |
112 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
113 | .master = &omap2420_l4_core_hwmod, | |
114 | .slave = &omap2420_mcspi2_hwmod, | |
115 | .clk = "mcspi2_ick", | |
ded11383 | 116 | .addr = omap2_mcspi2_addr_space, |
617871de C |
117 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
118 | }; | |
119 | ||
02bfc030 PW |
120 | /* L4_CORE -> L4_WKUP interface */ |
121 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | |
122 | .master = &omap2420_l4_core_hwmod, | |
123 | .slave = &omap2420_l4_wkup_hwmod, | |
124 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
125 | }; | |
126 | ||
046465b7 | 127 | /* L4 CORE -> UART1 interface */ |
046465b7 KH |
128 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
129 | .master = &omap2420_l4_core_hwmod, | |
130 | .slave = &omap2420_uart1_hwmod, | |
131 | .clk = "uart1_ick", | |
ded11383 | 132 | .addr = omap2xxx_uart1_addr_space, |
046465b7 KH |
133 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
134 | }; | |
135 | ||
136 | /* L4 CORE -> UART2 interface */ | |
046465b7 KH |
137 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
138 | .master = &omap2420_l4_core_hwmod, | |
139 | .slave = &omap2420_uart2_hwmod, | |
140 | .clk = "uart2_ick", | |
ded11383 | 141 | .addr = omap2xxx_uart2_addr_space, |
046465b7 KH |
142 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
143 | }; | |
144 | ||
145 | /* L4 PER -> UART3 interface */ | |
046465b7 KH |
146 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
147 | .master = &omap2420_l4_core_hwmod, | |
148 | .slave = &omap2420_uart3_hwmod, | |
149 | .clk = "uart3_ick", | |
ded11383 | 150 | .addr = omap2xxx_uart3_addr_space, |
046465b7 KH |
151 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
152 | }; | |
153 | ||
2004290f | 154 | /* L4 CORE -> I2C1 interface */ |
2004290f PW |
155 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
156 | .master = &omap2420_l4_core_hwmod, | |
157 | .slave = &omap2420_i2c1_hwmod, | |
158 | .clk = "i2c1_ick", | |
ded11383 | 159 | .addr = omap2_i2c1_addr_space, |
2004290f PW |
160 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
161 | }; | |
162 | ||
163 | /* L4 CORE -> I2C2 interface */ | |
2004290f PW |
164 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
165 | .master = &omap2420_l4_core_hwmod, | |
166 | .slave = &omap2420_i2c2_hwmod, | |
167 | .clk = "i2c2_ick", | |
ded11383 | 168 | .addr = omap2_i2c2_addr_space, |
2004290f PW |
169 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
170 | }; | |
171 | ||
02bfc030 PW |
172 | /* L4 CORE */ |
173 | static struct omap_hwmod omap2420_l4_core_hwmod = { | |
fa98347e | 174 | .name = "l4_core", |
43b40992 | 175 | .class = &l4_hwmod_class, |
2eb1875d | 176 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
177 | }; |
178 | ||
02bfc030 PW |
179 | /* L4 WKUP */ |
180 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | |
fa98347e | 181 | .name = "l4_wkup", |
43b40992 | 182 | .class = &l4_hwmod_class, |
2eb1875d | 183 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
184 | }; |
185 | ||
02bfc030 PW |
186 | /* MPU */ |
187 | static struct omap_hwmod omap2420_mpu_hwmod = { | |
5c2c0296 | 188 | .name = "mpu", |
43b40992 | 189 | .class = &mpu_hwmod_class, |
50ebdac2 | 190 | .main_clk = "mpu_ck", |
02bfc030 PW |
191 | }; |
192 | ||
08072acf PW |
193 | /* |
194 | * IVA1 interface data | |
195 | */ | |
196 | ||
197 | /* IVA <- L3 interface */ | |
198 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | |
199 | .master = &omap2420_l3_main_hwmod, | |
200 | .slave = &omap2420_iva_hwmod, | |
201 | .clk = "iva1_ifck", | |
202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
203 | }; | |
204 | ||
08072acf PW |
205 | /* |
206 | * IVA2 (IVA2) | |
207 | */ | |
208 | ||
209 | static struct omap_hwmod omap2420_iva_hwmod = { | |
210 | .name = "iva", | |
211 | .class = &iva_hwmod_class, | |
08072acf PW |
212 | }; |
213 | ||
c345c8b0 TKD |
214 | /* always-on timers dev attribute */ |
215 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
216 | .timer_capability = OMAP_TIMER_ALWON, | |
217 | }; | |
218 | ||
219 | /* pwm timers dev attribute */ | |
220 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
221 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
222 | }; | |
223 | ||
eddb1262 TG |
224 | /* timer1 */ |
225 | static struct omap_hwmod omap2420_timer1_hwmod; | |
eddb1262 TG |
226 | |
227 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | |
228 | { | |
229 | .pa_start = 0x48028000, | |
230 | .pa_end = 0x48028000 + SZ_1K - 1, | |
231 | .flags = ADDR_TYPE_RT | |
232 | }, | |
78183f3f | 233 | { } |
eddb1262 TG |
234 | }; |
235 | ||
236 | /* l4_wkup -> timer1 */ | |
237 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | |
238 | .master = &omap2420_l4_wkup_hwmod, | |
239 | .slave = &omap2420_timer1_hwmod, | |
240 | .clk = "gpt1_ick", | |
241 | .addr = omap2420_timer1_addrs, | |
eddb1262 TG |
242 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
243 | }; | |
244 | ||
eddb1262 TG |
245 | /* timer1 hwmod */ |
246 | static struct omap_hwmod omap2420_timer1_hwmod = { | |
247 | .name = "timer1", | |
0d619a89 | 248 | .mpu_irqs = omap2_timer1_mpu_irqs, |
eddb1262 TG |
249 | .main_clk = "gpt1_fck", |
250 | .prcm = { | |
251 | .omap2 = { | |
252 | .prcm_reg_id = 1, | |
253 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
254 | .module_offs = WKUP_MOD, | |
255 | .idlest_reg_id = 1, | |
256 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
257 | }, | |
258 | }, | |
c345c8b0 | 259 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 260 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
261 | }; |
262 | ||
263 | /* timer2 */ | |
264 | static struct omap_hwmod omap2420_timer2_hwmod; | |
eddb1262 TG |
265 | |
266 | /* l4_core -> timer2 */ | |
267 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { | |
268 | .master = &omap2420_l4_core_hwmod, | |
269 | .slave = &omap2420_timer2_hwmod, | |
270 | .clk = "gpt2_ick", | |
ded11383 | 271 | .addr = omap2xxx_timer2_addrs, |
eddb1262 TG |
272 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
273 | }; | |
274 | ||
eddb1262 TG |
275 | /* timer2 hwmod */ |
276 | static struct omap_hwmod omap2420_timer2_hwmod = { | |
277 | .name = "timer2", | |
0d619a89 | 278 | .mpu_irqs = omap2_timer2_mpu_irqs, |
eddb1262 TG |
279 | .main_clk = "gpt2_fck", |
280 | .prcm = { | |
281 | .omap2 = { | |
282 | .prcm_reg_id = 1, | |
283 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
284 | .module_offs = CORE_MOD, | |
285 | .idlest_reg_id = 1, | |
286 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
287 | }, | |
288 | }, | |
c345c8b0 | 289 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 290 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
291 | }; |
292 | ||
293 | /* timer3 */ | |
294 | static struct omap_hwmod omap2420_timer3_hwmod; | |
eddb1262 | 295 | |
eddb1262 TG |
296 | /* l4_core -> timer3 */ |
297 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { | |
298 | .master = &omap2420_l4_core_hwmod, | |
299 | .slave = &omap2420_timer3_hwmod, | |
300 | .clk = "gpt3_ick", | |
ded11383 | 301 | .addr = omap2xxx_timer3_addrs, |
eddb1262 TG |
302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
303 | }; | |
304 | ||
eddb1262 TG |
305 | /* timer3 hwmod */ |
306 | static struct omap_hwmod omap2420_timer3_hwmod = { | |
307 | .name = "timer3", | |
0d619a89 | 308 | .mpu_irqs = omap2_timer3_mpu_irqs, |
eddb1262 TG |
309 | .main_clk = "gpt3_fck", |
310 | .prcm = { | |
311 | .omap2 = { | |
312 | .prcm_reg_id = 1, | |
313 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
314 | .module_offs = CORE_MOD, | |
315 | .idlest_reg_id = 1, | |
316 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
317 | }, | |
318 | }, | |
c345c8b0 | 319 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 320 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
321 | }; |
322 | ||
323 | /* timer4 */ | |
324 | static struct omap_hwmod omap2420_timer4_hwmod; | |
eddb1262 | 325 | |
eddb1262 TG |
326 | /* l4_core -> timer4 */ |
327 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { | |
328 | .master = &omap2420_l4_core_hwmod, | |
329 | .slave = &omap2420_timer4_hwmod, | |
330 | .clk = "gpt4_ick", | |
ded11383 | 331 | .addr = omap2xxx_timer4_addrs, |
eddb1262 TG |
332 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
333 | }; | |
334 | ||
eddb1262 TG |
335 | /* timer4 hwmod */ |
336 | static struct omap_hwmod omap2420_timer4_hwmod = { | |
337 | .name = "timer4", | |
0d619a89 | 338 | .mpu_irqs = omap2_timer4_mpu_irqs, |
eddb1262 TG |
339 | .main_clk = "gpt4_fck", |
340 | .prcm = { | |
341 | .omap2 = { | |
342 | .prcm_reg_id = 1, | |
343 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
344 | .module_offs = CORE_MOD, | |
345 | .idlest_reg_id = 1, | |
346 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
347 | }, | |
348 | }, | |
c345c8b0 | 349 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 350 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
351 | }; |
352 | ||
353 | /* timer5 */ | |
354 | static struct omap_hwmod omap2420_timer5_hwmod; | |
eddb1262 | 355 | |
eddb1262 TG |
356 | /* l4_core -> timer5 */ |
357 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { | |
358 | .master = &omap2420_l4_core_hwmod, | |
359 | .slave = &omap2420_timer5_hwmod, | |
360 | .clk = "gpt5_ick", | |
ded11383 | 361 | .addr = omap2xxx_timer5_addrs, |
eddb1262 TG |
362 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
363 | }; | |
364 | ||
eddb1262 TG |
365 | /* timer5 hwmod */ |
366 | static struct omap_hwmod omap2420_timer5_hwmod = { | |
367 | .name = "timer5", | |
0d619a89 | 368 | .mpu_irqs = omap2_timer5_mpu_irqs, |
eddb1262 TG |
369 | .main_clk = "gpt5_fck", |
370 | .prcm = { | |
371 | .omap2 = { | |
372 | .prcm_reg_id = 1, | |
373 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
374 | .module_offs = CORE_MOD, | |
375 | .idlest_reg_id = 1, | |
376 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
377 | }, | |
378 | }, | |
c345c8b0 | 379 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 380 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
381 | }; |
382 | ||
383 | ||
384 | /* timer6 */ | |
385 | static struct omap_hwmod omap2420_timer6_hwmod; | |
eddb1262 | 386 | |
eddb1262 TG |
387 | /* l4_core -> timer6 */ |
388 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { | |
389 | .master = &omap2420_l4_core_hwmod, | |
390 | .slave = &omap2420_timer6_hwmod, | |
391 | .clk = "gpt6_ick", | |
ded11383 | 392 | .addr = omap2xxx_timer6_addrs, |
eddb1262 TG |
393 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
394 | }; | |
395 | ||
eddb1262 TG |
396 | /* timer6 hwmod */ |
397 | static struct omap_hwmod omap2420_timer6_hwmod = { | |
398 | .name = "timer6", | |
0d619a89 | 399 | .mpu_irqs = omap2_timer6_mpu_irqs, |
eddb1262 TG |
400 | .main_clk = "gpt6_fck", |
401 | .prcm = { | |
402 | .omap2 = { | |
403 | .prcm_reg_id = 1, | |
404 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
405 | .module_offs = CORE_MOD, | |
406 | .idlest_reg_id = 1, | |
407 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
408 | }, | |
409 | }, | |
c345c8b0 | 410 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 411 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
412 | }; |
413 | ||
414 | /* timer7 */ | |
415 | static struct omap_hwmod omap2420_timer7_hwmod; | |
eddb1262 | 416 | |
eddb1262 TG |
417 | /* l4_core -> timer7 */ |
418 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { | |
419 | .master = &omap2420_l4_core_hwmod, | |
420 | .slave = &omap2420_timer7_hwmod, | |
421 | .clk = "gpt7_ick", | |
ded11383 | 422 | .addr = omap2xxx_timer7_addrs, |
eddb1262 TG |
423 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
424 | }; | |
425 | ||
eddb1262 TG |
426 | /* timer7 hwmod */ |
427 | static struct omap_hwmod omap2420_timer7_hwmod = { | |
428 | .name = "timer7", | |
0d619a89 | 429 | .mpu_irqs = omap2_timer7_mpu_irqs, |
eddb1262 TG |
430 | .main_clk = "gpt7_fck", |
431 | .prcm = { | |
432 | .omap2 = { | |
433 | .prcm_reg_id = 1, | |
434 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
435 | .module_offs = CORE_MOD, | |
436 | .idlest_reg_id = 1, | |
437 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
438 | }, | |
439 | }, | |
c345c8b0 | 440 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 441 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
442 | }; |
443 | ||
444 | /* timer8 */ | |
445 | static struct omap_hwmod omap2420_timer8_hwmod; | |
eddb1262 | 446 | |
eddb1262 TG |
447 | /* l4_core -> timer8 */ |
448 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { | |
449 | .master = &omap2420_l4_core_hwmod, | |
450 | .slave = &omap2420_timer8_hwmod, | |
451 | .clk = "gpt8_ick", | |
ded11383 | 452 | .addr = omap2xxx_timer8_addrs, |
eddb1262 TG |
453 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
454 | }; | |
455 | ||
eddb1262 TG |
456 | /* timer8 hwmod */ |
457 | static struct omap_hwmod omap2420_timer8_hwmod = { | |
458 | .name = "timer8", | |
0d619a89 | 459 | .mpu_irqs = omap2_timer8_mpu_irqs, |
eddb1262 TG |
460 | .main_clk = "gpt8_fck", |
461 | .prcm = { | |
462 | .omap2 = { | |
463 | .prcm_reg_id = 1, | |
464 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
465 | .module_offs = CORE_MOD, | |
466 | .idlest_reg_id = 1, | |
467 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
468 | }, | |
469 | }, | |
c345c8b0 | 470 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 471 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
472 | }; |
473 | ||
474 | /* timer9 */ | |
475 | static struct omap_hwmod omap2420_timer9_hwmod; | |
eddb1262 | 476 | |
eddb1262 TG |
477 | /* l4_core -> timer9 */ |
478 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { | |
479 | .master = &omap2420_l4_core_hwmod, | |
480 | .slave = &omap2420_timer9_hwmod, | |
481 | .clk = "gpt9_ick", | |
ded11383 | 482 | .addr = omap2xxx_timer9_addrs, |
eddb1262 TG |
483 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
484 | }; | |
485 | ||
eddb1262 TG |
486 | /* timer9 hwmod */ |
487 | static struct omap_hwmod omap2420_timer9_hwmod = { | |
488 | .name = "timer9", | |
0d619a89 | 489 | .mpu_irqs = omap2_timer9_mpu_irqs, |
eddb1262 TG |
490 | .main_clk = "gpt9_fck", |
491 | .prcm = { | |
492 | .omap2 = { | |
493 | .prcm_reg_id = 1, | |
494 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
495 | .module_offs = CORE_MOD, | |
496 | .idlest_reg_id = 1, | |
497 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
498 | }, | |
499 | }, | |
c345c8b0 | 500 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 501 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
502 | }; |
503 | ||
504 | /* timer10 */ | |
505 | static struct omap_hwmod omap2420_timer10_hwmod; | |
eddb1262 | 506 | |
eddb1262 TG |
507 | /* l4_core -> timer10 */ |
508 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { | |
509 | .master = &omap2420_l4_core_hwmod, | |
510 | .slave = &omap2420_timer10_hwmod, | |
511 | .clk = "gpt10_ick", | |
ded11383 | 512 | .addr = omap2_timer10_addrs, |
eddb1262 TG |
513 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
514 | }; | |
515 | ||
eddb1262 TG |
516 | /* timer10 hwmod */ |
517 | static struct omap_hwmod omap2420_timer10_hwmod = { | |
518 | .name = "timer10", | |
0d619a89 | 519 | .mpu_irqs = omap2_timer10_mpu_irqs, |
eddb1262 TG |
520 | .main_clk = "gpt10_fck", |
521 | .prcm = { | |
522 | .omap2 = { | |
523 | .prcm_reg_id = 1, | |
524 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
525 | .module_offs = CORE_MOD, | |
526 | .idlest_reg_id = 1, | |
527 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
528 | }, | |
529 | }, | |
c345c8b0 | 530 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 531 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
532 | }; |
533 | ||
534 | /* timer11 */ | |
535 | static struct omap_hwmod omap2420_timer11_hwmod; | |
eddb1262 | 536 | |
eddb1262 TG |
537 | /* l4_core -> timer11 */ |
538 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { | |
539 | .master = &omap2420_l4_core_hwmod, | |
540 | .slave = &omap2420_timer11_hwmod, | |
541 | .clk = "gpt11_ick", | |
ded11383 | 542 | .addr = omap2_timer11_addrs, |
eddb1262 TG |
543 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
544 | }; | |
545 | ||
eddb1262 TG |
546 | /* timer11 hwmod */ |
547 | static struct omap_hwmod omap2420_timer11_hwmod = { | |
548 | .name = "timer11", | |
0d619a89 | 549 | .mpu_irqs = omap2_timer11_mpu_irqs, |
eddb1262 TG |
550 | .main_clk = "gpt11_fck", |
551 | .prcm = { | |
552 | .omap2 = { | |
553 | .prcm_reg_id = 1, | |
554 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
555 | .module_offs = CORE_MOD, | |
556 | .idlest_reg_id = 1, | |
557 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
558 | }, | |
559 | }, | |
c345c8b0 | 560 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 561 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
562 | }; |
563 | ||
564 | /* timer12 */ | |
565 | static struct omap_hwmod omap2420_timer12_hwmod; | |
eddb1262 | 566 | |
eddb1262 TG |
567 | /* l4_core -> timer12 */ |
568 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { | |
569 | .master = &omap2420_l4_core_hwmod, | |
570 | .slave = &omap2420_timer12_hwmod, | |
571 | .clk = "gpt12_ick", | |
ded11383 | 572 | .addr = omap2xxx_timer12_addrs, |
eddb1262 TG |
573 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
574 | }; | |
575 | ||
eddb1262 TG |
576 | /* timer12 hwmod */ |
577 | static struct omap_hwmod omap2420_timer12_hwmod = { | |
578 | .name = "timer12", | |
0d619a89 | 579 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
eddb1262 TG |
580 | .main_clk = "gpt12_fck", |
581 | .prcm = { | |
582 | .omap2 = { | |
583 | .prcm_reg_id = 1, | |
584 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
585 | .module_offs = CORE_MOD, | |
586 | .idlest_reg_id = 1, | |
587 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
588 | }, | |
589 | }, | |
c345c8b0 | 590 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 591 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
592 | }; |
593 | ||
a714b9cf VC |
594 | /* l4_wkup -> wd_timer2 */ |
595 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | |
596 | { | |
597 | .pa_start = 0x48022000, | |
598 | .pa_end = 0x4802207f, | |
599 | .flags = ADDR_TYPE_RT | |
600 | }, | |
78183f3f | 601 | { } |
a714b9cf VC |
602 | }; |
603 | ||
604 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { | |
605 | .master = &omap2420_l4_wkup_hwmod, | |
606 | .slave = &omap2420_wd_timer2_hwmod, | |
607 | .clk = "mpu_wdt_ick", | |
608 | .addr = omap2420_wd_timer2_addrs, | |
a714b9cf VC |
609 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
610 | }; | |
611 | ||
a714b9cf VC |
612 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
613 | .name = "wd_timer2", | |
273b9465 | 614 | .class = &omap2xxx_wd_timer_hwmod_class, |
a714b9cf VC |
615 | .main_clk = "mpu_wdt_fck", |
616 | .prcm = { | |
617 | .omap2 = { | |
618 | .prcm_reg_id = 1, | |
619 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
620 | .module_offs = WKUP_MOD, | |
621 | .idlest_reg_id = 1, | |
622 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
623 | }, | |
624 | }, | |
a714b9cf VC |
625 | }; |
626 | ||
046465b7 KH |
627 | /* UART1 */ |
628 | ||
046465b7 KH |
629 | static struct omap_hwmod omap2420_uart1_hwmod = { |
630 | .name = "uart1", | |
0d619a89 | 631 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 632 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 KH |
633 | .main_clk = "uart1_fck", |
634 | .prcm = { | |
635 | .omap2 = { | |
636 | .module_offs = CORE_MOD, | |
637 | .prcm_reg_id = 1, | |
638 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
639 | .idlest_reg_id = 1, | |
640 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
641 | }, | |
642 | }, | |
273b9465 | 643 | .class = &omap2_uart_class, |
046465b7 KH |
644 | }; |
645 | ||
646 | /* UART2 */ | |
647 | ||
046465b7 KH |
648 | static struct omap_hwmod omap2420_uart2_hwmod = { |
649 | .name = "uart2", | |
0d619a89 | 650 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 651 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 KH |
652 | .main_clk = "uart2_fck", |
653 | .prcm = { | |
654 | .omap2 = { | |
655 | .module_offs = CORE_MOD, | |
656 | .prcm_reg_id = 1, | |
657 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
658 | .idlest_reg_id = 1, | |
659 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
660 | }, | |
661 | }, | |
273b9465 | 662 | .class = &omap2_uart_class, |
046465b7 KH |
663 | }; |
664 | ||
665 | /* UART3 */ | |
666 | ||
046465b7 KH |
667 | static struct omap_hwmod omap2420_uart3_hwmod = { |
668 | .name = "uart3", | |
0d619a89 | 669 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 670 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
671 | .main_clk = "uart3_fck", |
672 | .prcm = { | |
673 | .omap2 = { | |
674 | .module_offs = CORE_MOD, | |
675 | .prcm_reg_id = 2, | |
676 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
677 | .idlest_reg_id = 2, | |
678 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
679 | }, | |
680 | }, | |
273b9465 | 681 | .class = &omap2_uart_class, |
046465b7 KH |
682 | }; |
683 | ||
996746ca | 684 | /* dss */ |
996746ca | 685 | |
996746ca SG |
686 | /* l4_core -> dss */ |
687 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { | |
688 | .master = &omap2420_l4_core_hwmod, | |
689 | .slave = &omap2420_dss_core_hwmod, | |
690 | .clk = "dss_ick", | |
ded11383 | 691 | .addr = omap2_dss_addrs, |
996746ca SG |
692 | .fw = { |
693 | .omap2 = { | |
694 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
695 | .flags = OMAP_FIREWALL_L4, | |
696 | } | |
697 | }, | |
698 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
699 | }; | |
700 | ||
996746ca | 701 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
1258ea59 TV |
702 | /* |
703 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
704 | * driver does not use these clocks. | |
705 | */ | |
996746ca SG |
706 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
707 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
708 | }; | |
709 | ||
710 | static struct omap_hwmod omap2420_dss_core_hwmod = { | |
711 | .name = "dss_core", | |
273b9465 | 712 | .class = &omap2_dss_hwmod_class, |
996746ca | 713 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
d826ebfa | 714 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
996746ca SG |
715 | .prcm = { |
716 | .omap2 = { | |
717 | .prcm_reg_id = 1, | |
718 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
719 | .module_offs = CORE_MOD, | |
720 | .idlest_reg_id = 1, | |
721 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
722 | }, | |
723 | }, | |
724 | .opt_clks = dss_opt_clks, | |
725 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1258ea59 | 726 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
996746ca SG |
727 | }; |
728 | ||
996746ca SG |
729 | /* l4_core -> dss_dispc */ |
730 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { | |
731 | .master = &omap2420_l4_core_hwmod, | |
732 | .slave = &omap2420_dss_dispc_hwmod, | |
733 | .clk = "dss_ick", | |
ded11383 | 734 | .addr = omap2_dss_dispc_addrs, |
996746ca SG |
735 | .fw = { |
736 | .omap2 = { | |
737 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, | |
738 | .flags = OMAP_FIREWALL_L4, | |
739 | } | |
740 | }, | |
741 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
742 | }; | |
743 | ||
996746ca SG |
744 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { |
745 | .name = "dss_dispc", | |
273b9465 | 746 | .class = &omap2_dispc_hwmod_class, |
0d619a89 | 747 | .mpu_irqs = omap2_dispc_irqs, |
996746ca SG |
748 | .main_clk = "dss1_fck", |
749 | .prcm = { | |
750 | .omap2 = { | |
751 | .prcm_reg_id = 1, | |
752 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
753 | .module_offs = CORE_MOD, | |
754 | .idlest_reg_id = 1, | |
755 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
756 | }, | |
757 | }, | |
996746ca | 758 | .flags = HWMOD_NO_IDLEST, |
b923d40d | 759 | .dev_attr = &omap2_3_dss_dispc_dev_attr |
996746ca SG |
760 | }; |
761 | ||
996746ca SG |
762 | /* l4_core -> dss_rfbi */ |
763 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { | |
764 | .master = &omap2420_l4_core_hwmod, | |
765 | .slave = &omap2420_dss_rfbi_hwmod, | |
766 | .clk = "dss_ick", | |
ded11383 | 767 | .addr = omap2_dss_rfbi_addrs, |
996746ca SG |
768 | .fw = { |
769 | .omap2 = { | |
770 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
771 | .flags = OMAP_FIREWALL_L4, | |
772 | } | |
773 | }, | |
774 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
775 | }; | |
776 | ||
b8ac10d8 TV |
777 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
778 | { .role = "ick", .clk = "dss_ick" }, | |
779 | }; | |
780 | ||
996746ca SG |
781 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { |
782 | .name = "dss_rfbi", | |
273b9465 | 783 | .class = &omap2_rfbi_hwmod_class, |
996746ca SG |
784 | .main_clk = "dss1_fck", |
785 | .prcm = { | |
786 | .omap2 = { | |
787 | .prcm_reg_id = 1, | |
788 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
789 | .module_offs = CORE_MOD, | |
790 | }, | |
791 | }, | |
b8ac10d8 TV |
792 | .opt_clks = dss_rfbi_opt_clks, |
793 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
996746ca SG |
794 | .flags = HWMOD_NO_IDLEST, |
795 | }; | |
796 | ||
996746ca SG |
797 | /* l4_core -> dss_venc */ |
798 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { | |
799 | .master = &omap2420_l4_core_hwmod, | |
800 | .slave = &omap2420_dss_venc_hwmod, | |
b8ac10d8 | 801 | .clk = "dss_ick", |
ded11383 | 802 | .addr = omap2_dss_venc_addrs, |
996746ca SG |
803 | .fw = { |
804 | .omap2 = { | |
805 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, | |
806 | .flags = OMAP_FIREWALL_L4, | |
807 | } | |
808 | }, | |
809 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
810 | }; | |
811 | ||
996746ca SG |
812 | static struct omap_hwmod omap2420_dss_venc_hwmod = { |
813 | .name = "dss_venc", | |
273b9465 | 814 | .class = &omap2_venc_hwmod_class, |
b8ac10d8 | 815 | .main_clk = "dss_54m_fck", |
996746ca SG |
816 | .prcm = { |
817 | .omap2 = { | |
818 | .prcm_reg_id = 1, | |
819 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
820 | .module_offs = CORE_MOD, | |
821 | }, | |
822 | }, | |
996746ca SG |
823 | .flags = HWMOD_NO_IDLEST, |
824 | }; | |
825 | ||
2004290f PW |
826 | /* I2C common */ |
827 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
828 | .rev_offs = 0x00, | |
829 | .sysc_offs = 0x20, | |
830 | .syss_offs = 0x10, | |
d73d65fa | 831 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
2004290f PW |
832 | .sysc_fields = &omap_hwmod_sysc_type1, |
833 | }; | |
834 | ||
835 | static struct omap_hwmod_class i2c_class = { | |
836 | .name = "i2c", | |
837 | .sysc = &i2c_sysc, | |
db791a75 | 838 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 839 | .reset = &omap_i2c_reset, |
2004290f PW |
840 | }; |
841 | ||
4d4441a6 AG |
842 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
843 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
844 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
845 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
846 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
847 | }; | |
2004290f PW |
848 | |
849 | /* I2C1 */ | |
850 | ||
2004290f PW |
851 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
852 | .name = "i2c1", | |
0d619a89 | 853 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 854 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
855 | .main_clk = "i2c1_fck", |
856 | .prcm = { | |
857 | .omap2 = { | |
858 | .module_offs = CORE_MOD, | |
859 | .prcm_reg_id = 1, | |
860 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | |
861 | .idlest_reg_id = 1, | |
862 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | |
863 | }, | |
864 | }, | |
2004290f PW |
865 | .class = &i2c_class, |
866 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
867 | .flags = HWMOD_16BIT_REG, |
868 | }; | |
869 | ||
870 | /* I2C2 */ | |
871 | ||
2004290f PW |
872 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
873 | .name = "i2c2", | |
0d619a89 | 874 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 875 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
876 | .main_clk = "i2c2_fck", |
877 | .prcm = { | |
878 | .omap2 = { | |
879 | .module_offs = CORE_MOD, | |
880 | .prcm_reg_id = 1, | |
881 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | |
882 | .idlest_reg_id = 1, | |
883 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | |
884 | }, | |
885 | }, | |
2004290f PW |
886 | .class = &i2c_class, |
887 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
888 | .flags = HWMOD_16BIT_REG, |
889 | }; | |
890 | ||
59c348c3 VC |
891 | /* l4_wkup -> gpio1 */ |
892 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | |
893 | { | |
894 | .pa_start = 0x48018000, | |
895 | .pa_end = 0x480181ff, | |
896 | .flags = ADDR_TYPE_RT | |
897 | }, | |
78183f3f | 898 | { } |
59c348c3 VC |
899 | }; |
900 | ||
901 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | |
902 | .master = &omap2420_l4_wkup_hwmod, | |
903 | .slave = &omap2420_gpio1_hwmod, | |
904 | .clk = "gpios_ick", | |
905 | .addr = omap2420_gpio1_addr_space, | |
59c348c3 VC |
906 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
907 | }; | |
908 | ||
909 | /* l4_wkup -> gpio2 */ | |
910 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | |
911 | { | |
912 | .pa_start = 0x4801a000, | |
913 | .pa_end = 0x4801a1ff, | |
914 | .flags = ADDR_TYPE_RT | |
915 | }, | |
78183f3f | 916 | { } |
59c348c3 VC |
917 | }; |
918 | ||
919 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | |
920 | .master = &omap2420_l4_wkup_hwmod, | |
921 | .slave = &omap2420_gpio2_hwmod, | |
922 | .clk = "gpios_ick", | |
923 | .addr = omap2420_gpio2_addr_space, | |
59c348c3 VC |
924 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
925 | }; | |
926 | ||
927 | /* l4_wkup -> gpio3 */ | |
928 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | |
929 | { | |
930 | .pa_start = 0x4801c000, | |
931 | .pa_end = 0x4801c1ff, | |
932 | .flags = ADDR_TYPE_RT | |
933 | }, | |
78183f3f | 934 | { } |
59c348c3 VC |
935 | }; |
936 | ||
937 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | |
938 | .master = &omap2420_l4_wkup_hwmod, | |
939 | .slave = &omap2420_gpio3_hwmod, | |
940 | .clk = "gpios_ick", | |
941 | .addr = omap2420_gpio3_addr_space, | |
59c348c3 VC |
942 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
943 | }; | |
944 | ||
945 | /* l4_wkup -> gpio4 */ | |
946 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | |
947 | { | |
948 | .pa_start = 0x4801e000, | |
949 | .pa_end = 0x4801e1ff, | |
950 | .flags = ADDR_TYPE_RT | |
951 | }, | |
78183f3f | 952 | { } |
59c348c3 VC |
953 | }; |
954 | ||
955 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | |
956 | .master = &omap2420_l4_wkup_hwmod, | |
957 | .slave = &omap2420_gpio4_hwmod, | |
958 | .clk = "gpios_ick", | |
959 | .addr = omap2420_gpio4_addr_space, | |
59c348c3 VC |
960 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
961 | }; | |
962 | ||
963 | /* gpio dev_attr */ | |
964 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
965 | .bank_width = 32, | |
966 | .dbck_flag = false, | |
967 | }; | |
968 | ||
59c348c3 | 969 | /* gpio1 */ |
59c348c3 VC |
970 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
971 | .name = "gpio1", | |
f95440ca | 972 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 973 | .mpu_irqs = omap2_gpio1_irqs, |
59c348c3 VC |
974 | .main_clk = "gpios_fck", |
975 | .prcm = { | |
976 | .omap2 = { | |
977 | .prcm_reg_id = 1, | |
978 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
979 | .module_offs = WKUP_MOD, | |
980 | .idlest_reg_id = 1, | |
981 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
982 | }, | |
983 | }, | |
273b9465 | 984 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 | 985 | .dev_attr = &gpio_dev_attr, |
59c348c3 VC |
986 | }; |
987 | ||
988 | /* gpio2 */ | |
59c348c3 VC |
989 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
990 | .name = "gpio2", | |
f95440ca | 991 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 992 | .mpu_irqs = omap2_gpio2_irqs, |
59c348c3 VC |
993 | .main_clk = "gpios_fck", |
994 | .prcm = { | |
995 | .omap2 = { | |
996 | .prcm_reg_id = 1, | |
997 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
998 | .module_offs = WKUP_MOD, | |
999 | .idlest_reg_id = 1, | |
1000 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1001 | }, | |
1002 | }, | |
273b9465 | 1003 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 | 1004 | .dev_attr = &gpio_dev_attr, |
59c348c3 VC |
1005 | }; |
1006 | ||
1007 | /* gpio3 */ | |
59c348c3 VC |
1008 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
1009 | .name = "gpio3", | |
f95440ca | 1010 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1011 | .mpu_irqs = omap2_gpio3_irqs, |
59c348c3 VC |
1012 | .main_clk = "gpios_fck", |
1013 | .prcm = { | |
1014 | .omap2 = { | |
1015 | .prcm_reg_id = 1, | |
1016 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1017 | .module_offs = WKUP_MOD, | |
1018 | .idlest_reg_id = 1, | |
1019 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1020 | }, | |
1021 | }, | |
273b9465 | 1022 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 | 1023 | .dev_attr = &gpio_dev_attr, |
59c348c3 VC |
1024 | }; |
1025 | ||
1026 | /* gpio4 */ | |
59c348c3 VC |
1027 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
1028 | .name = "gpio4", | |
f95440ca | 1029 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1030 | .mpu_irqs = omap2_gpio4_irqs, |
59c348c3 VC |
1031 | .main_clk = "gpios_fck", |
1032 | .prcm = { | |
1033 | .omap2 = { | |
1034 | .prcm_reg_id = 1, | |
1035 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1036 | .module_offs = WKUP_MOD, | |
1037 | .idlest_reg_id = 1, | |
1038 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1039 | }, | |
1040 | }, | |
273b9465 | 1041 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 | 1042 | .dev_attr = &gpio_dev_attr, |
59c348c3 VC |
1043 | }; |
1044 | ||
745685df MK |
1045 | /* dma attributes */ |
1046 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1047 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1048 | IS_CSSA_32 | IS_CDSA_32, | |
1049 | .lch_count = 32, | |
1050 | }; | |
1051 | ||
745685df MK |
1052 | /* dma_system -> L3 */ |
1053 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | |
1054 | .master = &omap2420_dma_system_hwmod, | |
1055 | .slave = &omap2420_l3_main_hwmod, | |
1056 | .clk = "core_l3_ck", | |
1057 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1058 | }; | |
1059 | ||
745685df MK |
1060 | /* l4_core -> dma_system */ |
1061 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | |
1062 | .master = &omap2420_l4_core_hwmod, | |
1063 | .slave = &omap2420_dma_system_hwmod, | |
1064 | .clk = "sdma_ick", | |
ded11383 | 1065 | .addr = omap2_dma_system_addrs, |
745685df MK |
1066 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1067 | }; | |
1068 | ||
745685df MK |
1069 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
1070 | .name = "dma", | |
273b9465 | 1071 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 1072 | .mpu_irqs = omap2_dma_system_irqs, |
745685df | 1073 | .main_clk = "core_l3_ck", |
745685df | 1074 | .dev_attr = &dma_dev_attr, |
745685df MK |
1075 | .flags = HWMOD_NO_IDLEST, |
1076 | }; | |
1077 | ||
fca1ab55 ORL |
1078 | /* mailbox */ |
1079 | static struct omap_hwmod omap2420_mailbox_hwmod; | |
1080 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { | |
1081 | { .name = "dsp", .irq = 26 }, | |
1082 | { .name = "iva", .irq = 34 }, | |
212738a4 | 1083 | { .irq = -1 } |
fca1ab55 ORL |
1084 | }; |
1085 | ||
fca1ab55 ORL |
1086 | /* l4_core -> mailbox */ |
1087 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | |
1088 | .master = &omap2420_l4_core_hwmod, | |
1089 | .slave = &omap2420_mailbox_hwmod, | |
ded11383 | 1090 | .addr = omap2_mailbox_addrs, |
fca1ab55 ORL |
1091 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1092 | }; | |
1093 | ||
fca1ab55 ORL |
1094 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
1095 | .name = "mailbox", | |
273b9465 | 1096 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 1097 | .mpu_irqs = omap2420_mailbox_irqs, |
fca1ab55 ORL |
1098 | .main_clk = "mailboxes_ick", |
1099 | .prcm = { | |
1100 | .omap2 = { | |
1101 | .prcm_reg_id = 1, | |
1102 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1103 | .module_offs = CORE_MOD, | |
1104 | .idlest_reg_id = 1, | |
1105 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
1106 | }, | |
1107 | }, | |
fca1ab55 ORL |
1108 | }; |
1109 | ||
617871de | 1110 | /* mcspi1 */ |
617871de C |
1111 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
1112 | .num_chipselect = 4, | |
1113 | }; | |
1114 | ||
1115 | static struct omap_hwmod omap2420_mcspi1_hwmod = { | |
bec93811 | 1116 | .name = "mcspi1", |
0d619a89 | 1117 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 1118 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
617871de C |
1119 | .main_clk = "mcspi1_fck", |
1120 | .prcm = { | |
1121 | .omap2 = { | |
1122 | .module_offs = CORE_MOD, | |
1123 | .prcm_reg_id = 1, | |
1124 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1125 | .idlest_reg_id = 1, | |
1126 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1127 | }, | |
1128 | }, | |
273b9465 PW |
1129 | .class = &omap2xxx_mcspi_class, |
1130 | .dev_attr = &omap_mcspi1_dev_attr, | |
617871de C |
1131 | }; |
1132 | ||
1133 | /* mcspi2 */ | |
617871de C |
1134 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
1135 | .num_chipselect = 2, | |
1136 | }; | |
1137 | ||
1138 | static struct omap_hwmod omap2420_mcspi2_hwmod = { | |
bec93811 | 1139 | .name = "mcspi2", |
0d619a89 | 1140 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 1141 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
617871de C |
1142 | .main_clk = "mcspi2_fck", |
1143 | .prcm = { | |
1144 | .omap2 = { | |
1145 | .module_offs = CORE_MOD, | |
1146 | .prcm_reg_id = 1, | |
1147 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1148 | .idlest_reg_id = 1, | |
1149 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1150 | }, | |
1151 | }, | |
273b9465 PW |
1152 | .class = &omap2xxx_mcspi_class, |
1153 | .dev_attr = &omap_mcspi2_dev_attr, | |
617871de C |
1154 | }; |
1155 | ||
3cb72fa4 C |
1156 | /* |
1157 | * 'mcbsp' class | |
1158 | * multi channel buffered serial port controller | |
1159 | */ | |
1160 | ||
1161 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |
1162 | .name = "mcbsp", | |
1163 | }; | |
1164 | ||
1165 | /* mcbsp1 */ | |
1166 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | |
1167 | { .name = "tx", .irq = 59 }, | |
1168 | { .name = "rx", .irq = 60 }, | |
212738a4 | 1169 | { .irq = -1 } |
3cb72fa4 C |
1170 | }; |
1171 | ||
3cb72fa4 C |
1172 | /* l4_core -> mcbsp1 */ |
1173 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | |
1174 | .master = &omap2420_l4_core_hwmod, | |
1175 | .slave = &omap2420_mcbsp1_hwmod, | |
1176 | .clk = "mcbsp1_ick", | |
ded11383 | 1177 | .addr = omap2_mcbsp1_addrs, |
3cb72fa4 C |
1178 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1179 | }; | |
1180 | ||
3cb72fa4 C |
1181 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
1182 | .name = "mcbsp1", | |
1183 | .class = &omap2420_mcbsp_hwmod_class, | |
1184 | .mpu_irqs = omap2420_mcbsp1_irqs, | |
d826ebfa | 1185 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
3cb72fa4 C |
1186 | .main_clk = "mcbsp1_fck", |
1187 | .prcm = { | |
1188 | .omap2 = { | |
1189 | .prcm_reg_id = 1, | |
1190 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1191 | .module_offs = CORE_MOD, | |
1192 | .idlest_reg_id = 1, | |
1193 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
1194 | }, | |
1195 | }, | |
3cb72fa4 C |
1196 | }; |
1197 | ||
1198 | /* mcbsp2 */ | |
1199 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | |
1200 | { .name = "tx", .irq = 62 }, | |
1201 | { .name = "rx", .irq = 63 }, | |
212738a4 | 1202 | { .irq = -1 } |
3cb72fa4 C |
1203 | }; |
1204 | ||
3cb72fa4 C |
1205 | /* l4_core -> mcbsp2 */ |
1206 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | |
1207 | .master = &omap2420_l4_core_hwmod, | |
1208 | .slave = &omap2420_mcbsp2_hwmod, | |
1209 | .clk = "mcbsp2_ick", | |
ded11383 | 1210 | .addr = omap2xxx_mcbsp2_addrs, |
3cb72fa4 C |
1211 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1212 | }; | |
1213 | ||
3cb72fa4 C |
1214 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
1215 | .name = "mcbsp2", | |
1216 | .class = &omap2420_mcbsp_hwmod_class, | |
1217 | .mpu_irqs = omap2420_mcbsp2_irqs, | |
d826ebfa | 1218 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
3cb72fa4 C |
1219 | .main_clk = "mcbsp2_fck", |
1220 | .prcm = { | |
1221 | .omap2 = { | |
1222 | .prcm_reg_id = 1, | |
1223 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1224 | .module_offs = CORE_MOD, | |
1225 | .idlest_reg_id = 1, | |
1226 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
1227 | }, | |
1228 | }, | |
0a78c5c5 PW |
1229 | }; |
1230 | ||
1231 | static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { | |
1232 | &omap2420_l3_main__l4_core, | |
1233 | &omap2420_mpu__l3_main, | |
1234 | &omap2420_dss__l3, | |
1235 | &omap2420_l4_core__mcspi1, | |
1236 | &omap2420_l4_core__mcspi2, | |
1237 | &omap2420_l4_core__l4_wkup, | |
1238 | &omap2_l4_core__uart1, | |
1239 | &omap2_l4_core__uart2, | |
1240 | &omap2_l4_core__uart3, | |
1241 | &omap2420_l4_core__i2c1, | |
1242 | &omap2420_l4_core__i2c2, | |
1243 | &omap2420_l3__iva, | |
1244 | &omap2420_l4_wkup__timer1, | |
1245 | &omap2420_l4_core__timer2, | |
1246 | &omap2420_l4_core__timer3, | |
1247 | &omap2420_l4_core__timer4, | |
1248 | &omap2420_l4_core__timer5, | |
1249 | &omap2420_l4_core__timer6, | |
1250 | &omap2420_l4_core__timer7, | |
1251 | &omap2420_l4_core__timer8, | |
1252 | &omap2420_l4_core__timer9, | |
1253 | &omap2420_l4_core__timer10, | |
1254 | &omap2420_l4_core__timer11, | |
1255 | &omap2420_l4_core__timer12, | |
1256 | &omap2420_l4_wkup__wd_timer2, | |
1257 | &omap2420_l4_core__dss, | |
1258 | &omap2420_l4_core__dss_dispc, | |
1259 | &omap2420_l4_core__dss_rfbi, | |
1260 | &omap2420_l4_core__dss_venc, | |
1261 | &omap2420_l4_wkup__gpio1, | |
1262 | &omap2420_l4_wkup__gpio2, | |
1263 | &omap2420_l4_wkup__gpio3, | |
1264 | &omap2420_l4_wkup__gpio4, | |
1265 | &omap2420_dma_system__l3, | |
1266 | &omap2420_l4_core__dma_system, | |
1267 | &omap2420_l4_core__mailbox, | |
1268 | &omap2420_l4_core__mcbsp1, | |
1269 | &omap2420_l4_core__mcbsp2, | |
02bfc030 PW |
1270 | NULL, |
1271 | }; | |
1272 | ||
7359154e PW |
1273 | int __init omap2420_hwmod_init(void) |
1274 | { | |
0a78c5c5 | 1275 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
7359154e | 1276 | } |