[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c

/*
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */

#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"

/*
 * OMAP2420 hardware module integration data
 *
 * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

/*
 * IP blocks
 */

/* IVA1 (IVA1) */
static struct omap_hwmod_class iva1_hwmod_class = {
	.name		= "iva1",
};

static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	{ .name = "iva", .rst_shift = 8 },
};

static struct omap_hwmod omap2420_iva_hwmod = {
	.name		= "iva",
	.class		= &iva1_hwmod_class,
	.clkdm_name	= "iva1_clkdm",
	.rst_lines	= omap2420_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
	.main_clk	= "iva1_ifck",
};

/* DSP */
static struct omap_hwmod_class dsp_hwmod_class = {
	.name		= "dsp",
};

static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	{ .name = "logic", .rst_shift = 0 },
	{ .name = "mmu", .rst_shift = 1 },
};

static struct omap_hwmod omap2420_dsp_hwmod = {
	.name		= "dsp",
	.class		= &dsp_hwmod_class,
	.clkdm_name	= "dsp_clkdm",
	.rst_lines	= omap2420_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
	.main_clk	= "dsp_fck",
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
	.rev		= OMAP_I2C_IP_VERSION_1,
	.reset		= &omap_i2c_reset,
};

static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags		= OMAP_I2C_FLAG_NO_FIFO |
			  OMAP_I2C_FLAG_SIMPLE_CLOCK |
			  OMAP_I2C_FLAG_16BIT_DATA_REG |
			  OMAP_I2C_FLAG_BUS_SHIFT_2,
};

/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
	.name		= "i2c1",
	.main_clk	= "i2c1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	/*
	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	 * while a transfer is active seems to cause the I2C block to
	 * timeout. Why? Good question."
	 */
	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
};

/* I2C2 */
static struct omap_hwmod omap2420_i2c2_hwmod = {
	.name		= "i2c2",
	.main_clk	= "i2c2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	.flags		= HWMOD_16BIT_REG,
};

/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
						IS_CSSA_32 | IS_CDSA_32,
	.lch_count = 32,
};

static struct omap_hwmod omap2420_dma_system_hwmod = {
	.name		= "dma",
	.class		= &omap2xxx_dma_hwmod_class,
	.mpu_irqs	= omap2_dma_system_irqs,
	.main_clk	= "core_l3_ck",
	.dev_attr	= &dma_dev_attr,
	.flags		= HWMOD_NO_IDLEST,
};

/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap2xxx_mailbox_hwmod_class,
	.main_clk	= "mailboxes_ick",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
		},
	},
};

/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	.name = "mcbsp",
};

static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	{ .role = "prcm_fck", .clk = "func_96m_ck" },
};

/* mcbsp1 */
static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

/* mcbsp2 */
static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	.rev_offs	= 0x3c,
	.sysc_offs	= 0x64,
	.syss_offs	= 0x68,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	.name	= "msdi",
	.sysc	= &omap2420_msdi_sysc,
	.reset	= &omap_msdi_reset,
};

/* msdi1 */
static struct omap_hwmod omap2420_msdi1_hwmod = {
	.name		= "msdi1",
	.class		= &omap2420_msdi_hwmod_class,
	.main_clk	= "mmc_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_MMC_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
		},
	},
	.flags		= HWMOD_16BIT_REG,
};

/* HDQ1W/1-wire */
static struct omap_hwmod omap2420_hdq1w_hwmod = {
	.name		= "hdq1w",
	.main_clk	= "hdq_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
		},
	},
	.class		= &omap2_hdq1w_class,
};

/*
 * interfaces
 */

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* IVA <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__iva = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_iva_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* DSP <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_dsp_hwmod,
	.clk		= "dsp_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_timer1_hwmod,
	.clk		= "gpt1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio1_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio2_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio3 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio3_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio4 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio4_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	.master		= &omap2420_dma_system_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_dma_system_hwmod,
	.clk		= "sdma_ick",
	.addr		= omap2_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mailbox_hwmod,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp1_hwmod,
	.clk		= "mcbsp1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp2_hwmod,
	.clk		= "mcbsp2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> msdi1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_msdi1_hwmod,
	.clk		= "mmc_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> hdq1w interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_hdq1w_hwmod,
	.clk		= "hdq_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};


/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_counter_32k_hwmod,
	.clk		= "sync_32k_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2xxx_gpmc_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
	&omap2xxx_l3_main__l4_core,
	&omap2xxx_mpu__l3_main,
	&omap2xxx_dss__l3,
	&omap2xxx_l4_core__mcspi1,
	&omap2xxx_l4_core__mcspi2,
	&omap2xxx_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
	&omap2420_l4_core__i2c1,
	&omap2420_l4_core__i2c2,
	&omap2420_l3__iva,
	&omap2420_l3__dsp,
	&omap2420_l4_wkup__timer1,
	&omap2xxx_l4_core__timer2,
	&omap2xxx_l4_core__timer3,
	&omap2xxx_l4_core__timer4,
	&omap2xxx_l4_core__timer5,
	&omap2xxx_l4_core__timer6,
	&omap2xxx_l4_core__timer7,
	&omap2xxx_l4_core__timer8,
	&omap2xxx_l4_core__timer9,
	&omap2xxx_l4_core__timer10,
	&omap2xxx_l4_core__timer11,
	&omap2xxx_l4_core__timer12,
	&omap2420_l4_wkup__wd_timer2,
	&omap2xxx_l4_core__dss,
	&omap2xxx_l4_core__dss_dispc,
	&omap2xxx_l4_core__dss_rfbi,
	&omap2xxx_l4_core__dss_venc,
	&omap2420_l4_wkup__gpio1,
	&omap2420_l4_wkup__gpio2,
	&omap2420_l4_wkup__gpio3,
	&omap2420_l4_wkup__gpio4,
	&omap2420_dma_system__l3,
	&omap2420_l4_core__dma_system,
	&omap2420_l4_core__mailbox,
	&omap2420_l4_core__mcbsp1,
	&omap2420_l4_core__mcbsp2,
	&omap2420_l4_core__msdi1,
	&omap2xxx_l4_core__rng,
	&omap2xxx_l4_core__sham,
	&omap2xxx_l4_core__aes,
	&omap2420_l4_core__hdq1w,
	&omap2420_l4_wkup__counter_32k,
	&omap2420_l3__gpmc,
	NULL,
};

int __init omap2420_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
Commit	Line	Data
02bfc030	1	/*
7359154e	2	* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
02bfc030	3	*
78183f3f	4	* Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5	5	* Copyright (C) 2012 Texas Instruments, Inc.
02bfc030 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* XXX handle crossbar/shared link difference for L3?
7359154e	13	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	14	*/
3a8761c0 TL	15
3a8761c0 TL	16	#include <linux/i2c-omap.h>
2203747c	17	#include <linux/platform_data/spi-omap2-mcspi.h>
45c3eb7d	18	#include <linux/omap-dma.h>
eddb1262	19	#include <plat/dmtimer.h>
2a296c8f TL	20
2a296c8f TL	21	#include "omap_hwmod.h"
1e0f51a9	22	#include "l3_2xxx.h"
70606b1c	23	#include "l4_2xxx.h"
02bfc030	24
43b40992 PW	25	#include "omap_hwmod_common_data.h"
43b40992 PW	26
a714b9cf	27	#include "cm-regbits-24xx.h"
2004290f	28	#include "prm-regbits-24xx.h"
3a8761c0	29	#include "i2c.h"
68f39e74	30	#include "mmc.h"
3d82cbbb	31	#include "serial.h"
ff2516fb	32	#include "wd_timer.h"
02bfc030	33
7359154e PW	34	/*
	35	* OMAP2420 hardware module integration data
	36	*
844a3b63	37	* All of the data in this section should be autogeneratable from the
7359154e PW	38	* TI hardware database or other technical documentation. Data that
	39	* is driver-specific or driver-kernel integration-specific belongs
	40	* elsewhere.
	41	*/
	42
844a3b63 PW	43	/*
	44	* IP blocks
	45	*/
996746ca	46
3af35fbc PW	47	/* IVA1 (IVA1) */
	48	static struct omap_hwmod_class iva1_hwmod_class = {
	49	.name = "iva1",
	50	};
	51
	52	static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	53	{ .name = "iva", .rst_shift = 8 },
	54	};
	55
08072acf PW	56	static struct omap_hwmod omap2420_iva_hwmod = {
08072acf PW	57	.name = "iva",
3af35fbc PW	58	.class = &iva1_hwmod_class,
	59	.clkdm_name = "iva1_clkdm",
	60	.rst_lines = omap2420_iva_resets,
	61	.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
	62	.main_clk = "iva1_ifck",
	63	};
	64
	65	/* DSP */
	66	static struct omap_hwmod_class dsp_hwmod_class = {
	67	.name = "dsp",
	68	};
	69
	70	static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	71	{ .name = "logic", .rst_shift = 0 },
	72	{ .name = "mmu", .rst_shift = 1 },
	73	};
	74
	75	static struct omap_hwmod omap2420_dsp_hwmod = {
	76	.name = "dsp",
	77	.class = &dsp_hwmod_class,
	78	.clkdm_name = "dsp_clkdm",
	79	.rst_lines = omap2420_dsp_resets,
	80	.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
	81	.main_clk = "dsp_fck",
08072acf PW	82	};
08072acf PW	83
2004290f PW	84	/* I2C common */
	85	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	86	.rev_offs = 0x00,
	87	.sysc_offs = 0x20,
	88	.syss_offs = 0x10,
d73d65fa	89	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
2004290f PW	90	.sysc_fields = &omap_hwmod_sysc_type1,
	91	};
	92
	93	static struct omap_hwmod_class i2c_class = {
	94	.name = "i2c",
	95	.sysc = &i2c_sysc,
db791a75	96	.rev = OMAP_I2C_IP_VERSION_1,
6d3c55fd	97	.reset = &omap_i2c_reset,
2004290f PW	98	};
2004290f PW	99
4d4441a6 AG	100	static struct omap_i2c_dev_attr i2c_dev_attr = {
	101	.flags = OMAP_I2C_FLAG_NO_FIFO \|
	102	OMAP_I2C_FLAG_SIMPLE_CLOCK \|
	103	OMAP_I2C_FLAG_16BIT_DATA_REG \|
	104	OMAP_I2C_FLAG_BUS_SHIFT_2,
	105	};
2004290f PW	106
2004290f PW	107	/* I2C1 */
2004290f PW	108	static struct omap_hwmod omap2420_i2c1_hwmod = {
2004290f PW	109	.name = "i2c1",
2004290f PW	110	.main_clk = "i2c1_fck",
	111	.prcm = {
	112	.omap2 = {
	113	.module_offs = CORE_MOD,
	114	.prcm_reg_id = 1,
	115	.module_bit = OMAP2420_EN_I2C1_SHIFT,
	116	.idlest_reg_id = 1,
	117	.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
	118	},
	119	},
2004290f PW	120	.class = &i2c_class,
2004290f PW	121	.dev_attr = &i2c_dev_attr,
aff2f7d9 PW	122	/*
	123	* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	124	* while a transfer is active seems to cause the I2C block to
	125	* timeout. Why? Good question."
	126	*/
	127	.flags = (HWMOD_16BIT_REG \| HWMOD_BLOCK_WFI),
2004290f PW	128	};
	129
	130	/* I2C2 */
2004290f PW	131	static struct omap_hwmod omap2420_i2c2_hwmod = {
2004290f PW	132	.name = "i2c2",
2004290f PW	133	.main_clk = "i2c2_fck",
	134	.prcm = {
	135	.omap2 = {
	136	.module_offs = CORE_MOD,
	137	.prcm_reg_id = 1,
	138	.module_bit = OMAP2420_EN_I2C2_SHIFT,
	139	.idlest_reg_id = 1,
	140	.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
	141	},
	142	},
2004290f PW	143	.class = &i2c_class,
2004290f PW	144	.dev_attr = &i2c_dev_attr,
2004290f PW	145	.flags = HWMOD_16BIT_REG,
	146	};
	147
745685df MK	148	/* dma attributes */
	149	static struct omap_dma_dev_attr dma_dev_attr = {
	150	.dev_caps = RESERVE_CHANNEL \| DMA_LINKED_LCH \| GLOBAL_PRIORITY \|
	151	IS_CSSA_32 \| IS_CDSA_32,
	152	.lch_count = 32,
	153	};
	154
745685df MK	155	static struct omap_hwmod omap2420_dma_system_hwmod = {
745685df MK	156	.name = "dma",
273b9465	157	.class = &omap2xxx_dma_hwmod_class,
0d619a89	158	.mpu_irqs = omap2_dma_system_irqs,
745685df	159	.main_clk = "core_l3_ck",
745685df	160	.dev_attr = &dma_dev_attr,
745685df MK	161	.flags = HWMOD_NO_IDLEST,
	162	};
	163
fca1ab55	164	/* mailbox */
fca1ab55 ORL	165	static struct omap_hwmod omap2420_mailbox_hwmod = {
fca1ab55 ORL	166	.name = "mailbox",
273b9465	167	.class = &omap2xxx_mailbox_hwmod_class,
fca1ab55 ORL	168	.main_clk = "mailboxes_ick",
	169	.prcm = {
	170	.omap2 = {
	171	.prcm_reg_id = 1,
	172	.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
	173	.module_offs = CORE_MOD,
	174	.idlest_reg_id = 1,
	175	.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
	176	},
	177	},
fca1ab55 ORL	178	};
fca1ab55 ORL	179
3cb72fa4 C	180	/*
	181	* 'mcbsp' class
	182	* multi channel buffered serial port controller
	183	*/
	184
	185	static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	186	.name = "mcbsp",
	187	};
	188
b3153100 PU	189	static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	190	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	191	{ .role = "prcm_fck", .clk = "func_96m_ck" },
	192	};
	193
3cb72fa4	194	/* mcbsp1 */
3cb72fa4 C	195	static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	196	.name = "mcbsp1",
	197	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	198	.main_clk = "mcbsp1_fck",
	199	.prcm = {
	200	.omap2 = {
	201	.prcm_reg_id = 1,
	202	.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
	203	.module_offs = CORE_MOD,
	204	.idlest_reg_id = 1,
	205	.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
	206	},
	207	},
b3153100 PU	208	.opt_clks = mcbsp_opt_clks,
b3153100 PU	209	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
3cb72fa4 C	210	};
	211
	212	/* mcbsp2 */
3cb72fa4 C	213	static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	214	.name = "mcbsp2",
	215	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	216	.main_clk = "mcbsp2_fck",
	217	.prcm = {
	218	.omap2 = {
	219	.prcm_reg_id = 1,
	220	.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
	221	.module_offs = CORE_MOD,
	222	.idlest_reg_id = 1,
	223	.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
	224	},
	225	},
b3153100 PU	226	.opt_clks = mcbsp_opt_clks,
b3153100 PU	227	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
0a78c5c5 PW	228	};
0a78c5c5 PW	229
ad1b6662 TL	230	static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	231	.rev_offs = 0x3c,
	232	.sysc_offs = 0x64,
	233	.syss_offs = 0x68,
	234	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
	235	.sysc_fields = &omap_hwmod_sysc_type1,
	236	};
	237
	238	static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	239	.name = "msdi",
	240	.sysc = &omap2420_msdi_sysc,
	241	.reset = &omap_msdi_reset,
	242	};
	243
	244	/* msdi1 */
ad1b6662 TL	245	static struct omap_hwmod omap2420_msdi1_hwmod = {
	246	.name = "msdi1",
	247	.class = &omap2420_msdi_hwmod_class,
ad1b6662 TL	248	.main_clk = "mmc_fck",
	249	.prcm = {
	250	.omap2 = {
	251	.prcm_reg_id = 1,
	252	.module_bit = OMAP2420_EN_MMC_SHIFT,
	253	.module_offs = CORE_MOD,
	254	.idlest_reg_id = 1,
	255	.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
	256	},
	257	},
	258	.flags = HWMOD_16BIT_REG,
	259	};
	260
f32bd778 PW	261	/* HDQ1W/1-wire */
	262	static struct omap_hwmod omap2420_hdq1w_hwmod = {
	263	.name = "hdq1w",
f32bd778 PW	264	.main_clk = "hdq_fck",
	265	.prcm = {
	266	.omap2 = {
	267	.module_offs = CORE_MOD,
	268	.prcm_reg_id = 1,
	269	.module_bit = OMAP24XX_EN_HDQ_SHIFT,
	270	.idlest_reg_id = 1,
	271	.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
	272	},
	273	},
	274	.class = &omap2_hdq1w_class,
	275	};
	276
844a3b63 PW	277	/*
	278	* interfaces
	279	*/
	280
844a3b63 PW	281	/* L4 CORE -> I2C1 interface */
844a3b63 PW	282	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
cb48427e	283	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	284	.slave = &omap2420_i2c1_hwmod,
844a3b63 PW	285	.clk = "i2c1_ick",
844a3b63 PW	286	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	287	};
	288
	289	/* L4 CORE -> I2C2 interface */
	290	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
cb48427e	291	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	292	.slave = &omap2420_i2c2_hwmod,
844a3b63 PW	293	.clk = "i2c2_ick",
844a3b63 PW	294	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	295	};
	296
	297	/* IVA <- L3 interface */
	298	static struct omap_hwmod_ocp_if omap2420_l3__iva = {
cb48427e	299	.master = &omap2xxx_l3_main_hwmod,
844a3b63	300	.slave = &omap2420_iva_hwmod,
3af35fbc PW	301	.clk = "core_l3_ck",
	302	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	303	};
	304
	305	/* DSP <- L3 interface */
	306	static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	307	.master = &omap2xxx_l3_main_hwmod,
	308	.slave = &omap2420_dsp_hwmod,
	309	.clk = "dsp_ick",
844a3b63 PW	310	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	311	};
	312
844a3b63 PW	313	/* l4_wkup -> timer1 */
844a3b63 PW	314	static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
cb48427e PW	315	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	316	.slave = &omap2xxx_timer1_hwmod,
844a3b63	317	.clk = "gpt1_ick",
844a3b63 PW	318	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	319	};
	320
844a3b63	321	/* l4_wkup -> wd_timer2 */
844a3b63	322	static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
cb48427e PW	323	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	324	.slave = &omap2xxx_wd_timer2_hwmod,
844a3b63	325	.clk = "mpu_wdt_ick",
844a3b63 PW	326	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	327	};
	328
844a3b63	329	/* l4_wkup -> gpio1 */
844a3b63	330	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
cb48427e PW	331	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	332	.slave = &omap2xxx_gpio1_hwmod,
844a3b63	333	.clk = "gpios_ick",
844a3b63 PW	334	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	335	};
	336
	337	/* l4_wkup -> gpio2 */
844a3b63	338	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
cb48427e PW	339	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	340	.slave = &omap2xxx_gpio2_hwmod,
844a3b63	341	.clk = "gpios_ick",
844a3b63 PW	342	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	343	};
	344
	345	/* l4_wkup -> gpio3 */
844a3b63	346	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
cb48427e PW	347	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	348	.slave = &omap2xxx_gpio3_hwmod,
844a3b63	349	.clk = "gpios_ick",
844a3b63 PW	350	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	351	};
	352
	353	/* l4_wkup -> gpio4 */
844a3b63	354	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
cb48427e PW	355	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	356	.slave = &omap2xxx_gpio4_hwmod,
844a3b63	357	.clk = "gpios_ick",
844a3b63 PW	358	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	359	};
	360
	361	/* dma_system -> L3 */
	362	static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	363	.master = &omap2420_dma_system_hwmod,
cb48427e	364	.slave = &omap2xxx_l3_main_hwmod,
844a3b63 PW	365	.clk = "core_l3_ck",
	366	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	367	};
	368
	369	/* l4_core -> dma_system */
	370	static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
cb48427e	371	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	372	.slave = &omap2420_dma_system_hwmod,
	373	.clk = "sdma_ick",
	374	.addr = omap2_dma_system_addrs,
	375	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	376	};
	377
	378	/* l4_core -> mailbox */
	379	static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
cb48427e	380	.master = &omap2xxx_l4_core_hwmod,
844a3b63	381	.slave = &omap2420_mailbox_hwmod,
844a3b63 PW	382	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	383	};
	384
	385	/* l4_core -> mcbsp1 */
	386	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
cb48427e	387	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	388	.slave = &omap2420_mcbsp1_hwmod,
844a3b63 PW	389	.clk = "mcbsp1_ick",
844a3b63 PW	390	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	391	};
	392
	393	/* l4_core -> mcbsp2 */
	394	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
cb48427e	395	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	396	.slave = &omap2420_mcbsp2_hwmod,
844a3b63 PW	397	.clk = "mcbsp2_ick",
844a3b63 PW	398	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	399	};
	400
ad1b6662 TL	401	/* l4_core -> msdi1 */
	402	static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	403	.master = &omap2xxx_l4_core_hwmod,
	404	.slave = &omap2420_msdi1_hwmod,
	405	.clk = "mmc_ick",
ad1b6662 TL	406	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	407	};
	408
f32bd778 PW	409	/* l4_core -> hdq1w interface */
	410	static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	411	.master = &omap2xxx_l4_core_hwmod,
	412	.slave = &omap2420_hdq1w_hwmod,
	413	.clk = "hdq_ick",
f32bd778 PW	414	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	415	.flags = OMAP_FIREWALL_L4 \| OCPIF_SWSUP_IDLE,
	416	};
	417
	418
c8d82ff6	419	/* l4_wkup -> 32ksync_counter */
c8d82ff6 VH	420	static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	421	.master = &omap2xxx_l4_wkup_hwmod,
	422	.slave = &omap2xxx_counter_32k_hwmod,
	423	.clk = "sync_32k_ick",
c8d82ff6 VH	424	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	425	};
	426
49484a60 AM	427	static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	428	.master = &omap2xxx_l3_main_hwmod,
	429	.slave = &omap2xxx_gpmc_hwmod,
	430	.clk = "core_l3_ck",
49484a60 AM	431	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	432	};
	433
0a78c5c5	434	static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
6a29755f PW	435	&omap2xxx_l3_main__l4_core,
	436	&omap2xxx_mpu__l3_main,
	437	&omap2xxx_dss__l3,
	438	&omap2xxx_l4_core__mcspi1,
	439	&omap2xxx_l4_core__mcspi2,
	440	&omap2xxx_l4_core__l4_wkup,
0a78c5c5 PW	441	&omap2_l4_core__uart1,
	442	&omap2_l4_core__uart2,
	443	&omap2_l4_core__uart3,
	444	&omap2420_l4_core__i2c1,
	445	&omap2420_l4_core__i2c2,
	446	&omap2420_l3__iva,
3af35fbc	447	&omap2420_l3__dsp,
0a78c5c5	448	&omap2420_l4_wkup__timer1,
6a29755f PW	449	&omap2xxx_l4_core__timer2,
	450	&omap2xxx_l4_core__timer3,
	451	&omap2xxx_l4_core__timer4,
	452	&omap2xxx_l4_core__timer5,
	453	&omap2xxx_l4_core__timer6,
	454	&omap2xxx_l4_core__timer7,
	455	&omap2xxx_l4_core__timer8,
	456	&omap2xxx_l4_core__timer9,
	457	&omap2xxx_l4_core__timer10,
	458	&omap2xxx_l4_core__timer11,
	459	&omap2xxx_l4_core__timer12,
0a78c5c5	460	&omap2420_l4_wkup__wd_timer2,
6a29755f PW	461	&omap2xxx_l4_core__dss,
	462	&omap2xxx_l4_core__dss_dispc,
	463	&omap2xxx_l4_core__dss_rfbi,
	464	&omap2xxx_l4_core__dss_venc,
0a78c5c5 PW	465	&omap2420_l4_wkup__gpio1,
	466	&omap2420_l4_wkup__gpio2,
	467	&omap2420_l4_wkup__gpio3,
	468	&omap2420_l4_wkup__gpio4,
	469	&omap2420_dma_system__l3,
	470	&omap2420_l4_core__dma_system,
	471	&omap2420_l4_core__mailbox,
	472	&omap2420_l4_core__mcbsp1,
	473	&omap2420_l4_core__mcbsp2,
ad1b6662	474	&omap2420_l4_core__msdi1,
e9b0a2fb	475	&omap2xxx_l4_core__rng,
e569e994	476	&omap2xxx_l4_core__sham,
660ffd6b	477	&omap2xxx_l4_core__aes,
f32bd778	478	&omap2420_l4_core__hdq1w,
c8d82ff6	479	&omap2420_l4_wkup__counter_32k,
49484a60	480	&omap2420_l3__gpmc,
02bfc030 PW	481	NULL,
	482	};
	483
7359154e PW	484	int __init omap2420_hwmod_init(void)
7359154e PW	485	{
9ebfd285	486	omap_hwmod_init();
0a78c5c5	487	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
7359154e	488	}