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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
44595982 | 2 | /* |
44595982 PW |
3 | * This file contains the processor specific definitions |
4 | * of the TI OMAP24XX. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * Copyright (C) 2007 Nokia Corporation. | |
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8 | */ |
9 | ||
088ef950 TL |
10 | #ifndef __ASM_ARCH_OMAP2_H |
11 | #define __ASM_ARCH_OMAP2_H | |
9839c6b8 | 12 | |
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13 | /* |
14 | * Please place only base defines here and put the rest in device | |
15 | * specific headers. Note also that some of these defines are needed | |
16 | * for omap1 to compile without adding ifdefs. | |
17 | */ | |
18 | ||
19 | #define L4_24XX_BASE 0x48000000 | |
72d0f1c3 | 20 | #define L4_WK_243X_BASE 0x49000000 |
9ad5897c | 21 | #define L3_24XX_BASE 0x68000000 |
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22 | |
23 | /* interrupt controller */ | |
9ad5897c | 24 | #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) |
9839c6b8 | 25 | #define OMAP24XX_IVA_INTC_BASE 0x40000000 |
9839c6b8 | 26 | |
54164bb2 | 27 | #define OMAP242X_CTRL_BASE L4_24XX_BASE |
44595982 PW |
28 | #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) |
29 | #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) | |
30 | #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) | |
31 | #define OMAP2420_PRM_BASE OMAP2420_CM_BASE | |
32 | #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) | |
33 | #define OMAP2420_SMS_BASE 0x68008000 | |
fd1dc87d | 34 | #define OMAP2420_GPMC_BASE 0x6800a000 |
72d0f1c3 | 35 | |
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36 | #define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) |
37 | #define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) | |
38 | #define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) | |
39 | #define OMAP2430_PRM_BASE OMAP2430_CM_BASE | |
40 | ||
41 | #define OMAP243X_SMS_BASE 0x6C000000 | |
42 | #define OMAP243X_SDRC_BASE 0x6D000000 | |
72d0f1c3 | 43 | #define OMAP243X_GPMC_BASE 0x6E000000 |
44595982 PW |
44 | #define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) |
45 | #define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE | |
46 | #define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) | |
9ad5897c | 47 | |
f4e4c324 | 48 | /* DSP SS */ |
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49 | #define OMAP2420_DSP_BASE 0x58000000 |
50 | #define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) | |
51 | #define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) | |
52 | #define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) | |
53 | ||
54 | #define OMAP243X_DSP_BASE 0x5C000000 | |
55 | #define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) | |
56 | #define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) | |
f4e4c324 TL |
57 | |
58 | /* Mailbox */ | |
59 | #define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) | |
60 | ||
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61 | /* Camera */ |
62 | #define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) | |
63 | ||
64 | /* Security */ | |
65 | #define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) | |
66 | #define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) | |
67 | #define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) | |
68 | #define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) | |
69 | #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) | |
70 | #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) | |
71 | ||
088ef950 | 72 | #endif /* __ASM_ARCH_OMAP2_H */ |
9839c6b8 | 73 |