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367cd31e SS |
1 | /* |
2 | * OMAP4 SMP source file. It contains platform specific fucntions | |
3 | * needed for the linux smp kernel. | |
4 | * | |
5 | * Copyright (C) 2009 Texas Instruments, Inc. | |
6 | * | |
7 | * Author: | |
8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
10 | * Platform file needed for the OMAP4 SMP. This file is based on arm | |
11 | * realview smp platform. | |
12 | * * Copyright (c) 2002 ARM Limited. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
367cd31e SS |
20 | #include <linux/smp.h> |
21 | #include <linux/io.h> | |
22 | ||
942e2c9e | 23 | #include <asm/cacheflush.h> |
0f7b332f | 24 | #include <asm/hardware/gic.h> |
367cd31e SS |
25 | #include <asm/smp_scu.h> |
26 | #include <mach/hardware.h> | |
b2b9762f | 27 | #include <mach/omap-secure.h> |
4e65331c TL |
28 | |
29 | #include "common.h" | |
367cd31e | 30 | |
367cd31e | 31 | /* SCU base address */ |
e4e7a13a | 32 | static void __iomem *scu_base; |
367cd31e | 33 | |
367cd31e SS |
34 | static DEFINE_SPINLOCK(boot_lock); |
35 | ||
02afe8a7 SS |
36 | void __iomem *omap4_get_scu_base(void) |
37 | { | |
38 | return scu_base; | |
39 | } | |
40 | ||
367cd31e SS |
41 | void __cpuinit platform_secondary_init(unsigned int cpu) |
42 | { | |
b2b9762f SS |
43 | /* |
44 | * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. | |
45 | * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA | |
46 | * init and for CPU1, a secure PPA API provided. CPU0 must be ON | |
47 | * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. | |
48 | * OMAP443X GP devices- SMP bit isn't accessible. | |
49 | * OMAP446X GP devices - SMP bit access is enabled on both CPUs. | |
50 | */ | |
51 | if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) | |
52 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, | |
53 | 4, 0, 0, 0, 0, 0); | |
54 | ||
367cd31e SS |
55 | /* |
56 | * If any interrupts are already enabled for the primary | |
57 | * core (e.g. timer irq), then they will not have been enabled | |
58 | * for us: do so | |
59 | */ | |
38489533 | 60 | gic_secondary_init(0); |
367cd31e SS |
61 | |
62 | /* | |
63 | * Synchronise with the boot thread. | |
64 | */ | |
65 | spin_lock(&boot_lock); | |
66 | spin_unlock(&boot_lock); | |
67 | } | |
68 | ||
69 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
70 | { | |
367cd31e SS |
71 | /* |
72 | * Set synchronisation state between this boot processor | |
73 | * and the secondary one | |
74 | */ | |
75 | spin_lock(&boot_lock); | |
76 | ||
77 | /* | |
942e2c9e | 78 | * Update the AuxCoreBoot0 with boot state for secondary core. |
367cd31e SS |
79 | * omap_secondary_startup() routine will hold the secondary core till |
80 | * the AuxCoreBoot1 register is updated with cpu state | |
81 | * A barrier is added to ensure that write buffer is drained | |
82 | */ | |
7d35b8d0 | 83 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
942e2c9e | 84 | flush_cache_all(); |
367cd31e | 85 | smp_wmb(); |
0f7b332f | 86 | gic_raise_softirq(cpumask_of(cpu), 1); |
367cd31e | 87 | |
367cd31e SS |
88 | /* |
89 | * Now the secondary core is starting up let it run its | |
90 | * calibrations, then wait for it to finish | |
91 | */ | |
92 | spin_unlock(&boot_lock); | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static void __init wakeup_secondary(void) | |
98 | { | |
99 | /* | |
100 | * Write the address of secondary startup routine into the | |
942e2c9e | 101 | * AuxCoreBoot1 where ROM code will jump and start executing |
367cd31e SS |
102 | * on secondary core once out of WFE |
103 | * A barrier is added to ensure that write buffer is drained | |
104 | */ | |
942e2c9e | 105 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
367cd31e SS |
106 | smp_wmb(); |
107 | ||
108 | /* | |
109 | * Send a 'sev' to wake the secondary core from WFE. | |
942e2c9e | 110 | * Drain the outstanding writes to memory |
367cd31e | 111 | */ |
a4192d32 | 112 | dsb_sev(); |
367cd31e SS |
113 | mb(); |
114 | } | |
115 | ||
116 | /* | |
117 | * Initialise the CPU possible map early - this describes the CPUs | |
118 | * which may be present or become present in the system. | |
119 | */ | |
120 | void __init smp_init_cpus(void) | |
121 | { | |
e4e7a13a TL |
122 | unsigned int i, ncores; |
123 | ||
4c3cf901 TL |
124 | /* |
125 | * Currently we can't call ioremap here because | |
126 | * SoC detection won't work until after init_early. | |
127 | */ | |
128 | scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); | |
e4e7a13a TL |
129 | BUG_ON(!scu_base); |
130 | ||
fd778f0a | 131 | ncores = scu_get_core_count(scu_base); |
367cd31e SS |
132 | |
133 | /* sanity check */ | |
a06f916b RK |
134 | if (ncores > nr_cpu_ids) { |
135 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
136 | ncores, nr_cpu_ids); | |
137 | ncores = nr_cpu_ids; | |
367cd31e | 138 | } |
367cd31e | 139 | |
bbc3d14e RK |
140 | for (i = 0; i < ncores; i++) |
141 | set_cpu_possible(i, true); | |
0f7b332f RK |
142 | |
143 | set_smp_cross_call(gic_raise_softirq); | |
bbc3d14e RK |
144 | } |
145 | ||
05c74a6c | 146 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
bbc3d14e | 147 | { |
367cd31e | 148 | |
05c74a6c RK |
149 | /* |
150 | * Initialise the SCU and wake up the secondary core using | |
151 | * wakeup_secondary(). | |
152 | */ | |
153 | scu_enable(scu_base); | |
154 | wakeup_secondary(); | |
367cd31e | 155 | } |