[linux-2.6-block.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR
 *	OFF		OFF		OFF(Device OFF *TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include "soc.h"
#include "common.h"
#include "omap44xx.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"

#ifdef CONFIG_SMP

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
	void __iomem *l2x0_sar_addr;
	void (*secondary_startup)(void);
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static void __iomem *sar_base;

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	__raw_writel(addr, pm_info->wkup_sar_addr);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
}

/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}

static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
{
	u32 reg;

	if (cpu_id) {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	} else {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	}
}

/*
 * Store the CPU cluster state for L2X0 low power operations.
 */
static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	__raw_writel(save_state, pm_info->l2x0_sar_addr);
}

/*
 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 * in every restore MPUSS OFF path.
 */
#ifdef CONFIG_CACHE_L2X0
static void save_l2x0_context(void)
{
	u32 val;
	void __iomem *l2x0_base = omap4_get_l2cache_base();

	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
	val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
	__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
}
#else
static void save_l2x0_context(void)
{}
#endif

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int save_state = 0;
	unsigned int wakeup_cpu;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_pre_transition(NULL);

	/*
	 * Check MPUSS next state and save interrupt controller if needed.
	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
	 */
	mpuss_clear_prev_logic_pwrst();
	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
		save_state = 2;

	cpu_clear_prev_logic_pwrst(cpu);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
	scu_pwrst_prepare(cpu, power_state);
	l2x0_pwrst_prepare(cpu, save_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	cpu_suspend(save_state, omap4_finish_suspend);

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	wakeup_cpu = smp_processor_id();
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pwrdm_post_transition(NULL);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
	scu_pwrst_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap_secondary_startup().
	 */
	omap4_finish_suspend(cpu_state);

	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	return 0;
}


/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	sar_base = omap4_get_sar_ram_base();

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(0);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	if (cpu_is_omap446x())
		pm_info->secondary_startup = omap_secondary_startup_4460;
	else
		pm_info->secondary_startup = omap_secondary_startup;

	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(1);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	mpuss_clear_prev_logic_pwrst();

	/* Save device type on scratchpad for low level code to use */
	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
		__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	else
		__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);

	save_l2x0_context();

	return 0;
}

#endif
Commit	Line	Data
b2b9762f SS	1	/*
	2	* OMAP MPUSS low power code
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	*
	7	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	8	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	9	* CPU0 and CPU1 LPRM modules.
	10	* CPU0, CPU1 and MPUSS each have there own power domain and
	11	* hence multiple low power combinations of MPUSS are possible.
	12	*
	13	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	14	* because the mode is not supported by hw constraints of dormant
	15	* mode. While waking up from the dormant mode, a reset signal
	16	* to the Cortex-A9 processor must be asserted by the external
	17	* power controller.
	18	*
	19	* With architectural inputs and hardware recommendations, only
	20	* below modes are supported from power gain vs latency point of view.
	21	*
	22	* CPU0 CPU1 MPUSS
	23	* ----------------------------------------------
	24	* ON ON ON
	25	* ON(Inactive) OFF ON(Inactive)
	26	* OFF OFF CSWR
3ba2a739 SS	27	* OFF OFF OSWR
3ba2a739 SS	28	* OFF OFF OFF(Device OFF *TBD)
b2b9762f SS	29	* ----------------------------------------------
	30	*
	31	* Note: CPU0 is the master core and it is the last CPU to go down
	32	* and first to wake-up when MPUSS low power states are excercised
	33	*
	34	*
	35	* This program is free software; you can redistribute it and/or modify
	36	* it under the terms of the GNU General Public License version 2 as
	37	* published by the Free Software Foundation.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/io.h>
	42	#include <linux/errno.h>
	43	#include <linux/linkage.h>
	44	#include <linux/smp.h>
	45
	46	#include <asm/cacheflush.h>
	47	#include <asm/tlbflush.h>
	48	#include <asm/smp_scu.h>
b2b9762f SS	49	#include <asm/pgalloc.h>
b2b9762f SS	50	#include <asm/suspend.h>
5e94c6e3	51	#include <asm/hardware/cache-l2x0.h>
b2b9762f	52
e4c060db	53	#include "soc.h"
b2b9762f	54	#include "common.h"
c49f34bc	55	#include "omap44xx.h"
b2b9762f SS	56	#include "omap4-sar-layout.h"
b2b9762f SS	57	#include "pm.h"
3ba2a739 SS	58	#include "prcm_mpu44xx.h"
	59	#include "prminst44xx.h"
	60	#include "prcm44xx.h"
	61	#include "prm44xx.h"
	62	#include "prm-regbits-44xx.h"
b2b9762f SS	63
	64	#ifdef CONFIG_SMP
	65
	66	struct omap4_cpu_pm_info {
	67	struct powerdomain *pwrdm;
	68	void __iomem *scu_sar_addr;
	69	void __iomem *wkup_sar_addr;
5e94c6e3	70	void __iomem *l2x0_sar_addr;
ff999b8a	71	void (*secondary_startup)(void);
b2b9762f SS	72	};
	73
	74	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	75	static struct powerdomain *mpuss_pd;
5e94c6e3	76	static void __iomem *sar_base;
b2b9762f SS	77
	78	/*
	79	* Program the wakeup routine address for the CPU0 and CPU1
	80	* used for OFF or DORMANT wakeup.
	81	*/
	82	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	83	{
	84	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	85
	86	__raw_writel(addr, pm_info->wkup_sar_addr);
	87	}
	88
b2b9762f SS	89	/*
	90	* Store the SCU power status value to scratchpad memory
	91	*/
	92	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	93	{
	94	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	95	u32 scu_pwr_st;
	96
	97	switch (cpu_state) {
	98	case PWRDM_POWER_RET:
	99	scu_pwr_st = SCU_PM_DORMANT;
	100	break;
	101	case PWRDM_POWER_OFF:
	102	scu_pwr_st = SCU_PM_POWEROFF;
	103	break;
	104	case PWRDM_POWER_ON:
	105	case PWRDM_POWER_INACTIVE:
	106	default:
	107	scu_pwr_st = SCU_PM_NORMAL;
	108	break;
	109	}
	110
	111	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
	112	}
	113
3ba2a739 SS	114	/* Helper functions for MPUSS OSWR */
	115	static inline void mpuss_clear_prev_logic_pwrst(void)
	116	{
	117	u32 reg;
	118
	119	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	120	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	121	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
	122	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	123	}
	124
	125	static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
	126	{
	127	u32 reg;
	128
	129	if (cpu_id) {
	130	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
	131	OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	132	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
	133	OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	134	} else {
	135	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
	136	OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	137	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
	138	OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	139	}
	140	}
	141
5e94c6e3 SS	142	/*
	143	* Store the CPU cluster state for L2X0 low power operations.
	144	*/
	145	static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
	146	{
	147	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	148
	149	__raw_writel(save_state, pm_info->l2x0_sar_addr);
	150	}
	151
	152	/*
	153	* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
	154	* in every restore MPUSS OFF path.
	155	*/
	156	#ifdef CONFIG_CACHE_L2X0
	157	static void save_l2x0_context(void)
	158	{
	159	u32 val;
	160	void __iomem *l2x0_base = omap4_get_l2cache_base();
	161
	162	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
	163	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
	164	val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
	165	__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	166	}
	167	#else
	168	static void save_l2x0_context(void)
	169	{}
	170	#endif
	171
b2b9762f SS	172	/**
	173	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
	174	* The purpose of this function is to manage low power programming
	175	* of OMAP4 MPUSS subsystem
	176	* @cpu : CPU ID
	177	* @power_state: Low power state.
e44f9a77 SS	178	*
	179	* MPUSS states for the context save:
	180	* save_state =
	181	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	182	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	183	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	184	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	185	*/
	186	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	187	{
32d174ed	188	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
b2b9762f SS	189	unsigned int save_state = 0;
	190	unsigned int wakeup_cpu;
	191
	192	if (omap_rev() == OMAP4430_REV_ES1_0)
	193	return -ENXIO;
	194
	195	switch (power_state) {
	196	case PWRDM_POWER_ON:
	197	case PWRDM_POWER_INACTIVE:
	198	save_state = 0;
	199	break;
	200	case PWRDM_POWER_OFF:
	201	save_state = 1;
	202	break;
	203	case PWRDM_POWER_RET:
	204	default:
	205	/*
	206	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	207	* doesn't make much scense, since logic is lost and $L1
	208	* needs to be cleaned because of coherency. This makes
	209	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	210	*/
	211	WARN_ON(1);
	212	return -ENXIO;
	213	}
	214
e0555489	215	pwrdm_pre_transition(NULL);
49404dd0	216
3ba2a739 SS	217	/*
	218	* Check MPUSS next state and save interrupt controller if needed.
	219	* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
	220	*/
	221	mpuss_clear_prev_logic_pwrst();
3ba2a739 SS	222	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
	223	(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
	224	save_state = 2;
	225
3ba2a739	226	cpu_clear_prev_logic_pwrst(cpu);
32d174ed	227	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
b2b9762f SS	228	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
b2b9762f SS	229	scu_pwrst_prepare(cpu, power_state);
5e94c6e3	230	l2x0_pwrst_prepare(cpu, save_state);
b2b9762f SS	231
	232	/*
	233	* Call low level function with targeted low power state.
	234	*/
	235	cpu_suspend(save_state, omap4_finish_suspend);
	236
	237	/*
	238	* Restore the CPUx power state to ON otherwise CPUx
	239	* power domain can transitions to programmed low power
	240	* state while doing WFI outside the low powe code. On
	241	* secure devices, CPUx does WFI which can result in
	242	* domain transition
	243	*/
	244	wakeup_cpu = smp_processor_id();
32d174ed	245	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b2b9762f	246
e0555489	247	pwrdm_post_transition(NULL);
49404dd0	248
b2b9762f SS	249	return 0;
	250	}
	251
b5b4f288 SS	252	/**
	253	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	254	* @cpu : CPU ID
	255	* @power_state: CPU low power state.
	256	*/
ccdeed62	257	int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
b5b4f288	258	{
ff999b8a	259	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
32d174ed	260	unsigned int cpu_state = 0;
b5b4f288 SS	261
	262	if (omap_rev() == OMAP4430_REV_ES1_0)
	263	return -ENXIO;
	264
	265	if (power_state == PWRDM_POWER_OFF)
	266	cpu_state = 1;
	267
32d174ed PW	268	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
32d174ed PW	269	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
ff999b8a	270	set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
b5b4f288 SS	271	scu_pwrst_prepare(cpu, power_state);
	272
	273	/*
260db902	274	* CPU never retuns back if targeted power state is OFF mode.
b5b4f288 SS	275	* CPU ONLINE follows normal CPU ONLINE ptah via
	276	* omap_secondary_startup().
	277	*/
	278	omap4_finish_suspend(cpu_state);
	279
32d174ed	280	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b5b4f288 SS	281	return 0;
	282	}
	283
	284
b2b9762f SS	285	/*
	286	* Initialise OMAP4 MPUSS
	287	*/
	288	int __init omap4_mpuss_init(void)
	289	{
	290	struct omap4_cpu_pm_info *pm_info;
b2b9762f SS	291
	292	if (omap_rev() == OMAP4430_REV_ES1_0) {
	293	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	294	return -ENODEV;
	295	}
	296
5e94c6e3 SS	297	sar_base = omap4_get_sar_ram_base();
5e94c6e3 SS	298
b2b9762f SS	299	/* Initilaise per CPU PM information */
	300	pm_info = &per_cpu(omap4_pm_info, 0x0);
	301	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	302	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
5e94c6e3	303	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
b2b9762f SS	304	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	305	if (!pm_info->pwrdm) {
	306	pr_err("Lookup failed for CPU0 pwrdm\n");
	307	return -ENODEV;
	308	}
	309
	310	/* Clear CPU previous power domain state */
	311	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	312	cpu_clear_prev_logic_pwrst(0);
b2b9762f SS	313
	314	/* Initialise CPU0 power domain state to ON */
	315	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	316
	317	pm_info = &per_cpu(omap4_pm_info, 0x1);
	318	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	319	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
5e94c6e3	320	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
ff999b8a SS	321	if (cpu_is_omap446x())
	322	pm_info->secondary_startup = omap_secondary_startup_4460;
	323	else
	324	pm_info->secondary_startup = omap_secondary_startup;
	325
b2b9762f SS	326	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	327	if (!pm_info->pwrdm) {
	328	pr_err("Lookup failed for CPU1 pwrdm\n");
	329	return -ENODEV;
	330	}
	331
	332	/* Clear CPU previous power domain state */
	333	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	334	cpu_clear_prev_logic_pwrst(1);
b2b9762f SS	335
	336	/* Initialise CPU1 power domain state to ON */
	337	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	338
e44f9a77 SS	339	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	340	if (!mpuss_pd) {
	341	pr_err("Failed to lookup MPUSS power domain\n");
	342	return -ENODEV;
	343	}
	344	pwrdm_clear_all_prev_pwrst(mpuss_pd);
3ba2a739	345	mpuss_clear_prev_logic_pwrst();
e44f9a77	346
b2b9762f SS	347	/* Save device type on scratchpad for low level code to use */
	348	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
	349	__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	350	else
	351	__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
	352
5e94c6e3 SS	353	save_l2x0_context();
5e94c6e3 SS	354
b2b9762f SS	355	return 0;
	356	}
	357
	358	#endif