[linux-block.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR
 *	OFF		OFF		OFF(Device OFF *TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <asm/virt.h>
#include <asm/hardware/cache-l2x0.h>

#include "soc.h"
#include "common.h"
#include "omap44xx.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
#include "prcm_mpu54xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"

static void __iomem *sar_base;
static u32 old_cpu1_ns_pa_addr;

#if defined(CONFIG_PM) && defined(CONFIG_SMP)

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
	void __iomem *l2x0_sar_addr;
};

/**
 * struct cpu_pm_ops - CPU pm operations
 * @finish_suspend:	CPU suspend finisher function pointer
 * @resume:		CPU resume function pointer
 * @scu_prepare:	CPU Snoop Control program function pointer
 * @hotplug_restart:	CPU restart function pointer
 *
 * Structure holds functions pointer for CPU low power operations like
 * suspend, resume and scu programming.
 */
struct cpu_pm_ops {
	int (*finish_suspend)(unsigned long cpu_state);
	void (*resume)(void);
	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
	void (*hotplug_restart)(void);
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static u32 cpu_context_offset;

static int default_finish_suspend(unsigned long cpu_state)
{
	omap_do_wfi();
	return 0;
}

static void dummy_cpu_resume(void)
{}

static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
{}

static struct cpu_pm_ops omap_pm_ops = {
	.finish_suspend		= default_finish_suspend,
	.resume			= dummy_cpu_resume,
	.scu_prepare		= dummy_scu_prepare,
	.hotplug_restart	= dummy_cpu_resume,
};

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->wkup_sar_addr)
		writel_relaxed(addr, pm_info->wkup_sar_addr);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	if (pm_info->scu_sar_addr)
		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
}

/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}

static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
{
	u32 reg;

	if (cpu_id) {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
	} else {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
	}
}

/*
 * Store the CPU cluster state for L2X0 low power operations.
 */
static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->l2x0_sar_addr)
		writel_relaxed(save_state, pm_info->l2x0_sar_addr);
}

/*
 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 * in every restore MPUSS OFF path.
 */
#ifdef CONFIG_CACHE_L2X0
static void __init save_l2x0_context(void)
{
	void __iomem *l2x0_base = omap4_get_l2cache_base();

	if (l2x0_base && sar_base) {
		writel_relaxed(l2x0_saved_regs.aux_ctrl,
			       sar_base + L2X0_AUXCTRL_OFFSET);
		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
			       sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	}
}
#else
static void __init save_l2x0_context(void)
{}
#endif

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		cpu_logic_state = PWRDM_POWER_OFF;
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
			save_state = 0;
		break;
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_pre_transition(NULL);

	/*
	 * Check MPUSS next state and save interrupt controller if needed.
	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
	 */
	mpuss_clear_prev_logic_pwrst();
	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
		save_state = 2;

	cpu_clear_prev_logic_pwrst(cpu);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
	omap_pm_ops.scu_prepare(cpu, power_state);
	l2x0_pwrst_prepare(cpu, save_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	if (save_state)
		cpu_suspend(save_state, omap_pm_ops.finish_suspend);
	else
		omap_pm_ops.finish_suspend(save_state);

	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
		gic_dist_enable();

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pwrdm_post_transition(NULL);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	/* Use the achievable power state for the domain */
	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
					       false, power_state);

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
	omap_pm_ops.scu_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap4_secondary_startup().
	 */
	omap_pm_ops.finish_suspend(cpu_state);

	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	return 0;
}


/*
 * Enable Mercury Fast HG retention mode by default.
 */
static void enable_mercury_retention_mode(void)
{
	u32 reg;

	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
				  OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	/* Enable HG_EN, HG_RAMPUP = fast mode */
	reg |= BIT(24) | BIT(25);
	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
				      OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
}

/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
		if (cpu_is_omap44xx())
			pm_info->wkup_sar_addr = sar_base +
				CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
		else
			pm_info->wkup_sar_addr = sar_base +
				OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	}
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(0);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
		if (cpu_is_omap44xx())
			pm_info->wkup_sar_addr = sar_base +
				CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
		else
			pm_info->wkup_sar_addr = sar_base +
				OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	}

	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(1);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	mpuss_clear_prev_logic_pwrst();

	if (sar_base) {
		/* Save device type on scratchpad for low level code to use */
		writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
			       sar_base + OMAP_TYPE_OFFSET);
		save_l2x0_context();
	}

	if (cpu_is_omap44xx()) {
		omap_pm_ops.finish_suspend = omap4_finish_suspend;
		omap_pm_ops.resume = omap4_cpu_resume;
		omap_pm_ops.scu_prepare = scu_pwrst_prepare;
		omap_pm_ops.hotplug_restart = omap4_secondary_startup;
		cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
		cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
		enable_mercury_retention_mode();
	}

	if (cpu_is_omap446x())
		omap_pm_ops.hotplug_restart = omap4460_secondary_startup;

	return 0;
}

#endif

u32 omap4_get_cpu1_ns_pa_addr(void)
{
	return old_cpu1_ns_pa_addr;
}

/*
 * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
 * current kernel's secondary_startup() early before
 * clockdomains_init(). Otherwise clockdomain_init() can
 * wake CPU1 and cause a hang.
 */
void __init omap4_mpuss_early_init(void)
{
	unsigned long startup_pa;
	void __iomem *ns_pa_addr;

	if (!(soc_is_omap44xx() || soc_is_omap54xx()))
		return;

	sar_base = omap4_get_sar_ram_base();

	/* Save old NS_PA_ADDR for validity checks later on */
	if (soc_is_omap44xx())
		ns_pa_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	else
		ns_pa_addr = sar_base + OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	old_cpu1_ns_pa_addr = readl_relaxed(ns_pa_addr);

	if (soc_is_omap443x())
		startup_pa = __pa_symbol(omap4_secondary_startup);
	else if (soc_is_omap446x())
		startup_pa = __pa_symbol(omap4460_secondary_startup);
	else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
		startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
	else
		startup_pa = __pa_symbol(omap5_secondary_startup);

	if (soc_is_omap44xx())
		writel_relaxed(startup_pa, sar_base +
			       CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
	else
		writel_relaxed(startup_pa, sar_base +
			       OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
b2b9762f SS	2	/*
	3	* OMAP MPUSS low power code
	4	*
	5	* Copyright (C) 2011 Texas Instruments, Inc.
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	9	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	10	* CPU0 and CPU1 LPRM modules.
	11	* CPU0, CPU1 and MPUSS each have there own power domain and
	12	* hence multiple low power combinations of MPUSS are possible.
	13	*
	14	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	15	* because the mode is not supported by hw constraints of dormant
	16	* mode. While waking up from the dormant mode, a reset signal
	17	* to the Cortex-A9 processor must be asserted by the external
	18	* power controller.
	19	*
	20	* With architectural inputs and hardware recommendations, only
	21	* below modes are supported from power gain vs latency point of view.
	22	*
	23	* CPU0 CPU1 MPUSS
	24	* ----------------------------------------------
	25	* ON ON ON
	26	* ON(Inactive) OFF ON(Inactive)
	27	* OFF OFF CSWR
3ba2a739 SS	28	* OFF OFF OSWR
3ba2a739 SS	29	* OFF OFF OFF(Device OFF *TBD)
b2b9762f SS	30	* ----------------------------------------------
	31	*
	32	* Note: CPU0 is the master core and it is the last CPU to go down
	33	* and first to wake-up when MPUSS low power states are excercised
b2b9762f SS	34	*/
	35
	36	#include <linux/kernel.h>
	37	#include <linux/io.h>
	38	#include <linux/errno.h>
	39	#include <linux/linkage.h>
	40	#include <linux/smp.h>
	41
	42	#include <asm/cacheflush.h>
	43	#include <asm/tlbflush.h>
	44	#include <asm/smp_scu.h>
b2b9762f	45	#include <asm/suspend.h>
8a8be46a	46	#include <asm/virt.h>
5e94c6e3	47	#include <asm/hardware/cache-l2x0.h>
b2b9762f	48
e4c060db	49	#include "soc.h"
b2b9762f	50	#include "common.h"
c49f34bc	51	#include "omap44xx.h"
b2b9762f SS	52	#include "omap4-sar-layout.h"
b2b9762f SS	53	#include "pm.h"
3ba2a739	54	#include "prcm_mpu44xx.h"
a89726d3	55	#include "prcm_mpu54xx.h"
3ba2a739 SS	56	#include "prminst44xx.h"
	57	#include "prcm44xx.h"
	58	#include "prm44xx.h"
	59	#include "prm-regbits-44xx.h"
b2b9762f	60
0573b957	61	static void __iomem *sar_base;
351b7c49	62	static u32 old_cpu1_ns_pa_addr;
0573b957	63
b3bf289c	64	#if defined(CONFIG_PM) && defined(CONFIG_SMP)
b2b9762f SS	65
	66	struct omap4_cpu_pm_info {
	67	struct powerdomain *pwrdm;
	68	void __iomem *scu_sar_addr;
	69	void __iomem *wkup_sar_addr;
5e94c6e3	70	void __iomem *l2x0_sar_addr;
b2b9762f SS	71	};
b2b9762f SS	72
9f192cf7 SS	73	/**
	74	* struct cpu_pm_ops - CPU pm operations
	75	* @finish_suspend: CPU suspend finisher function pointer
	76	* @resume: CPU resume function pointer
	77	* @scu_prepare: CPU Snoop Control program function pointer
e97c4eb3	78	* @hotplug_restart: CPU restart function pointer
9f192cf7 SS	79	*
	80	* Structure holds functions pointer for CPU low power operations like
	81	* suspend, resume and scu programming.
	82	*/
	83	struct cpu_pm_ops {
	84	int (*finish_suspend)(unsigned long cpu_state);
	85	void (*resume)(void);
	86	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
e97c4eb3	87	void (*hotplug_restart)(void);
9f192cf7 SS	88	};
9f192cf7 SS	89
b2b9762f	90	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	91	static struct powerdomain *mpuss_pd;
a89726d3	92	static u32 cpu_context_offset;
b2b9762f	93
9f192cf7 SS	94	static int default_finish_suspend(unsigned long cpu_state)
	95	{
	96	omap_do_wfi();
	97	return 0;
	98	}
	99
	100	static void dummy_cpu_resume(void)
	101	{}
	102
	103	static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
	104	{}
	105
f734a9b3	106	static struct cpu_pm_ops omap_pm_ops = {
9f192cf7 SS	107	.finish_suspend = default_finish_suspend,
	108	.resume = dummy_cpu_resume,
	109	.scu_prepare = dummy_scu_prepare,
e97c4eb3	110	.hotplug_restart = dummy_cpu_resume,
9f192cf7 SS	111	};
9f192cf7 SS	112
b2b9762f SS	113	/*
	114	* Program the wakeup routine address for the CPU0 and CPU1
	115	* used for OFF or DORMANT wakeup.
	116	*/
	117	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	118	{
	119	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	120
325f29da RN	121	if (pm_info->wkup_sar_addr)
325f29da RN	122	writel_relaxed(addr, pm_info->wkup_sar_addr);
b2b9762f SS	123	}
b2b9762f SS	124
b2b9762f SS	125	/*
	126	* Store the SCU power status value to scratchpad memory
	127	*/
	128	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	129	{
	130	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	131	u32 scu_pwr_st;
	132
	133	switch (cpu_state) {
	134	case PWRDM_POWER_RET:
	135	scu_pwr_st = SCU_PM_DORMANT;
	136	break;
	137	case PWRDM_POWER_OFF:
	138	scu_pwr_st = SCU_PM_POWEROFF;
	139	break;
	140	case PWRDM_POWER_ON:
	141	case PWRDM_POWER_INACTIVE:
	142	default:
	143	scu_pwr_st = SCU_PM_NORMAL;
	144	break;
	145	}
	146
325f29da RN	147	if (pm_info->scu_sar_addr)
325f29da RN	148	writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
b2b9762f SS	149	}
b2b9762f SS	150
3ba2a739 SS	151	/* Helper functions for MPUSS OSWR */
	152	static inline void mpuss_clear_prev_logic_pwrst(void)
	153	{
	154	u32 reg;
	155
	156	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	157	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	158	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
	159	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	160	}
	161
	162	static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
	163	{
	164	u32 reg;
	165
	166	if (cpu_id) {
	167	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	168	cpu_context_offset);
3ba2a739	169	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	170	cpu_context_offset);
3ba2a739 SS	171	} else {
3ba2a739 SS	172	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	173	cpu_context_offset);
3ba2a739	174	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	175	cpu_context_offset);
3ba2a739 SS	176	}
	177	}
	178
5e94c6e3 SS	179	/*
	180	* Store the CPU cluster state for L2X0 low power operations.
	181	*/
	182	static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
	183	{
	184	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	185
325f29da RN	186	if (pm_info->l2x0_sar_addr)
325f29da RN	187	writel_relaxed(save_state, pm_info->l2x0_sar_addr);
5e94c6e3 SS	188	}
	189
	190	/*
	191	* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
	192	* in every restore MPUSS OFF path.
	193	*/
	194	#ifdef CONFIG_CACHE_L2X0
7a09b28e	195	static void __init save_l2x0_context(void)
5e94c6e3	196	{
325f29da RN	197	void __iomem *l2x0_base = omap4_get_l2cache_base();
	198
	199	if (l2x0_base && sar_base) {
	200	writel_relaxed(l2x0_saved_regs.aux_ctrl,
	201	sar_base + L2X0_AUXCTRL_OFFSET);
	202	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
	203	sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	204	}
5e94c6e3 SS	205	}
5e94c6e3 SS	206	#else
7a09b28e	207	static void __init save_l2x0_context(void)
5e94c6e3 SS	208	{}
	209	#endif
	210
b2b9762f SS	211	/**
	212	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
	213	* The purpose of this function is to manage low power programming
	214	* of OMAP4 MPUSS subsystem
	215	* @cpu : CPU ID
	216	* @power_state: Low power state.
e44f9a77 SS	217	*
	218	* MPUSS states for the context save:
	219	* save_state =
	220	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	221	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	222	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	223	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	224	*/
	225	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	226	{
32d174ed	227	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
a30d81b9	228	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
b2b9762f SS	229
	230	if (omap_rev() == OMAP4430_REV_ES1_0)
	231	return -ENXIO;
	232
	233	switch (power_state) {
	234	case PWRDM_POWER_ON:
	235	case PWRDM_POWER_INACTIVE:
	236	save_state = 0;
	237	break;
	238	case PWRDM_POWER_OFF:
a30d81b9	239	cpu_logic_state = PWRDM_POWER_OFF;
b2b9762f SS	240	save_state = 1;
	241	break;
	242	case PWRDM_POWER_RET:
cbf26428	243	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
6099dd37	244	save_state = 0;
cbf26428	245	break;
b2b9762f SS	246	default:
	247	/*
	248	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	249	* doesn't make much scense, since logic is lost and $L1
	250	* needs to be cleaned because of coherency. This makes
	251	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	252	*/
	253	WARN_ON(1);
	254	return -ENXIO;
	255	}
	256
e0555489	257	pwrdm_pre_transition(NULL);
49404dd0	258
3ba2a739 SS	259	/*
	260	* Check MPUSS next state and save interrupt controller if needed.
	261	* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
	262	*/
	263	mpuss_clear_prev_logic_pwrst();
3ba2a739 SS	264	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
	265	(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
	266	save_state = 2;
	267
3ba2a739	268	cpu_clear_prev_logic_pwrst(cpu);
32d174ed	269	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
a30d81b9	270	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
64fc2a94	271	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
9f192cf7	272	omap_pm_ops.scu_prepare(cpu, power_state);
5e94c6e3	273	l2x0_pwrst_prepare(cpu, save_state);
b2b9762f SS	274
	275	/*
	276	* Call low level function with targeted low power state.
	277	*/
72433eba	278	if (save_state)
9f192cf7	279	cpu_suspend(save_state, omap_pm_ops.finish_suspend);
72433eba	280	else
9f192cf7	281	omap_pm_ops.finish_suspend(save_state);
b2b9762f	282
74ed7bdc SG	283	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
	284	gic_dist_enable();
	285
b2b9762f SS	286	/*
	287	* Restore the CPUx power state to ON otherwise CPUx
	288	* power domain can transitions to programmed low power
	289	* state while doing WFI outside the low powe code. On
	290	* secure devices, CPUx does WFI which can result in
	291	* domain transition
	292	*/
32d174ed	293	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b2b9762f	294
e0555489	295	pwrdm_post_transition(NULL);
49404dd0	296
b2b9762f SS	297	return 0;
	298	}
	299
b5b4f288 SS	300	/**
	301	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	302	* @cpu : CPU ID
	303	* @power_state: CPU low power state.
	304	*/
8bd26e3a	305	int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
b5b4f288	306	{
ff999b8a	307	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
32d174ed	308	unsigned int cpu_state = 0;
b5b4f288 SS	309
	310	if (omap_rev() == OMAP4430_REV_ES1_0)
	311	return -ENXIO;
	312
3e6a1c94 NM	313	/* Use the achievable power state for the domain */
	314	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
	315	false, power_state);
	316
b5b4f288 SS	317	if (power_state == PWRDM_POWER_OFF)
	318	cpu_state = 1;
	319
32d174ed PW	320	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
32d174ed PW	321	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
64fc2a94	322	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
9f192cf7	323	omap_pm_ops.scu_prepare(cpu, power_state);
b5b4f288 SS	324
b5b4f288 SS	325	/*
260db902	326	* CPU never retuns back if targeted power state is OFF mode.
b5b4f288	327	* CPU ONLINE follows normal CPU ONLINE ptah via
baf4b7d3	328	* omap4_secondary_startup().
b5b4f288	329	*/
9f192cf7	330	omap_pm_ops.finish_suspend(cpu_state);
b5b4f288	331
32d174ed	332	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b5b4f288 SS	333	return 0;
	334	}
	335
	336
6d846c46 SS	337	/*
	338	* Enable Mercury Fast HG retention mode by default.
	339	*/
	340	static void enable_mercury_retention_mode(void)
	341	{
	342	u32 reg;
	343
	344	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
	345	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	346	/* Enable HG_EN, HG_RAMPUP = fast mode */
	347	reg \|= BIT(24) \| BIT(25);
	348	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
	349	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	350	}
	351
b2b9762f SS	352	/*
	353	* Initialise OMAP4 MPUSS
	354	*/
	355	int __init omap4_mpuss_init(void)
	356	{
	357	struct omap4_cpu_pm_info *pm_info;
b2b9762f SS	358
	359	if (omap_rev() == OMAP4430_REV_ES1_0) {
	360	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	361	return -ENODEV;
	362	}
	363
	364	/* Initilaise per CPU PM information */
	365	pm_info = &per_cpu(omap4_pm_info, 0x0);
325f29da RN	366	if (sar_base) {
325f29da RN	367	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
8a8be46a TL	368	if (cpu_is_omap44xx())
	369	pm_info->wkup_sar_addr = sar_base +
	370	CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	371	else
	372	pm_info->wkup_sar_addr = sar_base +
	373	OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
325f29da RN	374	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
325f29da RN	375	}
b2b9762f SS	376	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	377	if (!pm_info->pwrdm) {
	378	pr_err("Lookup failed for CPU0 pwrdm\n");
	379	return -ENODEV;
	380	}
	381
	382	/* Clear CPU previous power domain state */
	383	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	384	cpu_clear_prev_logic_pwrst(0);
b2b9762f SS	385
	386	/* Initialise CPU0 power domain state to ON */
	387	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	388
	389	pm_info = &per_cpu(omap4_pm_info, 0x1);
325f29da RN	390	if (sar_base) {
325f29da RN	391	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
8a8be46a TL	392	if (cpu_is_omap44xx())
	393	pm_info->wkup_sar_addr = sar_base +
	394	CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	395	else
	396	pm_info->wkup_sar_addr = sar_base +
	397	OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
325f29da RN	398	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
325f29da RN	399	}
ff999b8a	400
b2b9762f SS	401	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	402	if (!pm_info->pwrdm) {
	403	pr_err("Lookup failed for CPU1 pwrdm\n");
	404	return -ENODEV;
	405	}
	406
	407	/* Clear CPU previous power domain state */
	408	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	409	cpu_clear_prev_logic_pwrst(1);
b2b9762f SS	410
	411	/* Initialise CPU1 power domain state to ON */
	412	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	413
e44f9a77 SS	414	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	415	if (!mpuss_pd) {
	416	pr_err("Failed to lookup MPUSS power domain\n");
	417	return -ENODEV;
	418	}
	419	pwrdm_clear_all_prev_pwrst(mpuss_pd);
3ba2a739	420	mpuss_clear_prev_logic_pwrst();
e44f9a77	421
325f29da RN	422	if (sar_base) {
	423	/* Save device type on scratchpad for low level code to use */
	424	writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
	425	sar_base + OMAP_TYPE_OFFSET);
	426	save_l2x0_context();
	427	}
5e94c6e3	428
9f192cf7 SS	429	if (cpu_is_omap44xx()) {
	430	omap_pm_ops.finish_suspend = omap4_finish_suspend;
	431	omap_pm_ops.resume = omap4_cpu_resume;
	432	omap_pm_ops.scu_prepare = scu_pwrst_prepare;
e97c4eb3	433	omap_pm_ops.hotplug_restart = omap4_secondary_startup;
a89726d3 SS	434	cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	435	} else if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
	436	cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
6d846c46	437	enable_mercury_retention_mode();
9f192cf7 SS	438	}
9f192cf7 SS	439
e97c4eb3 SS	440	if (cpu_is_omap446x())
	441	omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
	442
b2b9762f SS	443	return 0;
	444	}
	445
	446	#endif
0573b957	447
6f921208 AB	448	u32 omap4_get_cpu1_ns_pa_addr(void)
	449	{
	450	return old_cpu1_ns_pa_addr;
	451	}
	452
0573b957 TL	453	/*
	454	* For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
	455	* current kernel's secondary_startup() early before
	456	* clockdomains_init(). Otherwise clockdomain_init() can
	457	* wake CPU1 and cause a hang.
	458	*/
	459	void __init omap4_mpuss_early_init(void)
	460	{
	461	unsigned long startup_pa;
351b7c49	462	void __iomem *ns_pa_addr;
0573b957	463
351b7c49	464	if (!(soc_is_omap44xx() \|\| soc_is_omap54xx()))
0573b957 TL	465	return;
	466
	467	sar_base = omap4_get_sar_ram_base();
	468
351b7c49 TL	469	/* Save old NS_PA_ADDR for validity checks later on */
	470	if (soc_is_omap44xx())
	471	ns_pa_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	472	else
	473	ns_pa_addr = sar_base + OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	474	old_cpu1_ns_pa_addr = readl_relaxed(ns_pa_addr);
	475
	476	if (soc_is_omap443x())
64fc2a94	477	startup_pa = __pa_symbol(omap4_secondary_startup);
351b7c49	478	else if (soc_is_omap446x())
64fc2a94	479	startup_pa = __pa_symbol(omap4460_secondary_startup);
8a8be46a	480	else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
64fc2a94	481	startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
8a8be46a	482	else
64fc2a94	483	startup_pa = __pa_symbol(omap5_secondary_startup);
0573b957	484
351b7c49	485	if (soc_is_omap44xx())
8a8be46a TL	486	writel_relaxed(startup_pa, sar_base +
	487	CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
	488	else
	489	writel_relaxed(startup_pa, sar_base +
	490	OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
0573b957	491	}