projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 367cd31e SS |
1 | /* |
| 2 | * Secondary CPU startup routine source file. | |
| 3 | * | |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * Author: | |
| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| 8 | * | |
| 9 | * Interface functions needed for the SMP. This file is based on arm | |
| 10 | * realview smp platform. | |
| 11 | * Copyright (c) 2003 ARM Limited. | |
| 12 | * | |
| 13 | * This program is free software,you can redistribute it and/or modify | |
| 14 | * it under the terms of the GNU General Public License version 2 as | |
| 15 | * published by the Free Software Foundation. | |
| 16 | */ | |
| 17 | ||
| 18 | #include <linux/linkage.h> | |
| 19 | #include <linux/init.h> | |
| 20 | ||
| 21 | /* Physical address needed since MMU not enabled yet on secondary core */ | |
| 22 | #define OMAP4_AUX_CORE_BOOT1_PA 0x48281804 | |
| 23 | ||
| 24 | __INIT | |
| 25 | ||
| 26 | /* | |
| 27 | * OMAP4 specific entry point for secondary CPU to jump from ROM | |
| 28 | * code. This routine also provides a holding flag into which | |
| 29 | * secondary core is held until we're ready for it to initialise. | |
| 942e2c9e SS |
30 | * The primary core will update this flag using a hardware |
| 31 | * register AuxCoreBoot0. | |
| 367cd31e SS |
32 | */ |
| 33 | ENTRY(omap_secondary_startup) | |
| 942e2c9e SS |
34 | hold: ldr r12,=0x103 |
| 35 | dsb | |
| df571c4a | 36 | smc #0 @ read from AuxCoreBoot0 |
| 942e2c9e SS |
37 | mov r0, r0, lsr #9 |
| 38 | mrc p15, 0, r4, c0, c0, 5 | |
| 39 | and r4, r4, #0x0f | |
| 40 | cmp r0, r4 | |
| 367cd31e SS |
41 | bne hold |
| 42 | ||
| 43 | /* | |
| 942e2c9e | 44 | * we've been released from the wait loop,secondary_stack |
| 367cd31e SS |
45 | * should now contain the SVC stack for this core |
| 46 | */ | |
| 47 | b secondary_startup | |
| 942e2c9e | 48 | END(omap_secondary_startup) |
| 367cd31e | 49 | |
| 942e2c9e SS |
50 | |
| 51 | ENTRY(omap_modify_auxcoreboot0) | |
| 52 | stmfd sp!, {r1-r12, lr} | |
| 53 | ldr r12, =0x104 | |
| 54 | dsb | |
| df571c4a | 55 | smc #0 |
| 942e2c9e SS |
56 | ldmfd sp!, {r1-r12, pc} |
| 57 | END(omap_modify_auxcoreboot0) | |
| 58 | ||
| 59 | ENTRY(omap_auxcoreboot_addr) | |
| 60 | stmfd sp!, {r2-r12, lr} | |
| 61 | ldr r12, =0x105 | |
| 62 | dsb | |
| df571c4a | 63 | smc #0 |
| 942e2c9e SS |
64 | ldmfd sp!, {r2-r12, pc} |
| 65 | END(omap_auxcoreboot_addr) |