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a041a52c BC |
1 | /* |
2 | * OMAP44xx MUX registers and bitfields | |
3 | * | |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | |
5 | * | |
6 | * Benoit Cousson (b-cousson@ti.com) | |
7 | * | |
8 | * This file is automatically generated from the OMAP hardware databases. | |
9 | * We respectfully ask that any modifications to this file be coordinated | |
10 | * with the public linux-omap@vger.kernel.org mailing list and the | |
11 | * authors above to ensure that the autogeneration scripts are kept | |
12 | * up-to-date with the file contents. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | |
20 | #define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | |
21 | ||
22 | #define OMAP4_MUX(M0, mux_value) \ | |
23 | { \ | |
24 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | |
25 | .value = (mux_value), \ | |
26 | } | |
27 | ||
28 | /* ctrl_module_pad_core base address */ | |
29 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 | |
30 | ||
31 | /* ctrl_module_pad_core registers offset */ | |
32 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 | |
33 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 | |
34 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 | |
35 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 | |
36 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 | |
37 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a | |
38 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c | |
39 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e | |
40 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 | |
41 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 | |
42 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 | |
43 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 | |
44 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 | |
45 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a | |
46 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c | |
47 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e | |
48 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 | |
49 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 | |
50 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 | |
51 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 | |
52 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 | |
53 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a | |
54 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c | |
55 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e | |
56 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 | |
57 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 | |
58 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 | |
59 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 | |
60 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 | |
61 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a | |
62 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c | |
63 | #define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e | |
64 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 | |
65 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 | |
66 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 | |
67 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 | |
68 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 | |
69 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a | |
70 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c | |
71 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e | |
72 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 | |
73 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 | |
74 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 | |
75 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 | |
76 | #define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 | |
77 | #define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a | |
78 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c | |
79 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e | |
80 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 | |
81 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 | |
82 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 | |
83 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 | |
84 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 | |
85 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa | |
86 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac | |
87 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae | |
88 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 | |
89 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 | |
90 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 | |
91 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 | |
92 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 | |
93 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba | |
94 | #define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc | |
95 | #define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be | |
96 | #define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 | |
97 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 | |
98 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 | |
99 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 | |
100 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 | |
101 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca | |
102 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc | |
103 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce | |
104 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 | |
105 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 | |
106 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 | |
107 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 | |
108 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 | |
109 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da | |
110 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc | |
111 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de | |
112 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 | |
113 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 | |
114 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 | |
115 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 | |
116 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 | |
117 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea | |
118 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec | |
119 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee | |
120 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 | |
121 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 | |
122 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 | |
123 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 | |
124 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 | |
125 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa | |
126 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc | |
127 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe | |
128 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 | |
129 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 | |
130 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 | |
131 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 | |
132 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 | |
133 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a | |
134 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c | |
135 | #define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e | |
136 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 | |
137 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 | |
138 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 | |
139 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 | |
140 | #define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 | |
141 | #define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a | |
142 | #define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c | |
143 | #define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e | |
144 | #define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 | |
145 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 | |
146 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 | |
147 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 | |
148 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 | |
149 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a | |
150 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c | |
151 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e | |
152 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 | |
153 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 | |
154 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 | |
155 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 | |
156 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 | |
157 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a | |
158 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c | |
159 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e | |
160 | #define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 | |
161 | #define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 | |
162 | #define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 | |
163 | #define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 | |
164 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 | |
165 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a | |
166 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c | |
167 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e | |
168 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 | |
169 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 | |
170 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 | |
171 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 | |
172 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 | |
173 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a | |
174 | #define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c | |
175 | #define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e | |
176 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 | |
177 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 | |
178 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 | |
179 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 | |
180 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 | |
181 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a | |
182 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c | |
183 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e | |
184 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 | |
185 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 | |
186 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 | |
187 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 | |
188 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 | |
189 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a | |
190 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c | |
191 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e | |
192 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 | |
193 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 | |
194 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 | |
195 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 | |
196 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 | |
197 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a | |
198 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c | |
199 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e | |
200 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 | |
201 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 | |
202 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 | |
203 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 | |
204 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 | |
205 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a | |
206 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c | |
207 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e | |
208 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 | |
209 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 | |
210 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 | |
211 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 | |
212 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 | |
213 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa | |
214 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac | |
215 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae | |
216 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 | |
217 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 | |
218 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 | |
219 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 | |
220 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 | |
221 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba | |
222 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc | |
223 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be | |
224 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 | |
225 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 | |
226 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 | |
227 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 | |
228 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 | |
229 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca | |
230 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc | |
231 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce | |
232 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 | |
233 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 | |
234 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 | |
235 | ||
a7722d87 BC |
236 | /* ES2.0 only */ |
237 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e | |
238 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 | |
239 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 | |
240 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 | |
241 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 | |
242 | ||
243 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c | |
244 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e | |
245 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 | |
246 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 | |
247 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 | |
248 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 | |
249 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 | |
250 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a | |
251 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c | |
252 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e | |
253 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 | |
254 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 | |
255 | ||
256 | ||
a041a52c BC |
257 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ |
258 | (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ | |
259 | - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) | |
260 | ||
261 | /* ctrl_module_pad_wkup base address */ | |
262 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 | |
263 | ||
264 | /* ctrl_module_pad_wkup registers offset */ | |
265 | #define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 | |
266 | #define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 | |
267 | #define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 | |
268 | #define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 | |
269 | #define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 | |
270 | #define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a | |
271 | #define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c | |
272 | #define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e | |
273 | #define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 | |
274 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 | |
275 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 | |
276 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 | |
277 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 | |
278 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a | |
279 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c | |
280 | #define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e | |
281 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 | |
282 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 | |
283 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 | |
284 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 | |
285 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 | |
286 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a | |
287 | #define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c | |
288 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e | |
289 | #define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 | |
290 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 | |
291 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 | |
292 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 | |
293 | ||
294 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ | |
295 | (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ | |
296 | - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) | |
297 | ||
298 | #endif |