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2b27bdcc | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ad1b6662 TL |
2 | /* |
3 | * MSDI IP block reset | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * Paul Walmsley | |
7 | * | |
ad1b6662 TL |
8 | * XXX What about pad muxing? |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
b955eefc | 12 | #include <linux/err.h> |
ad1b6662 | 13 | |
b13159af | 14 | #include "prm.h" |
ad1b6662 | 15 | #include "common.h" |
b955eefc | 16 | #include "control.h" |
2a296c8f | 17 | #include "omap_hwmod.h" |
25c7d49e | 18 | #include "omap_device.h" |
68f39e74 | 19 | #include "mmc.h" |
ad1b6662 TL |
20 | |
21 | /* | |
22 | * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register | |
23 | * from the IP block's base address | |
24 | */ | |
25 | #define MSDI_CON_OFFSET 0x0c | |
26 | ||
27 | /* Register bitfields in the CON register */ | |
28 | #define MSDI_CON_POW_MASK BIT(11) | |
29 | #define MSDI_CON_CLKD_MASK (0x3f << 0) | |
30 | #define MSDI_CON_CLKD_SHIFT 0 | |
31 | ||
ad1b6662 TL |
32 | /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */ |
33 | #define MSDI_TARGET_RESET_CLKD 0x3ff | |
34 | ||
35 | /** | |
36 | * omap_msdi_reset - reset the MSDI IP block | |
37 | * @oh: struct omap_hwmod * | |
38 | * | |
39 | * The MSDI IP block on OMAP2420 has to have both the POW and CLKD | |
40 | * fields set inside its CON register for a reset to complete | |
41 | * successfully. This is not documented in the TRM. For CLKD, we use | |
42 | * the value that results in the lowest possible clock rate, to attempt | |
43 | * to avoid disturbing any cards. | |
44 | */ | |
45 | int omap_msdi_reset(struct omap_hwmod *oh) | |
46 | { | |
47 | u16 v = 0; | |
48 | int c = 0; | |
49 | ||
50 | /* Write to the SOFTRESET bit */ | |
51 | omap_hwmod_softreset(oh); | |
52 | ||
53 | /* Enable the MSDI core and internal clock */ | |
54 | v |= MSDI_CON_POW_MASK; | |
55 | v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT; | |
56 | omap_hwmod_write(v, oh, MSDI_CON_OFFSET); | |
57 | ||
58 | /* Poll on RESETDONE bit */ | |
59 | omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) | |
60 | & SYSS_RESETDONE_MASK), | |
61 | MAX_MODULE_SOFTRESET_WAIT, c); | |
62 | ||
63 | if (c == MAX_MODULE_SOFTRESET_WAIT) | |
3d0cb73e JP |
64 | pr_warn("%s: %s: softreset failed (waited %d usec)\n", |
65 | __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
ad1b6662 TL |
66 | else |
67 | pr_debug("%s: %s: softreset in %d usec\n", __func__, | |
68 | oh->name, c); | |
69 | ||
70 | /* Disable the MSDI internal clock */ | |
71 | v &= ~MSDI_CON_CLKD_MASK; | |
72 | omap_hwmod_write(v, oh, MSDI_CON_OFFSET); | |
73 | ||
74 | return 0; | |
75 | } |