[linux-2.6-block.git] / arch / arm / mach-omap2 / memory.c

/*
 * linux/arch/arm/mach-omap2/memory.c
 *
 * Memory timing related functions for OMAP24XX
 *
 * Copyright (C) 2005 Texas Instruments Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Copyright (C) 2005 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/common.h>
#include <mach/clock.h>
#include <mach/sram.h>

#include "prm.h"

#include "memory.h"
#include "sdrc.h"

void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;

static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

u32 omap2_memory_get_slow_dll_ctrl(void)
{
	return mem_timings.slow_dll_ctrl;
}

u32 omap2_memory_get_fast_dll_ctrl(void)
{
	return mem_timings.fast_dll_ctrl;
}

u32 omap2_memory_get_type(void)
{
	return mem_timings.m_type;
}

/*
 * Check the DLL lock state, and return tue if running in unlock mode.
 * This is needed to compensate for the shifted DLL value in unlock mode.
 */
u32 omap2_dll_force_needed(void)
{
	/* dlla and dllb are a set */
	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);

	if ((dll_state & (1 << 2)) == (1 << 2))
		return 1;
	else
		return 0;
}

/*
 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
 */
u32 omap2_reprogram_sdrc(u32 level, u32 force)
{
	u32 dll_ctrl, m_type;
	u32 prev = curr_perf_level;
	unsigned long flags;

	if ((curr_perf_level == level) && !force)
		return prev;

	if (level == CORE_CLK_SRC_DPLL) {
		dll_ctrl = omap2_memory_get_slow_dll_ctrl();
	} else if (level == CORE_CLK_SRC_DPLL_X2) {
		dll_ctrl = omap2_memory_get_fast_dll_ctrl();
	} else {
		return prev;
	}

	m_type = omap2_memory_get_type();

	local_irq_save(flags);
	__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	curr_perf_level = level;
	local_irq_restore(flags);

	return prev;
}

void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
	unsigned long dll_cnt;
	u32 fast_dll = 0;

	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */

	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	 * In the case of 2422, its ok to use CS1 instead of CS0.
	 */
	if (cpu_is_omap2422())
		mem_timings.base_cs = 1;
	else
		mem_timings.base_cs = 0;

	if (mem_timings.m_type != M_DDR)
		return;

	/* With DDR we need to determine the low frequency DLL value */
	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
		mem_timings.dll_mode = M_UNLOCK;
	else
		mem_timings.dll_mode = M_LOCK;

	if (mem_timings.base_cs == 0) {
		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
	} else {
		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
	}
	if (force_lock_to_unlock_mode) {
		fast_dll &= ~0xff00;
		fast_dll |= dll_cnt;		/* Current lock mode */
	}
	/* set fast timings with DLL filter disabled */
	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));

	/* No disruptions, DDR will be offline & C-ABI not followed */
	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
			    mem_timings.fast_dll_ctrl,
			    mem_timings.base_cs,
			    force_lock_to_unlock_mode);
	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */

	/* Turn status into unlock ctrl */
	mem_timings.slow_dll_ctrl |=
		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));

	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}

void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
{
	omap2_sdrc_base = omap2_globals->sdrc;
	omap2_sms_base = omap2_globals->sms;
}

/* turn on smart idle modes for SDRAM scheduler and controller */
void __init omap2_init_memory(void)
{
	u32 l;

	l = sms_read_reg(SMS_SYSCONFIG);
	l &= ~(0x3 << 3);
	l |= (0x2 << 3);
	sms_write_reg(l, SMS_SYSCONFIG);

	l = sdrc_read_reg(SDRC_SYSCONFIG);
	l &= ~(0x3 << 3);
	l |= (0x2 << 3);
	sdrc_write_reg(l, SDRC_SYSCONFIG);
}
Commit	Line	Data
b824efae TL	1	/*
	2	* linux/arch/arm/mach-omap2/memory.c
	3	*
	4	* Memory timing related functions for OMAP24XX
	5	*
	6	* Copyright (C) 2005 Texas Instruments Inc.
	7	* Richard Woodruff <r-woodruff2@ti.com>
	8	*
	9	* Copyright (C) 2005 Nokia Corporation
	10	* Tony Lindgren <tony@atomide.com>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
b824efae TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/list.h>
	21	#include <linux/errno.h>
	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
fced80c7	24	#include <linux/io.h>
b824efae	25
a09e64fb RK	26	#include <mach/common.h>
	27	#include <mach/clock.h>
	28	#include <mach/sram.h>
b824efae	29
44595982 PW	30	#include "prm.h"
44595982 PW	31
b824efae	32	#include "memory.h"
44595982	33	#include "sdrc.h"
b824efae	34
a58caad1 TL	35	void __iomem *omap2_sdrc_base;
a58caad1 TL	36	void __iomem *omap2_sms_base;
33c99075	37
b824efae	38	static struct memory_timings mem_timings;
44595982	39	static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
b824efae TL	40
	41	u32 omap2_memory_get_slow_dll_ctrl(void)
	42	{
	43	return mem_timings.slow_dll_ctrl;
	44	}
	45
	46	u32 omap2_memory_get_fast_dll_ctrl(void)
	47	{
	48	return mem_timings.fast_dll_ctrl;
	49	}
	50
	51	u32 omap2_memory_get_type(void)
	52	{
	53	return mem_timings.m_type;
	54	}
	55
6b8858a9 PW	56	/*
	57	* Check the DLL lock state, and return tue if running in unlock mode.
	58	* This is needed to compensate for the shifted DLL value in unlock mode.
	59	*/
	60	u32 omap2_dll_force_needed(void)
	61	{
	62	/* dlla and dllb are a set */
	63	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
	64
	65	if ((dll_state & (1 << 2)) == (1 << 2))
	66	return 1;
	67	else
	68	return 0;
	69	}
	70
	71	/*
	72	* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
	73	* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
	74	* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
	75	*/
	76	u32 omap2_reprogram_sdrc(u32 level, u32 force)
	77	{
	78	u32 dll_ctrl, m_type;
	79	u32 prev = curr_perf_level;
	80	unsigned long flags;
	81
	82	if ((curr_perf_level == level) && !force)
	83	return prev;
	84
	85	if (level == CORE_CLK_SRC_DPLL) {
	86	dll_ctrl = omap2_memory_get_slow_dll_ctrl();
	87	} else if (level == CORE_CLK_SRC_DPLL_X2) {
	88	dll_ctrl = omap2_memory_get_fast_dll_ctrl();
	89	} else {
	90	return prev;
	91	}
	92
	93	m_type = omap2_memory_get_type();
	94
	95	local_irq_save(flags);
	96	__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
	97	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
	98	curr_perf_level = level;
	99	local_irq_restore(flags);
	100
	101	return prev;
	102	}
	103
b824efae TL	104	void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
	105	{
	106	unsigned long dll_cnt;
	107	u32 fast_dll = 0;
	108
44595982	109	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
b824efae TL	110
	111	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	112	* In the case of 2422, its ok to use CS1 instead of CS0.
	113	*/
	114	if (cpu_is_omap2422())
	115	mem_timings.base_cs = 1;
	116	else
	117	mem_timings.base_cs = 0;
	118
	119	if (mem_timings.m_type != M_DDR)
	120	return;
	121
	122	/* With DDR we need to determine the low frequency DLL value */
	123	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
	124	mem_timings.dll_mode = M_UNLOCK;
	125	else
	126	mem_timings.dll_mode = M_LOCK;
	127
	128	if (mem_timings.base_cs == 0) {
44595982 PW	129	fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
44595982 PW	130	dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
b824efae	131	} else {
44595982 PW	132	fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
44595982 PW	133	dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
b824efae TL	134	}
	135	if (force_lock_to_unlock_mode) {
	136	fast_dll &= ~0xff00;
	137	fast_dll \|= dll_cnt; /* Current lock mode */
	138	}
	139	/* set fast timings with DLL filter disabled */
	140	mem_timings.fast_dll_ctrl = (fast_dll \| (3 << 8));
	141
	142	/* No disruptions, DDR will be offline & C-ABI not followed */
	143	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
	144	mem_timings.fast_dll_ctrl,
	145	mem_timings.base_cs,
	146	force_lock_to_unlock_mode);
	147	mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
	148
	149	/* Turn status into unlock ctrl */
	150	mem_timings.slow_dll_ctrl \|=
	151	((mem_timings.fast_dll_ctrl & 0xF) \| (1 << 2));
	152
	153	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	154	mem_timings.slow_dll_ctrl \|= ((1 << 1) \| (3 << 8));
	155	}
33c99075	156
a58caad1 TL	157	void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
	158	{
	159	omap2_sdrc_base = omap2_globals->sdrc;
	160	omap2_sms_base = omap2_globals->sms;
	161	}
	162
742c53e4	163	/* turn on smart idle modes for SDRAM scheduler and controller */
33c99075 JY	164	void __init omap2_init_memory(void)
	165	{
	166	u32 l;
	167
44595982	168	l = sms_read_reg(SMS_SYSCONFIG);
33c99075 JY	169	l &= ~(0x3 << 3);
33c99075 JY	170	l \|= (0x2 << 3);
44595982	171	sms_write_reg(l, SMS_SYSCONFIG);
33c99075	172
44595982	173	l = sdrc_read_reg(SDRC_SYSCONFIG);
33c99075 JY	174	l &= ~(0x3 << 3);
33c99075 JY	175	l \|= (0x2 << 3);
44595982	176	sdrc_write_reg(l, SDRC_SYSCONFIG);
33c99075	177	}