[linux-2.6-block.git] / arch / arm / mach-omap2 / mcbsp.c

/*
 * linux/arch/arm/mach-omap2/mcbsp.c
 *
 * Copyright (C) 2008 Instituto Nokia de Tecnologia
 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Multichannel mode not supported.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <mach/irqs.h>
#include <plat/dma.h>
#include <plat/cpu.h>
#include <plat/mcbsp.h>
#include <plat/omap_device.h>
#include <linux/pm_runtime.h>

#include "control.h"

/*
 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
 */
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/* McBSP1 internal signal muxing function for OMAP2/3 */
static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP2_MCBSP1_CLKR_MASK;
		else if (!strcmp(src, "clkx"))
			v |= OMAP2_MCBSP1_CLKR_MASK;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP2_MCBSP1_FSR_MASK;
		else if (!strcmp(src, "fsx"))
			v |= OMAP2_MCBSP1_FSR_MASK;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);

	return 0;
}

/* McBSP4 internal signal muxing function for OMAP4 */
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	/*
	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	 * mux) is used */
	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else if (!strcmp(src, "clkx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else if (!strcmp(src, "fsx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	return 0;
}

static int omap3_enable_st_clock(unsigned int id, bool enable)
{
	unsigned int w;

	/*
	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
	 * are enabled or sidetones start sounding ugly.
	 */
	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	if (enable)
		w &= ~(1 << (id - 2));
	else
		w |= 1 << (id - 2);
	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);

	return 0;
}

static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
{
	int id, count = 1;
	char *name = "omap-mcbsp";
	struct omap_hwmod *oh_device[2];
	struct omap_mcbsp_platform_data *pdata = NULL;
	struct platform_device *pdev;

	sscanf(oh->name, "mcbsp%d", &id);

	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for mcbsp\n", __func__);
		return -ENOMEM;
	}

	pdata->reg_step = 4;
	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
		pdata->reg_size = 2;
	} else {
		pdata->reg_size = 4;
		pdata->has_ccr = true;
	}

	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;

	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;

	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
		if (id == 2)
			/* The FIFO has 1024 + 256 locations */
			pdata->buffer_size = 0x500;
		else
			/* The FIFO has 128 locations */
			pdata->buffer_size = 0x80;
	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
		/* The FIFO has 128 locations for all instances */
		pdata->buffer_size = 0x80;
	}

	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
		pdata->has_wakeup = true;

	oh_device[0] = oh;

	if (oh->dev_attr) {
		oh_device[1] = omap_hwmod_lookup((
		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
		pdata->enable_st_clock = omap3_enable_st_clock;
		count++;
	}
	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
				sizeof(*pdata), NULL, 0, false);
	kfree(pdata);
	if (IS_ERR(pdev))  {
		pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
					name, oh->name);
		return PTR_ERR(pdev);
	}
	return 0;
}

static int __init omap2_mcbsp_init(void)
{
	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);

	return 0;
}
arch_initcall(omap2_mcbsp_init);
Commit	Line	Data
78673bc8 EV	1	/*
	2	* linux/arch/arm/mach-omap2/mcbsp.c
	3	*
	4	* Copyright (C) 2008 Instituto Nokia de Tecnologia
	5	* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Multichannel mode not supported.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
78673bc8	20
dd7667aa	21	#include <mach/irqs.h>
ce491cf8	22	#include <plat/dma.h>
ce491cf8 TL	23	#include <plat/cpu.h>
ce491cf8 TL	24	#include <plat/mcbsp.h>
64bcbd33	25	#include <plat/omap_device.h>
e95496d4	26	#include <linux/pm_runtime.h>
4814ced5 PW	27
	28	#include "control.h"
	29
1743d14f JN	30	/*
	31	* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
	32	* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
	33	*/
	34	#include "cm2xxx_3xxx.h"
	35	#include "cm-regbits-34xx.h"
	36
40c0764b	37	/* McBSP1 internal signal muxing function for OMAP2/3 */
7bc0c4ba JN	38	static int omap2_mcbsp1_mux_rx_clk(struct device dev, const char signal,
7bc0c4ba JN	39	const char *src)
cf4c87ab PW	40	{
	41	u32 v;
	42
	43	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
cf4c87ab	44
7bc0c4ba JN	45	if (!strcmp(signal, "clkr")) {
	46	if (!strcmp(src, "clkr"))
	47	v &= ~OMAP2_MCBSP1_CLKR_MASK;
	48	else if (!strcmp(src, "clkx"))
	49	v \|= OMAP2_MCBSP1_CLKR_MASK;
	50	else
	51	return -EINVAL;
	52	} else if (!strcmp(signal, "fsr")) {
	53	if (!strcmp(src, "fsr"))
	54	v &= ~OMAP2_MCBSP1_FSR_MASK;
	55	else if (!strcmp(src, "fsx"))
	56	v \|= OMAP2_MCBSP1_FSR_MASK;
	57	else
	58	return -EINVAL;
	59	} else {
	60	return -EINVAL;
	61	}
cf4c87ab	62
cf4c87ab	63	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
7bc0c4ba JN	64
7bc0c4ba JN	65	return 0;
cf4c87ab	66	}
cf4c87ab	67
40c0764b PU	68	/* McBSP4 internal signal muxing function for OMAP4 */
	69	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
	70	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
	71	static int omap4_mcbsp4_mux_rx_clk(struct device dev, const char signal,
	72	const char *src)
	73	{
	74	u32 v;
	75
	76	/*
	77	* In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	78	* mux) is used */
	79	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	80
	81	if (!strcmp(signal, "clkr")) {
	82	if (!strcmp(src, "clkr"))
	83	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	84	else if (!strcmp(src, "clkx"))
	85	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	86	else
	87	return -EINVAL;
	88	} else if (!strcmp(signal, "fsr")) {
	89	if (!strcmp(src, "fsr"))
	90	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	91	else if (!strcmp(src, "fsx"))
	92	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	93	else
	94	return -EINVAL;
	95	} else {
	96	return -EINVAL;
	97	}
	98
	99	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	100
	101	return 0;
	102	}
	103
1743d14f JN	104	static int omap3_enable_st_clock(unsigned int id, bool enable)
	105	{
	106	unsigned int w;
	107
	108	/*
	109	* Sidetone uses McBSP ICLK - which must not idle when sidetones
	110	* are enabled or sidetones start sounding ugly.
	111	*/
	112	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	113	if (enable)
	114	w &= ~(1 << (id - 2));
	115	else
	116	w \|= 1 << (id - 2);
	117	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
	118
	119	return 0;
	120	}
	121
9cf793f9	122	static int __init omap_init_mcbsp(struct omap_hwmod oh, void unused)
64bcbd33 KVA	123	{
	124	int id, count = 1;
	125	char *name = "omap-mcbsp";
	126	struct omap_hwmod *oh_device[2];
	127	struct omap_mcbsp_platform_data *pdata = NULL;
3528c58e	128	struct platform_device *pdev;
3cf32bba	129
64bcbd33	130	sscanf(oh->name, "mcbsp%d", &id);
78673bc8	131
64bcbd33 KVA	132	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	133	if (!pdata) {
	134	pr_err("%s: No memory for mcbsp\n", __func__);
	135	return -ENOMEM;
	136	}
3cf32bba	137
cdc71514	138	pdata->reg_step = 4;
88408230	139	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
cdc71514	140	pdata->reg_size = 2;
88408230	141	} else {
cdc71514	142	pdata->reg_size = 4;
88408230 JN	143	pdata->has_ccr = true;
88408230 JN	144	}
40c0764b PU	145
	146	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	147	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
0c8551e5	148	pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
9504ba64	149
40c0764b PU	150	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	151	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
	152	pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
	153
64bcbd33 KVA	154	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
	155	if (id == 2)
	156	/* The FIFO has 1024 + 256 locations */
	157	pdata->buffer_size = 0x500;
	158	else
	159	/* The FIFO has 128 locations */
	160	pdata->buffer_size = 0x80;
da76250e PU	161	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
	162	/* The FIFO has 128 locations for all instances */
	163	pdata->buffer_size = 0x80;
64bcbd33	164	}
3cf32bba	165
1a645884 JN	166	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
	167	pdata->has_wakeup = true;
	168
64bcbd33	169	oh_device[0] = oh;
78673bc8	170
64bcbd33 KVA	171	if (oh->dev_attr) {
	172	oh_device[1] = omap_hwmod_lookup((
	173	(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
1743d14f	174	pdata->enable_st_clock = omap3_enable_st_clock;
64bcbd33 KVA	175	count++;
64bcbd33 KVA	176	}
3528c58e	177	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
f718e2c0	178	sizeof(*pdata), NULL, 0, false);
64bcbd33	179	kfree(pdata);
3528c58e	180	if (IS_ERR(pdev)) {
25985edc	181	pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
64bcbd33	182	name, oh->name);
3528c58e	183	return PTR_ERR(pdev);
64bcbd33	184	}
64bcbd33 KVA	185	return 0;
64bcbd33 KVA	186	}
a5b92cc3	187
b4b58f58	188	static int __init omap2_mcbsp_init(void)
78673bc8	189	{
64bcbd33	190	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
b4b58f58	191
0210dc4e	192	return 0;
78673bc8 EV	193	}
78673bc8 EV	194	arch_initcall(omap2_mcbsp_init);