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78673bc8 EV |
1 | /* |
2 | * linux/arch/arm/mach-omap2/mcbsp.c | |
3 | * | |
4 | * Copyright (C) 2008 Instituto Nokia de Tecnologia | |
5 | * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Multichannel mode not supported. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/platform_device.h> | |
19 | ||
dd7667aa | 20 | #include <mach/irqs.h> |
a09e64fb RK |
21 | #include <mach/dma.h> |
22 | #include <mach/mux.h> | |
23 | #include <mach/cpu.h> | |
24 | #include <mach/mcbsp.h> | |
78673bc8 | 25 | |
78673bc8 EV |
26 | static void omap2_mcbsp2_mux_setup(void) |
27 | { | |
28 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); | |
29 | omap_cfg_reg(R14_24XX_MCBSP2_FSX); | |
30 | omap_cfg_reg(W15_24XX_MCBSP2_DR); | |
31 | omap_cfg_reg(V15_24XX_MCBSP2_DX); | |
32 | omap_cfg_reg(V14_24XX_GPIO117); | |
33 | /* | |
34 | * TODO: Need to add MUX settings for OMAP 2430 SDP | |
35 | */ | |
36 | } | |
37 | ||
38 | static void omap2_mcbsp_request(unsigned int id) | |
39 | { | |
40 | if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) | |
41 | omap2_mcbsp2_mux_setup(); | |
42 | } | |
43 | ||
78673bc8 EV |
44 | static struct omap_mcbsp_ops omap2_mcbsp_ops = { |
45 | .request = omap2_mcbsp_request, | |
78673bc8 EV |
46 | }; |
47 | ||
05228c35 JN |
48 | #ifdef CONFIG_ARCH_OMAP2420 |
49 | static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |
78673bc8 | 50 | { |
65846909 | 51 | .phys_base = OMAP24XX_MCBSP1_BASE, |
78673bc8 EV |
52 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, |
53 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | |
54 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | |
55 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | |
56 | .ops = &omap2_mcbsp_ops, | |
78673bc8 EV |
57 | }, |
58 | { | |
65846909 | 59 | .phys_base = OMAP24XX_MCBSP2_BASE, |
78673bc8 EV |
60 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
61 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | |
62 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | |
63 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | |
64 | .ops = &omap2_mcbsp_ops, | |
78673bc8 EV |
65 | }, |
66 | }; | |
05228c35 | 67 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
78673bc8 | 68 | #else |
05228c35 JN |
69 | #define omap2420_mcbsp_pdata NULL |
70 | #define OMAP2420_MCBSP_PDATA_SZ 0 | |
71 | #endif | |
72 | ||
73 | #ifdef CONFIG_ARCH_OMAP2430 | |
74 | static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |
75 | { | |
76 | .phys_base = OMAP24XX_MCBSP1_BASE, | |
77 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, | |
78 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | |
79 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | |
80 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | |
81 | .ops = &omap2_mcbsp_ops, | |
05228c35 JN |
82 | }, |
83 | { | |
84 | .phys_base = OMAP24XX_MCBSP2_BASE, | |
85 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, | |
86 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | |
87 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | |
88 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | |
89 | .ops = &omap2_mcbsp_ops, | |
05228c35 JN |
90 | }, |
91 | { | |
92 | .phys_base = OMAP2430_MCBSP3_BASE, | |
93 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, | |
94 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, | |
95 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | |
96 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | |
97 | .ops = &omap2_mcbsp_ops, | |
05228c35 JN |
98 | }, |
99 | { | |
100 | .phys_base = OMAP2430_MCBSP4_BASE, | |
101 | .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, | |
102 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, | |
103 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | |
104 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | |
105 | .ops = &omap2_mcbsp_ops, | |
05228c35 JN |
106 | }, |
107 | { | |
108 | .phys_base = OMAP2430_MCBSP5_BASE, | |
109 | .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, | |
110 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, | |
111 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | |
112 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | |
113 | .ops = &omap2_mcbsp_ops, | |
05228c35 JN |
114 | }, |
115 | }; | |
116 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | |
117 | #else | |
118 | #define omap2430_mcbsp_pdata NULL | |
119 | #define OMAP2430_MCBSP_PDATA_SZ 0 | |
78673bc8 EV |
120 | #endif |
121 | ||
122 | #ifdef CONFIG_ARCH_OMAP34XX | |
123 | static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |
124 | { | |
65846909 | 125 | .phys_base = OMAP34XX_MCBSP1_BASE, |
78673bc8 EV |
126 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, |
127 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, | |
128 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | |
129 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | |
130 | .ops = &omap2_mcbsp_ops, | |
78673bc8 EV |
131 | }, |
132 | { | |
65846909 | 133 | .phys_base = OMAP34XX_MCBSP2_BASE, |
78673bc8 EV |
134 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
135 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | |
136 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | |
137 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | |
138 | .ops = &omap2_mcbsp_ops, | |
78673bc8 | 139 | }, |
9c8e3a0f CS |
140 | { |
141 | .phys_base = OMAP34XX_MCBSP3_BASE, | |
142 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, | |
143 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, | |
144 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | |
145 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | |
146 | .ops = &omap2_mcbsp_ops, | |
9c8e3a0f CS |
147 | }, |
148 | { | |
149 | .phys_base = OMAP34XX_MCBSP4_BASE, | |
150 | .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, | |
151 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, | |
152 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | |
153 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | |
154 | .ops = &omap2_mcbsp_ops, | |
9c8e3a0f CS |
155 | }, |
156 | { | |
157 | .phys_base = OMAP34XX_MCBSP5_BASE, | |
158 | .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, | |
159 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, | |
160 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | |
161 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | |
162 | .ops = &omap2_mcbsp_ops, | |
9c8e3a0f | 163 | }, |
78673bc8 EV |
164 | }; |
165 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | |
166 | #else | |
167 | #define omap34xx_mcbsp_pdata NULL | |
168 | #define OMAP34XX_MCBSP_PDATA_SZ 0 | |
169 | #endif | |
170 | ||
b4b58f58 | 171 | static int __init omap2_mcbsp_init(void) |
78673bc8 | 172 | { |
05228c35 JN |
173 | if (cpu_is_omap2420()) |
174 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; | |
175 | if (cpu_is_omap2430()) | |
176 | omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; | |
b4b58f58 CS |
177 | if (cpu_is_omap34xx()) |
178 | omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; | |
179 | ||
180 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), | |
181 | GFP_KERNEL); | |
182 | if (!mcbsp_ptr) | |
183 | return -ENOMEM; | |
184 | ||
05228c35 JN |
185 | if (cpu_is_omap2420()) |
186 | omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, | |
187 | OMAP2420_MCBSP_PDATA_SZ); | |
188 | if (cpu_is_omap2430()) | |
189 | omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, | |
190 | OMAP2430_MCBSP_PDATA_SZ); | |
9c8e3a0f CS |
191 | if (cpu_is_omap34xx()) |
192 | omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, | |
193 | OMAP34XX_MCBSP_PDATA_SZ); | |
78673bc8 | 194 | |
78673bc8 EV |
195 | return omap_mcbsp_init(); |
196 | } | |
197 | arch_initcall(omap2_mcbsp_init); |