[linux-2.6-block.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/mailbox.h>
#include <mach/irqs.h>

#define MAILBOX_REVISION		0x000
#define MAILBOX_SYSCONFIG		0x010
#define MAILBOX_SYSSTATUS		0x014
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define MAILBOX_IRQ_NEWMSG(u)		(1 << (2 * (u)))
#define MAILBOX_IRQ_NOTFULL(u)		(1 << (2 * (u) + 1))

/* SYSCONFIG: register bit definition */
#define AUTOIDLE	(1 << 0)
#define SOFTRESET	(1 << 1)
#define SMARTIDLE	(2 << 3)

/* SYSSTATUS: register bit definition */
#define RESETDONE	(1 << 0)

#define MBOX_REG_SIZE			0x120
#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[MBOX_NR_REGS];
};

static struct clk *mbox_ick_handle;

static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
				  omap_mbox_type_t irq);

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;
	unsigned long timeout;

	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	if (IS_ERR(mbox_ick_handle)) {
		pr_err("Can't get mailboxes_ick\n");
		return -ENODEV;
	}
	clk_enable(mbox_ick_handle);

	mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
	timeout = jiffies + msecs_to_jiffies(20);
	do {
		l = mbox_read_reg(MAILBOX_SYSSTATUS);
		if (l & RESETDONE)
			break;
	} while (time_after(jiffies, timeout));

	if (!(l & RESETDONE)) {
		pr_err("Can't take mmu out of reset\n");
		return -ENODEV;
	}

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	l = SMARTIDLE | AUTOIDLE;
	mbox_write_reg(l, MAILBOX_SYSCONFIG);

	omap2_mbox_enable_irq(mbox, IRQ_RX);

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	clk_disable(mbox_ick_handle);
	clk_put(mbox_ick_handle);
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return (mbox_read_reg(fifo->fifo_stat));
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l &= ~bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;

	for (i = 0; i < MBOX_NR_REGS; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;

	for (i = 0; i < MBOX_NR_REGS; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};
EXPORT_SYMBOL(mbox_dsp_info);

#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};
#endif

static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret;

	/* MBOX base */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res)) {
		dev_err(&pdev->dev, "invalid mem resource\n");
		return -ENODEV;
	}
	mbox_base = ioremap(res->start, res->end - res->start);
	if (!mbox_base)
		return -ENOMEM;

	/* DSP or IVA2 IRQ */
	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "invalid irq resource\n");
		goto err_dsp;
	}
	mbox_dsp_info.irq = ret;

	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
	if (ret)
		goto err_dsp;

#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
	if (cpu_is_omap2420()) {
		/* IVA IRQ */
		res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
		if (unlikely(!res)) {
			dev_err(&pdev->dev, "invalid irq resource\n");
			ret = -ENODEV;
			goto err_iva1;
		}
		mbox_iva_info.irq = res->start;
		ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
		if (ret)
			goto err_iva1;
	}
#endif
	return 0;

err_iva1:
	omap_mbox_unregister(&mbox_dsp_info);
err_dsp:
	iounmap(mbox_base);
	return ret;
}

static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
#if defined(CONFIG_ARCH_OMAP2420)
	omap_mbox_unregister(&mbox_iva_info);
#endif
	omap_mbox_unregister(&mbox_dsp_info);
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = __devexit_p(omap2_mbox_remove),
	.driver = {
		.name = "omap2-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/clk.h>
	15	#include <linux/err.h>
	16	#include <linux/platform_device.h>
fced80c7	17	#include <linux/io.h>
a09e64fb RK	18	#include <mach/mailbox.h>
a09e64fb RK	19	#include <mach/irqs.h>
340a614a	20
733ecc5c HD	21	#define MAILBOX_REVISION 0x000
	22	#define MAILBOX_SYSCONFIG 0x010
	23	#define MAILBOX_SYSSTATUS 0x014
	24	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	25	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	26	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	27	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	28	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	29
733ecc5c HD	30	#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
733ecc5c HD	31	#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
340a614a	32
1ffe627d HD	33	/* SYSCONFIG: register bit definition */
	34	#define AUTOIDLE (1 << 0)
	35	#define SOFTRESET (1 << 1)
	36	#define SMARTIDLE (2 << 3)
	37
	38	/* SYSSTATUS: register bit definition */
	39	#define RESETDONE (1 << 0)
	40
c75ee752 HD	41	#define MBOX_REG_SIZE 0x120
	42	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
	43
6c20a683	44	static void __iomem *mbox_base;
340a614a HD	45
	46	struct omap_mbox2_fifo {
	47	unsigned long msg;
	48	unsigned long fifo_stat;
	49	unsigned long msg_stat;
	50	};
	51
	52	struct omap_mbox2_priv {
	53	struct omap_mbox2_fifo tx_fifo;
	54	struct omap_mbox2_fifo rx_fifo;
	55	unsigned long irqenable;
	56	unsigned long irqstatus;
	57	u32 newmsg_bit;
	58	u32 notfull_bit;
c75ee752	59	u32 ctx[MBOX_NR_REGS];
340a614a HD	60	};
	61
	62	static struct clk *mbox_ick_handle;
	63
bfbdcf8a HD	64	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
	65	omap_mbox_type_t irq);
	66
6c20a683	67	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	68	{
6c20a683	69	return __raw_readl(mbox_base + ofs);
340a614a HD	70	}
340a614a HD	71
6c20a683	72	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	73	{
6c20a683	74	__raw_writel(val, mbox_base + ofs);
340a614a HD	75	}
	76
	77	/* Mailbox H/W preparations */
bfbdcf8a	78	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	79	{
1ffe627d HD	80	u32 l;
1ffe627d HD	81	unsigned long timeout;
340a614a HD	82
	83	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	84	if (IS_ERR(mbox_ick_handle)) {
1ffe627d	85	pr_err("Can't get mailboxes_ick\n");
340a614a HD	86	return -ENODEV;
	87	}
	88	clk_enable(mbox_ick_handle);
	89
1ffe627d HD	90	mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
	91	timeout = jiffies + msecs_to_jiffies(20);
	92	do {
	93	l = mbox_read_reg(MAILBOX_SYSSTATUS);
	94	if (l & RESETDONE)
	95	break;
	96	} while (time_after(jiffies, timeout));
	97
	98	if (!(l & RESETDONE)) {
	99	pr_err("Can't take mmu out of reset\n");
	100	return -ENODEV;
	101	}
	102
94fc58c6 HD	103	l = mbox_read_reg(MAILBOX_REVISION);
	104	pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
	105
1ffe627d	106	l = SMARTIDLE \| AUTOIDLE;
340a614a HD	107	mbox_write_reg(l, MAILBOX_SYSCONFIG);
340a614a HD	108
bfbdcf8a HD	109	omap2_mbox_enable_irq(mbox, IRQ_RX);
bfbdcf8a HD	110
340a614a HD	111	return 0;
	112	}
	113
bfbdcf8a	114	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a HD	115	{
	116	clk_disable(mbox_ick_handle);
	117	clk_put(mbox_ick_handle);
	118	}
	119
	120	/* Mailbox FIFO handle functions */
bfbdcf8a	121	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	122	{
	123	struct omap_mbox2_fifo *fifo =
	124	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	125	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	126	}
	127
bfbdcf8a	128	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	129	{
	130	struct omap_mbox2_fifo *fifo =
	131	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	132	mbox_write_reg(msg, fifo->msg);
	133	}
	134
bfbdcf8a	135	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	136	{
	137	struct omap_mbox2_fifo *fifo =
	138	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	139	return (mbox_read_reg(fifo->msg_stat) == 0);
	140	}
	141
bfbdcf8a	142	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	143	{
	144	struct omap_mbox2_fifo *fifo =
	145	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	146	return (mbox_read_reg(fifo->fifo_stat));
	147	}
	148
	149	/* Mailbox IRQ handle functions */
bfbdcf8a	150	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
340a614a HD	151	omap_mbox_type_t irq)
	152	{
	153	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	154	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	155
	156	l = mbox_read_reg(p->irqenable);
	157	l \|= bit;
	158	mbox_write_reg(l, p->irqenable);
	159	}
	160
bfbdcf8a	161	static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
340a614a HD	162	omap_mbox_type_t irq)
	163	{
	164	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	165	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	166
	167	l = mbox_read_reg(p->irqenable);
	168	l &= ~bit;
	169	mbox_write_reg(l, p->irqenable);
	170	}
	171
bfbdcf8a	172	static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
340a614a HD	173	omap_mbox_type_t irq)
	174	{
	175	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	176	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	177
	178	mbox_write_reg(bit, p->irqstatus);
	179	}
	180
bfbdcf8a	181	static int omap2_mbox_is_irq(struct omap_mbox *mbox,
340a614a HD	182	omap_mbox_type_t irq)
	183	{
	184	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	185	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	186	u32 enable = mbox_read_reg(p->irqenable);
	187	u32 status = mbox_read_reg(p->irqstatus);
	188
	189	return (enable & status & bit);
	190	}
	191
c75ee752 HD	192	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	193	{
	194	int i;
	195	struct omap_mbox2_priv *p = mbox->priv;
	196
	197	for (i = 0; i < MBOX_NR_REGS; i++) {
	198	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	199
	200	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	201	i, p->ctx[i]);
	202	}
	203	}
	204
	205	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	206	{
	207	int i;
	208	struct omap_mbox2_priv *p = mbox->priv;
	209
	210	for (i = 0; i < MBOX_NR_REGS; i++) {
	211	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	212
	213	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	214	i, p->ctx[i]);
	215	}
	216	}
	217
340a614a HD	218	static struct omap_mbox_ops omap2_mbox_ops = {
	219	.type = OMAP_MBOX_TYPE2,
	220	.startup = omap2_mbox_startup,
	221	.shutdown = omap2_mbox_shutdown,
	222	.fifo_read = omap2_mbox_fifo_read,
	223	.fifo_write = omap2_mbox_fifo_write,
	224	.fifo_empty = omap2_mbox_fifo_empty,
	225	.fifo_full = omap2_mbox_fifo_full,
	226	.enable_irq = omap2_mbox_enable_irq,
	227	.disable_irq = omap2_mbox_disable_irq,
	228	.ack_irq = omap2_mbox_ack_irq,
	229	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	230	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	231	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	232	};
	233
	234	/*
	235	* MAILBOX 0: ARM -> DSP,
	236	* MAILBOX 1: ARM <- DSP.
	237	* MAILBOX 2: ARM -> IVA,
	238	* MAILBOX 3: ARM <- IVA.
	239	*/
	240
	241	/* FIXME: the following structs should be filled automatically by the user id */
	242
	243	/* DSP */
	244	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	245	.tx_fifo = {
733ecc5c HD	246	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	247	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	248	},
340a614a HD	249	.rx_fifo = {
733ecc5c HD	250	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	251	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	252	},
733ecc5c HD	253	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	254	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	255	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	256	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	257	};
	258
	259	struct omap_mbox mbox_dsp_info = {
	260	.name = "dsp",
	261	.ops = &omap2_mbox_ops,
	262	.priv = &omap2_mbox_dsp_priv,
	263	};
	264	EXPORT_SYMBOL(mbox_dsp_info);
	265
6c20a683	266	#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
340a614a HD	267	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
340a614a HD	268	.tx_fifo = {
733ecc5c HD	269	.msg = MAILBOX_MESSAGE(2),
733ecc5c HD	270	.fifo_stat = MAILBOX_FIFOSTATUS(2),
340a614a HD	271	},
340a614a HD	272	.rx_fifo = {
733ecc5c HD	273	.msg = MAILBOX_MESSAGE(3),
733ecc5c HD	274	.msg_stat = MAILBOX_MSGSTATUS(3),
340a614a	275	},
733ecc5c HD	276	.irqenable = MAILBOX_IRQENABLE(3),
733ecc5c HD	277	.irqstatus = MAILBOX_IRQSTATUS(3),
340a614a HD	278	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	279	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	280	};
	281
	282	static struct omap_mbox mbox_iva_info = {
	283	.name = "iva",
	284	.ops = &omap2_mbox_ops,
	285	.priv = &omap2_mbox_iva_priv,
	286	};
6c20a683	287	#endif
340a614a	288
da8cfe03	289	static int __devinit omap2_mbox_probe(struct platform_device *pdev)
340a614a HD	290	{
340a614a HD	291	struct resource *res;
6c20a683	292	int ret;
340a614a HD	293
	294	/* MBOX base */
	295	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	296	if (unlikely(!res)) {
	297	dev_err(&pdev->dev, "invalid mem resource\n");
	298	return -ENODEV;
	299	}
6c20a683 HD	300	mbox_base = ioremap(res->start, res->end - res->start);
	301	if (!mbox_base)
	302	return -ENOMEM;
340a614a	303
6c20a683	304	/* DSP or IVA2 IRQ */
091a58af RK	305	ret = platform_get_irq(pdev, 0);
091a58af RK	306	if (ret < 0) {
340a614a	307	dev_err(&pdev->dev, "invalid irq resource\n");
6c20a683	308	goto err_dsp;
340a614a	309	}
091a58af	310	mbox_dsp_info.irq = ret;
340a614a	311
da8cfe03	312	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
6c20a683 HD	313	if (ret)
	314	goto err_dsp;
	315
	316	#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
	317	if (cpu_is_omap2420()) {
	318	/* IVA IRQ */
	319	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
	320	if (unlikely(!res)) {
	321	dev_err(&pdev->dev, "invalid irq resource\n");
	322	ret = -ENODEV;
	323	goto err_iva1;
	324	}
	325	mbox_iva_info.irq = res->start;
da8cfe03	326	ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
6c20a683 HD	327	if (ret)
6c20a683 HD	328	goto err_iva1;
340a614a	329	}
6c20a683 HD	330	#endif
6c20a683 HD	331	return 0;
340a614a	332
6c20a683 HD	333	err_iva1:
	334	omap_mbox_unregister(&mbox_dsp_info);
	335	err_dsp:
	336	iounmap(mbox_base);
340a614a HD	337	return ret;
	338	}
	339
da8cfe03	340	static int __devexit omap2_mbox_remove(struct platform_device *pdev)
340a614a	341	{
6c20a683 HD	342	#if defined(CONFIG_ARCH_OMAP2420)
	343	omap_mbox_unregister(&mbox_iva_info);
	344	#endif
340a614a	345	omap_mbox_unregister(&mbox_dsp_info);
6c20a683	346	iounmap(mbox_base);
340a614a HD	347	return 0;
	348	}
	349
	350	static struct platform_driver omap2_mbox_driver = {
	351	.probe = omap2_mbox_probe,
da8cfe03	352	.remove = __devexit_p(omap2_mbox_remove),
340a614a	353	.driver = {
da8cfe03	354	.name = "omap2-mailbox",
340a614a HD	355	},
	356	};
	357
	358	static int __init omap2_mbox_init(void)
	359	{
	360	return platform_driver_register(&omap2_mbox_driver);
	361	}
	362
	363	static void __exit omap2_mbox_exit(void)
	364	{
	365	platform_driver_unregister(&omap2_mbox_driver);
	366	}
	367
	368	module_init(omap2_mbox_init);
	369	module_exit(omap2_mbox_exit);
	370
733ecc5c HD	371	MODULE_LICENSE("GPL v2");
	372	MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
	373	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
da8cfe03	374	MODULE_ALIAS("platform:omap2-mailbox");