Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/irq.c |
1dbae815 TL |
3 | * |
4 | * Interrupt handler for OMAP2 boards. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
52fa2120 | 14 | #include <linux/module.h> |
1dbae815 | 15 | #include <linux/init.h> |
1dbae815 | 16 | #include <linux/interrupt.h> |
2e7509e5 | 17 | #include <linux/io.h> |
ee0839c2 | 18 | |
2db14997 | 19 | #include <asm/exception.h> |
1dbae815 | 20 | #include <asm/mach/irq.h> |
52fa2120 BC |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
c4082d49 | 24 | #include <linux/of_irq.h> |
1dbae815 | 25 | |
dbc04161 | 26 | #include "soc.h" |
ee0839c2 | 27 | #include "iomap.h" |
e2ed89fc | 28 | #include "common.h" |
2e7509e5 PW |
29 | |
30 | /* selected INTC register offsets */ | |
31 | ||
32 | #define INTC_REVISION 0x0000 | |
33 | #define INTC_SYSCONFIG 0x0010 | |
34 | #define INTC_SYSSTATUS 0x0014 | |
6ccc4c0d | 35 | #define INTC_SIR 0x0040 |
2e7509e5 | 36 | #define INTC_CONTROL 0x0048 |
0addd61b RN |
37 | #define INTC_PROTECTION 0x004C |
38 | #define INTC_IDLE 0x0050 | |
39 | #define INTC_THRESHOLD 0x0068 | |
40 | #define INTC_MIR0 0x0084 | |
2e7509e5 PW |
41 | #define INTC_MIR_CLEAR0 0x0088 |
42 | #define INTC_MIR_SET0 0x008c | |
43 | #define INTC_PENDING_IRQ0 0x0098 | |
33c7c7b7 | 44 | #define INTC_ILR0 0x0100 |
1dbae815 | 45 | |
2db14997 MZ |
46 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) |
47 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | |
48 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ | |
49 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ | |
a88ab430 | 50 | #define INTCPS_NR_ILR_REGS 128 |
3003ce3e | 51 | #define INTCPS_NR_MIR_REGS 3 |
2db14997 | 52 | |
1dbae815 TL |
53 | /* |
54 | * OMAP2 has a number of different interrupt controllers, each interrupt | |
55 | * controller is identified as its own "bank". Register definitions are | |
56 | * fairly consistent for each bank, but not all registers are implemented | |
57 | * for each bank.. when in doubt, consult the TRM. | |
58 | */ | |
1dbae815 | 59 | |
52fa2120 | 60 | static struct irq_domain *domain; |
176da6c7 | 61 | static void __iomem *omap_irq_base; |
421b090c | 62 | static int omap_nr_irqs = 96; |
52fa2120 | 63 | |
0addd61b RN |
64 | /* Structure to save interrupt controller context */ |
65 | struct omap3_intc_regs { | |
66 | u32 sysconfig; | |
67 | u32 protection; | |
68 | u32 idle; | |
69 | u32 threshold; | |
a88ab430 | 70 | u32 ilr[INTCPS_NR_ILR_REGS]; |
0addd61b RN |
71 | u32 mir[INTCPS_NR_MIR_REGS]; |
72 | }; | |
73 | ||
2e7509e5 | 74 | /* INTC bank register get/set */ |
71be00c9 | 75 | static void intc_writel(u32 reg, u32 val) |
2e7509e5 | 76 | { |
71be00c9 | 77 | writel_relaxed(val, omap_irq_base + reg); |
2e7509e5 PW |
78 | } |
79 | ||
71be00c9 | 80 | static u32 intc_readl(u32 reg) |
2e7509e5 | 81 | { |
71be00c9 | 82 | return readl_relaxed(omap_irq_base + reg); |
2e7509e5 PW |
83 | } |
84 | ||
1dbae815 | 85 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
df303477 | 86 | static void omap_ack_irq(struct irq_data *d) |
1dbae815 | 87 | { |
71be00c9 | 88 | intc_writel(INTC_CONTROL, 0x1); |
1dbae815 TL |
89 | } |
90 | ||
df303477 | 91 | static void omap_mask_ack_irq(struct irq_data *d) |
1dbae815 | 92 | { |
667a11fa | 93 | irq_gc_mask_disable_reg(d); |
df303477 | 94 | omap_ack_irq(d); |
1dbae815 TL |
95 | } |
96 | ||
a88ab430 | 97 | static void __init omap_irq_soft_reset(void) |
1dbae815 TL |
98 | { |
99 | unsigned long tmp; | |
100 | ||
71be00c9 | 101 | tmp = intc_readl(INTC_REVISION) & 0xff; |
a88ab430 | 102 | |
7852ec05 | 103 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
a88ab430 | 104 | omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); |
1dbae815 | 105 | |
71be00c9 | 106 | tmp = intc_readl(INTC_SYSCONFIG); |
1dbae815 | 107 | tmp |= 1 << 1; /* soft reset */ |
71be00c9 | 108 | intc_writel(INTC_SYSCONFIG, tmp); |
1dbae815 | 109 | |
71be00c9 | 110 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
1dbae815 | 111 | /* Wait for reset to complete */; |
375e12ab JY |
112 | |
113 | /* Enable autoidle */ | |
71be00c9 | 114 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
1dbae815 TL |
115 | } |
116 | ||
94434535 JH |
117 | int omap_irq_pending(void) |
118 | { | |
a88ab430 | 119 | int irq; |
94434535 | 120 | |
a88ab430 FB |
121 | for (irq = 0; irq < omap_nr_irqs; irq += 32) |
122 | if (intc_readl(INTC_PENDING_IRQ0 + | |
123 | ((irq >> 5) << 5))) | |
124 | return 1; | |
94434535 JH |
125 | return 0; |
126 | } | |
127 | ||
667a11fa TL |
128 | static __init void |
129 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |
130 | { | |
131 | struct irq_chip_generic *gc; | |
132 | struct irq_chip_type *ct; | |
133 | ||
134 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, | |
135 | handle_level_irq); | |
136 | ct = gc->chip_types; | |
137 | ct->chip.irq_ack = omap_mask_ack_irq; | |
138 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
139 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
e3c83c2d | 140 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
667a11fa | 141 | |
667a11fa TL |
142 | ct->regs.enable = INTC_MIR_CLEAR0; |
143 | ct->regs.disable = INTC_MIR_SET0; | |
144 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
145 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
146 | } | |
147 | ||
52fa2120 BC |
148 | static void __init omap_init_irq(u32 base, int nr_irqs, |
149 | struct device_node *node) | |
1dbae815 | 150 | { |
a88ab430 | 151 | int j, irq_base; |
1dbae815 | 152 | |
741e3a89 TL |
153 | omap_irq_base = ioremap(base, SZ_4K); |
154 | if (WARN_ON(!omap_irq_base)) | |
155 | return; | |
156 | ||
421b090c FB |
157 | omap_nr_irqs = nr_irqs; |
158 | ||
52fa2120 BC |
159 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
160 | if (irq_base < 0) { | |
161 | pr_warn("Couldn't allocate IRQ numbers\n"); | |
162 | irq_base = 0; | |
163 | } | |
164 | ||
165 | domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | |
a88ab430 | 166 | &irq_domain_simple_ops, NULL); |
1dbae815 | 167 | |
a88ab430 | 168 | omap_irq_soft_reset(); |
667a11fa | 169 | |
a88ab430 FB |
170 | for (j = 0; j < omap_nr_irqs; j += 32) |
171 | omap_alloc_gc(omap_irq_base + j, j + irq_base, 32); | |
1dbae815 TL |
172 | } |
173 | ||
741e3a89 TL |
174 | void __init omap2_init_irq(void) |
175 | { | |
52fa2120 | 176 | omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); |
741e3a89 TL |
177 | } |
178 | ||
179 | void __init omap3_init_irq(void) | |
180 | { | |
52fa2120 | 181 | omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); |
741e3a89 TL |
182 | } |
183 | ||
a920360f | 184 | void __init ti81xx_init_irq(void) |
741e3a89 | 185 | { |
52fa2120 | 186 | omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); |
741e3a89 TL |
187 | } |
188 | ||
2db14997 MZ |
189 | static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) |
190 | { | |
191 | u32 irqnr; | |
698b4853 | 192 | int handled_irq = 0; |
2db14997 MZ |
193 | |
194 | do { | |
195 | irqnr = readl_relaxed(base_addr + 0x98); | |
196 | if (irqnr) | |
197 | goto out; | |
198 | ||
199 | irqnr = readl_relaxed(base_addr + 0xb8); | |
200 | if (irqnr) | |
201 | goto out; | |
202 | ||
203 | irqnr = readl_relaxed(base_addr + 0xd8); | |
0bebda68 | 204 | #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX) |
2db14997 MZ |
205 | if (irqnr) |
206 | goto out; | |
207 | irqnr = readl_relaxed(base_addr + 0xf8); | |
208 | #endif | |
209 | ||
210 | out: | |
211 | if (!irqnr) | |
212 | break; | |
213 | ||
214 | irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); | |
215 | irqnr &= ACTIVEIRQ_MASK; | |
216 | ||
52fa2120 BC |
217 | if (irqnr) { |
218 | irqnr = irq_find_mapping(domain, irqnr); | |
2db14997 | 219 | handle_IRQ(irqnr, regs); |
698b4853 | 220 | handled_irq = 1; |
52fa2120 | 221 | } |
2db14997 | 222 | } while (irqnr); |
698b4853 SS |
223 | |
224 | /* If an irq is masked or deasserted while active, we will | |
225 | * keep ending up here with no irq handled. So remove it from | |
226 | * the INTC with an ack.*/ | |
227 | if (!handled_irq) | |
228 | omap_ack_irq(NULL); | |
2db14997 MZ |
229 | } |
230 | ||
231 | asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) | |
232 | { | |
233 | void __iomem *base_addr = OMAP2_IRQ_BASE; | |
234 | omap_intc_handle_irq(base_addr, regs); | |
235 | } | |
236 | ||
c4082d49 | 237 | int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
238 | struct device_node *parent) |
239 | { | |
240 | struct resource res; | |
b56f2cb7 | 241 | u32 nr_irq = 96; |
52fa2120 BC |
242 | |
243 | if (WARN_ON(!node)) | |
244 | return -ENODEV; | |
245 | ||
246 | if (of_address_to_resource(node, 0, &res)) { | |
247 | WARN(1, "unable to get intc registers\n"); | |
248 | return -EINVAL; | |
249 | } | |
250 | ||
b56f2cb7 V |
251 | if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) |
252 | pr_warn("unable to get intc-size, default to %d\n", nr_irq); | |
52fa2120 | 253 | |
b56f2cb7 | 254 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
52fa2120 BC |
255 | |
256 | return 0; | |
257 | } | |
258 | ||
31957609 | 259 | static const struct of_device_id irq_match[] __initconst = { |
c4082d49 S |
260 | { .compatible = "ti,omap2-intc", .data = intc_of_init, }, |
261 | { } | |
262 | }; | |
263 | ||
264 | void __init omap_intc_of_init(void) | |
265 | { | |
266 | of_irq_init(irq_match); | |
267 | } | |
268 | ||
08f30989 | 269 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
a88ab430 | 270 | static struct omap3_intc_regs intc_context; |
ee23b93d | 271 | |
0addd61b RN |
272 | void omap_intc_save_context(void) |
273 | { | |
a88ab430 FB |
274 | int i; |
275 | ||
276 | intc_context.sysconfig = | |
277 | intc_readl(INTC_SYSCONFIG); | |
278 | intc_context.protection = | |
279 | intc_readl(INTC_PROTECTION); | |
280 | intc_context.idle = | |
281 | intc_readl(INTC_IDLE); | |
282 | intc_context.threshold = | |
283 | intc_readl(INTC_THRESHOLD); | |
284 | ||
285 | for (i = 0; i < omap_nr_irqs; i++) | |
286 | intc_context.ilr[i] = | |
287 | intc_readl((INTC_ILR0 + 0x4 * i)); | |
288 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
289 | intc_context.mir[i] = | |
290 | intc_readl(INTC_MIR0 + (0x20 * i)); | |
0addd61b RN |
291 | } |
292 | ||
293 | void omap_intc_restore_context(void) | |
294 | { | |
a88ab430 FB |
295 | int i; |
296 | ||
297 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | |
298 | intc_writel(INTC_PROTECTION, intc_context.protection); | |
299 | intc_writel(INTC_IDLE, intc_context.idle); | |
300 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | |
301 | ||
302 | for (i = 0; i < omap_nr_irqs; i++) | |
303 | intc_writel(INTC_ILR0 + 0x4 * i, | |
304 | intc_context.ilr[i]); | |
305 | ||
306 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
307 | intc_writel(INTC_MIR0 + 0x20 * i, | |
308 | intc_context.mir[i]); | |
0addd61b RN |
309 | /* MIRs are saved and restore with other PRCM registers */ |
310 | } | |
2bbe3af3 TK |
311 | |
312 | void omap3_intc_suspend(void) | |
313 | { | |
314 | /* A pending interrupt would prevent OMAP from entering suspend */ | |
a7022d60 | 315 | omap_ack_irq(NULL); |
2bbe3af3 | 316 | } |
f18cc2ff TK |
317 | |
318 | void omap3_intc_prepare_idle(void) | |
319 | { | |
447b8da5 JP |
320 | /* |
321 | * Disable autoidle as it can stall interrupt controller, | |
322 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | |
323 | */ | |
71be00c9 | 324 | intc_writel(INTC_SYSCONFIG, 0); |
f18cc2ff TK |
325 | } |
326 | ||
327 | void omap3_intc_resume_idle(void) | |
328 | { | |
329 | /* Re-enable autoidle */ | |
71be00c9 | 330 | intc_writel(INTC_SYSCONFIG, 1); |
f18cc2ff | 331 | } |
2db14997 MZ |
332 | |
333 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) | |
334 | { | |
335 | void __iomem *base_addr = OMAP3_IRQ_BASE; | |
336 | omap_intc_handle_irq(base_addr, regs); | |
337 | } | |
0addd61b | 338 | #endif /* CONFIG_ARCH_OMAP3 */ |