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2bcb5733 HD |
1 | /* |
2 | * omap iommu: omap2/3 architecture specific functions | |
3 | * | |
4 | * Copyright (C) 2008-2009 Nokia Corporation | |
5 | * | |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/jiffies.h> | |
17 | #include <linux/module.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
2bcb5733 HD |
19 | #include <linux/stringify.h> |
20 | ||
ce491cf8 | 21 | #include <plat/iommu.h> |
2bcb5733 HD |
22 | |
23 | /* | |
24 | * omap2 architecture specific register bit definitions | |
25 | */ | |
26 | #define IOMMU_ARCH_VERSION 0x00000011 | |
27 | ||
28 | /* SYSCONF */ | |
29 | #define MMU_SYS_IDLE_SHIFT 3 | |
30 | #define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) | |
31 | #define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) | |
32 | #define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) | |
33 | #define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) | |
34 | ||
35 | #define MMU_SYS_SOFTRESET (1 << 1) | |
36 | #define MMU_SYS_AUTOIDLE 1 | |
37 | ||
38 | /* SYSSTATUS */ | |
39 | #define MMU_SYS_RESETDONE 1 | |
40 | ||
41 | /* IRQSTATUS & IRQENABLE */ | |
42 | #define MMU_IRQ_MULTIHITFAULT (1 << 4) | |
43 | #define MMU_IRQ_TABLEWALKFAULT (1 << 3) | |
44 | #define MMU_IRQ_EMUMISS (1 << 2) | |
45 | #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) | |
46 | #define MMU_IRQ_TLBMISS (1 << 0) | |
47 | #define MMU_IRQ_MASK \ | |
48 | (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ | |
49 | MMU_IRQ_TRANSLATIONFAULT) | |
50 | ||
51 | /* MMU_CNTL */ | |
52 | #define MMU_CNTL_SHIFT 1 | |
53 | #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) | |
54 | #define MMU_CNTL_EML_TLB (1 << 3) | |
55 | #define MMU_CNTL_TWL_EN (1 << 2) | |
56 | #define MMU_CNTL_MMU_EN (1 << 1) | |
57 | ||
58 | #define get_cam_va_mask(pgsz) \ | |
59 | (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ | |
60 | ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ | |
61 | ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ | |
62 | ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) | |
63 | ||
64 | static int omap2_iommu_enable(struct iommu *obj) | |
65 | { | |
66 | u32 l, pa; | |
67 | unsigned long timeout; | |
68 | ||
69 | if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | |
70 | return -EINVAL; | |
71 | ||
72 | pa = virt_to_phys(obj->iopgd); | |
73 | if (!IS_ALIGNED(pa, SZ_16K)) | |
74 | return -EINVAL; | |
75 | ||
76 | iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); | |
77 | ||
78 | timeout = jiffies + msecs_to_jiffies(20); | |
79 | do { | |
80 | l = iommu_read_reg(obj, MMU_SYSSTATUS); | |
81 | if (l & MMU_SYS_RESETDONE) | |
82 | break; | |
055c49d2 | 83 | } while (!time_after(jiffies, timeout)); |
2bcb5733 HD |
84 | |
85 | if (!(l & MMU_SYS_RESETDONE)) { | |
86 | dev_err(obj->dev, "can't take mmu out of reset\n"); | |
87 | return -ENODEV; | |
88 | } | |
89 | ||
90 | l = iommu_read_reg(obj, MMU_REVISION); | |
91 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
92 | (l >> 4) & 0xf, l & 0xf); | |
93 | ||
94 | l = iommu_read_reg(obj, MMU_SYSCONFIG); | |
95 | l &= ~MMU_SYS_IDLE_MASK; | |
96 | l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); | |
97 | iommu_write_reg(obj, l, MMU_SYSCONFIG); | |
98 | ||
99 | iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); | |
100 | iommu_write_reg(obj, pa, MMU_TTB); | |
101 | ||
102 | l = iommu_read_reg(obj, MMU_CNTL); | |
103 | l &= ~MMU_CNTL_MASK; | |
104 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
105 | iommu_write_reg(obj, l, MMU_CNTL); | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
110 | static void omap2_iommu_disable(struct iommu *obj) | |
111 | { | |
112 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
113 | ||
114 | l &= ~MMU_CNTL_MASK; | |
115 | iommu_write_reg(obj, l, MMU_CNTL); | |
116 | iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); | |
117 | ||
118 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
119 | } | |
120 | ||
121 | static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) | |
122 | { | |
123 | int i; | |
124 | u32 stat, da; | |
125 | const char *err_msg[] = { | |
126 | "tlb miss", | |
127 | "translation fault", | |
128 | "emulation miss", | |
129 | "table walk fault", | |
130 | "multi hit fault", | |
131 | }; | |
132 | ||
133 | stat = iommu_read_reg(obj, MMU_IRQSTATUS); | |
134 | stat &= MMU_IRQ_MASK; | |
135 | if (!stat) | |
136 | return 0; | |
137 | ||
138 | da = iommu_read_reg(obj, MMU_FAULT_AD); | |
139 | *ra = da; | |
140 | ||
141 | dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); | |
142 | ||
143 | for (i = 0; i < ARRAY_SIZE(err_msg); i++) { | |
144 | if (stat & (1 << i)) | |
145 | printk("%s ", err_msg[i]); | |
146 | } | |
147 | printk("\n"); | |
148 | ||
149 | iommu_write_reg(obj, stat, MMU_IRQSTATUS); | |
be6d8026 | 150 | omap2_iommu_disable(obj); |
2bcb5733 HD |
151 | return stat; |
152 | } | |
153 | ||
154 | static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) | |
155 | { | |
156 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); | |
157 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
158 | } | |
159 | ||
160 | static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) | |
161 | { | |
162 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); | |
163 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
164 | } | |
165 | ||
166 | static u32 omap2_cr_to_virt(struct cr_regs *cr) | |
167 | { | |
168 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; | |
169 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
170 | ||
171 | return cr->cam & mask; | |
172 | } | |
173 | ||
174 | static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) | |
175 | { | |
176 | struct cr_regs *cr; | |
177 | ||
178 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
179 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
180 | e->da); | |
181 | return ERR_PTR(-EINVAL); | |
182 | } | |
183 | ||
184 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
185 | if (!cr) | |
186 | return ERR_PTR(-ENOMEM); | |
187 | ||
77bc5abb | 188 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; |
2bcb5733 HD |
189 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; |
190 | ||
191 | return cr; | |
192 | } | |
193 | ||
194 | static inline int omap2_cr_valid(struct cr_regs *cr) | |
195 | { | |
196 | return cr->cam & MMU_CAM_V; | |
197 | } | |
198 | ||
199 | static u32 omap2_get_pte_attr(struct iotlb_entry *e) | |
200 | { | |
201 | u32 attr; | |
202 | ||
203 | attr = e->mixed << 5; | |
204 | attr |= e->endian; | |
205 | attr |= e->elsz >> 3; | |
206 | attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6); | |
207 | ||
208 | return attr; | |
209 | } | |
210 | ||
211 | static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) | |
212 | { | |
213 | char *p = buf; | |
214 | ||
215 | /* FIXME: Need more detail analysis of cam/ram */ | |
be6d8026 KH |
216 | p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, |
217 | (cr->cam & MMU_CAM_P) ? 1 : 0); | |
2bcb5733 HD |
218 | |
219 | return p - buf; | |
220 | } | |
221 | ||
222 | #define pr_reg(name) \ | |
14e0e679 HD |
223 | do { \ |
224 | ssize_t bytes; \ | |
225 | const char *str = "%20s: %08x\n"; \ | |
226 | const int maxcol = 32; \ | |
227 | bytes = snprintf(p, maxcol, str, __stringify(name), \ | |
228 | iommu_read_reg(obj, MMU_##name)); \ | |
229 | p += bytes; \ | |
230 | len -= bytes; \ | |
231 | if (len < maxcol) \ | |
232 | goto out; \ | |
233 | } while (0) | |
234 | ||
235 | static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len) | |
2bcb5733 HD |
236 | { |
237 | char *p = buf; | |
238 | ||
239 | pr_reg(REVISION); | |
240 | pr_reg(SYSCONFIG); | |
241 | pr_reg(SYSSTATUS); | |
242 | pr_reg(IRQSTATUS); | |
243 | pr_reg(IRQENABLE); | |
244 | pr_reg(WALKING_ST); | |
245 | pr_reg(CNTL); | |
246 | pr_reg(FAULT_AD); | |
247 | pr_reg(TTB); | |
248 | pr_reg(LOCK); | |
249 | pr_reg(LD_TLB); | |
250 | pr_reg(CAM); | |
251 | pr_reg(RAM); | |
252 | pr_reg(GFLUSH); | |
253 | pr_reg(FLUSH_ENTRY); | |
254 | pr_reg(READ_CAM); | |
255 | pr_reg(READ_RAM); | |
256 | pr_reg(EMU_FAULT_AD); | |
14e0e679 | 257 | out: |
2bcb5733 HD |
258 | return p - buf; |
259 | } | |
260 | ||
261 | static void omap2_iommu_save_ctx(struct iommu *obj) | |
262 | { | |
263 | int i; | |
264 | u32 *p = obj->ctx; | |
265 | ||
266 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
267 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
268 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
269 | } | |
270 | ||
271 | BUG_ON(p[0] != IOMMU_ARCH_VERSION); | |
272 | } | |
273 | ||
274 | static void omap2_iommu_restore_ctx(struct iommu *obj) | |
275 | { | |
276 | int i; | |
277 | u32 *p = obj->ctx; | |
278 | ||
279 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
280 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
281 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
282 | } | |
283 | ||
284 | BUG_ON(p[0] != IOMMU_ARCH_VERSION); | |
285 | } | |
286 | ||
287 | static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) | |
288 | { | |
289 | e->da = cr->cam & MMU_CAM_VATAG_MASK; | |
290 | e->pa = cr->ram & MMU_RAM_PADDR_MASK; | |
291 | e->valid = cr->cam & MMU_CAM_V; | |
292 | e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; | |
293 | e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; | |
294 | e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; | |
295 | e->mixed = cr->ram & MMU_RAM_MIXED; | |
296 | } | |
297 | ||
298 | static const struct iommu_functions omap2_iommu_ops = { | |
299 | .version = IOMMU_ARCH_VERSION, | |
300 | ||
301 | .enable = omap2_iommu_enable, | |
302 | .disable = omap2_iommu_disable, | |
303 | .fault_isr = omap2_iommu_fault_isr, | |
304 | ||
305 | .tlb_read_cr = omap2_tlb_read_cr, | |
306 | .tlb_load_cr = omap2_tlb_load_cr, | |
307 | ||
308 | .cr_to_e = omap2_cr_to_e, | |
309 | .cr_to_virt = omap2_cr_to_virt, | |
310 | .alloc_cr = omap2_alloc_cr, | |
311 | .cr_valid = omap2_cr_valid, | |
312 | .dump_cr = omap2_dump_cr, | |
313 | ||
314 | .get_pte_attr = omap2_get_pte_attr, | |
315 | ||
316 | .save_ctx = omap2_iommu_save_ctx, | |
317 | .restore_ctx = omap2_iommu_restore_ctx, | |
318 | .dump_ctx = omap2_iommu_dump_ctx, | |
319 | }; | |
320 | ||
321 | static int __init omap2_iommu_init(void) | |
322 | { | |
323 | return install_iommu_arch(&omap2_iommu_ops); | |
324 | } | |
325 | module_init(omap2_iommu_init); | |
326 | ||
327 | static void __exit omap2_iommu_exit(void) | |
328 | { | |
329 | uninstall_iommu_arch(&omap2_iommu_ops); | |
330 | } | |
331 | module_exit(omap2_iommu_exit); | |
332 | ||
333 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
334 | MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); | |
335 | MODULE_LICENSE("GPL v2"); |