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Merge tag 'for-linux-6.12-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / arm / mach-omap2 / io.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1dbae815
TL		 2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
44169075 8 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
1dbae815 13 *
44169075 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 15 */
1dbae815
TL		 16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
fced80c7 19#include <linux/io.h>
2f135eaf 20#include <linux/clk.h>
1dbae815 21
120db2cb 22#include <asm/tlb.h>
120db2cb
TL		 23#include <asm/mach/map.h>
24
45c3eb7d 25#include <linux/omap-dma.h>
ee0839c2 26
dc843280 27#include "omap_hwmod.h"
dbc04161 28#include "soc.h"
ee0839c2 29#include "iomap.h"
81a60482 30#include "voltage.h"
72e06d08 31#include "powerdomain.h"
1540f214 32#include "clockdomain.h"
4e65331c 33#include "common.h"
e30384ab 34#include "clock.h"
3e6ece13 35#include "sdrc.h"
b6a4226c 36#include "control.h"
bf027ca1 37#include "sram.h"
c4ceedcb
PW		 38#include "cm2xxx.h"
39#include "cm3xxx.h"
7632a02f 40#include "cm33xx.h"
ab6c9bbf 41#include "cm44xx.h"
d9a16f9a
PW		 42#include "prm.h"
43#include "cm.h"
44#include "prcm_mpu44xx.h"
45#include "prminst44xx.h"
63a293e0
PW		 46#include "prm2xxx.h"
47#include "prm3xxx.h"
d9bbe84f 48#include "prm33xx.h"
63a293e0 49#include "prm44xx.h"
69a1e7a1 50#include "opp2xxx.h"
db711893 51#include "omap-secure.h"
02bfc030 52
ff931c82 53/*
cfa9667d 54 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 55 * clock initializations
56 */
cfa9667d 57static int (*omap_clk_soc_init)(void);
ff931c82 58
1dbae815
TL		 59/*
60 * The machine specific code may provide the extra mapping besides the
61 * default mapping provided here.
62 */
cc26b3b0 63
e48f814e 64#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 65static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 66 {
67 .virtual = L3_24XX_VIRT,
68 .pfn = __phys_to_pfn(L3_24XX_PHYS),
69 .length = L3_24XX_SIZE,
70 .type = MT_DEVICE
71 },
09f21ed4 72 {
cc26b3b0
SMK		 73 .virtual = L4_24XX_VIRT,
74 .pfn = __phys_to_pfn(L4_24XX_PHYS),
75 .length = L4_24XX_SIZE,
76 .type = MT_DEVICE
09f21ed4 77 },
cc26b3b0
SMK		 78};
79
59b479e0 80#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 81static struct map_desc omap242x_io_desc[] __initdata = {
82 {
7adb9987
PW		 83 .virtual = DSP_MEM_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
85 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 86 .type = MT_DEVICE
87 },
88 {
7adb9987
PW		 89 .virtual = DSP_IPI_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
91 .length = DSP_IPI_2420_SIZE,
cc26b3b0 92 .type = MT_DEVICE
09f21ed4 93 },
cc26b3b0 94 {
7adb9987
PW		 95 .virtual = DSP_MMU_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
97 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 98 .type = MT_DEVICE
99 },
100};
101
102#endif
103
59b479e0 104#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 105static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 106 {
107 .virtual = L4_WK_243X_VIRT,
108 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
109 .length = L4_WK_243X_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_GPMC_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
115 .length = OMAP243X_GPMC_SIZE,
116 .type = MT_DEVICE
117 },
cc26b3b0
SMK		 118 {
119 .virtual = OMAP243X_SDRC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
121 .length = OMAP243X_SDRC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SMS_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
127 .length = OMAP243X_SMS_SIZE,
128 .type = MT_DEVICE
129 },
130};
72d0f1c3 131#endif
72d0f1c3 132#endif
cc26b3b0 133
a8eb7ca0 134#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 135static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 136 {
cc26b3b0
SMK		 137 .virtual = L3_34XX_VIRT,
138 .pfn = __phys_to_pfn(L3_34XX_PHYS),
139 .length = L3_34XX_SIZE,
c40fae95
TL		 140 .type = MT_DEVICE
141 },
142 {
cc26b3b0
SMK		 143 .virtual = L4_34XX_VIRT,
144 .pfn = __phys_to_pfn(L4_34XX_PHYS),
145 .length = L4_34XX_SIZE,
c40fae95
TL		 146 .type = MT_DEVICE
147 },
cc26b3b0
SMK		 148 {
149 .virtual = OMAP34XX_GPMC_VIRT,
150 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
151 .length = OMAP34XX_GPMC_SIZE,
1dbae815 152 .type = MT_DEVICE
cc26b3b0
SMK		 153 },
154 {
155 .virtual = OMAP343X_SMS_VIRT,
156 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
157 .length = OMAP343X_SMS_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SDRC_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
163 .length = OMAP343X_SDRC_SIZE,
1dbae815 164 .type = MT_DEVICE
cc26b3b0
SMK		 165 },
166 {
167 .virtual = L4_PER_34XX_VIRT,
168 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
169 .length = L4_PER_34XX_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_EMU_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
175 .length = L4_EMU_34XX_SIZE,
176 .type = MT_DEVICE
177 },
1dbae815 178};
cc26b3b0 179#endif
01001712 180
33959553 181#ifdef CONFIG_SOC_TI81XX
a920360f 182static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 183 {
184 .virtual = L4_34XX_VIRT,
185 .pfn = __phys_to_pfn(L4_34XX_PHYS),
186 .length = L4_34XX_SIZE,
187 .type = MT_DEVICE
188 }
189};
190#endif
191
addb154a 192#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 193static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 194 {
195 .virtual = L4_34XX_VIRT,
196 .pfn = __phys_to_pfn(L4_34XX_PHYS),
197 .length = L4_34XX_SIZE,
198 .type = MT_DEVICE
199 },
1e6cb146
AM		 200 {
201 .virtual = L4_WK_AM33XX_VIRT,
202 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
203 .length = L4_WK_AM33XX_SIZE,
204 .type = MT_DEVICE
205 }
01001712
HP		 206};
207#endif
208
44169075
SS		 209#ifdef CONFIG_ARCH_OMAP4
210static struct map_desc omap44xx_io_desc[] __initdata = {
211 {
212 .virtual = L3_44XX_VIRT,
213 .pfn = __phys_to_pfn(L3_44XX_PHYS),
214 .length = L3_44XX_SIZE,
215 .type = MT_DEVICE,
216 },
217 {
218 .virtual = L4_44XX_VIRT,
219 .pfn = __phys_to_pfn(L4_44XX_PHYS),
220 .length = L4_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
44169075
SS		 223 {
224 .virtual = L4_PER_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
226 .length = L4_PER_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
44169075
SS		 229};
230#endif
1dbae815 231
ea827ad5 232#ifdef CONFIG_SOC_OMAP5
05e152c7
S		 233static struct map_desc omap54xx_io_desc[] __initdata = {
234 {
235 .virtual = L3_54XX_VIRT,
236 .pfn = __phys_to_pfn(L3_54XX_PHYS),
237 .length = L3_54XX_SIZE,
238 .type = MT_DEVICE,
239 },
240 {
241 .virtual = L4_54XX_VIRT,
242 .pfn = __phys_to_pfn(L4_54XX_PHYS),
243 .length = L4_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_WK_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
249 .length = L4_WK_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_PER_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
255 .length = L4_PER_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258};
259#endif
260
ea827ad5
NM		 261#ifdef CONFIG_SOC_DRA7XX
262static struct map_desc dra7xx_io_desc[] __initdata = {
263 {
264 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
265 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
266 .length = L4_CFG_MPU_DRA7XX_SIZE,
267 .type = MT_DEVICE,
268 },
269 {
270 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
272 .length = L3_MAIN_SN_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L4_PER1_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
278 .length = L4_PER1_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER2_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
284 .length = L4_PER2_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER3_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
290 .length = L4_PER3_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_CFG_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
296 .length = L4_CFG_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_WKUP_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
302 .length = L4_WKUP_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305};
306#endif
307
59b479e0 308#ifdef CONFIG_SOC_OMAP2420
b6a4226c 309void __init omap242x_map_io(void)
1dbae815 310{
cc26b3b0
SMK		 311 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
312 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 313}
cc26b3b0
SMK		 314#endif
315
59b479e0 316#ifdef CONFIG_SOC_OMAP2430
b6a4226c 317void __init omap243x_map_io(void)
6fbd55d0 318{
cc26b3b0
SMK		 319 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
320 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 321}
cc26b3b0
SMK		 322#endif
323
a8eb7ca0 324#ifdef CONFIG_ARCH_OMAP3
b6a4226c 325void __init omap3_map_io(void)
6fbd55d0 326{
cc26b3b0 327 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 328}
cc26b3b0 329#endif
120db2cb 330
33959553 331#ifdef CONFIG_SOC_TI81XX
b6a4226c 332void __init ti81xx_map_io(void)
01001712 333{
a920360f 334 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 335}
336#endif
337
addb154a 338#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 339void __init am33xx_map_io(void)
01001712 340{
1e6cb146 341 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 342}
343#endif
344
6fbd55d0 345#ifdef CONFIG_ARCH_OMAP4
b6a4226c 346void __init omap4_map_io(void)
6fbd55d0 347{
44169075 348 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
f746929f 349 omap_barriers_init();
120db2cb 350}
6fbd55d0 351#endif
120db2cb 352
ea827ad5 353#ifdef CONFIG_SOC_OMAP5
b6a4226c 354void __init omap5_map_io(void)
05e152c7
S		 355{
356 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
f746929f 357 omap_barriers_init();
05e152c7
S		 358}
359#endif
ea827ad5
NM		 360
361#ifdef CONFIG_SOC_DRA7XX
362void __init dra7xx_map_io(void)
363{
364 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
456e8d53 365 omap_barriers_init();
ea827ad5
NM		 366}
367#endif
2f135eaf
PW		 368/*
369 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
370 *
371 * Sets the CORE DPLL3 M2 divider to the same value that it's at
372 * currently. This has the effect of setting the SDRC SDRAM AC timing
373 * registers to the values currently defined by the kernel. Currently
374 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
375 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
376 * or passes along the return value of clk_set_rate().
377 */
378static int __init _omap2_init_reprogram_sdrc(void)
379{
380 struct clk *dpll3_m2_ck;
381 int v = -EINVAL;
382 long rate;
383
384 if (!cpu_is_omap34xx())
385 return 0;
386
387 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 388 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 389 return -EINVAL;
390
391 rate = clk_get_rate(dpll3_m2_ck);
392 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
393 v = clk_set_rate(dpll3_m2_ck, rate);
394 if (v)
395 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
396
397 clk_put(dpll3_m2_ck);
398
399 return v;
400}
401
f21af425 402#ifdef CONFIG_OMAP_HWMOD
2092e5cc
PW		 403static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
404{
405 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
406}
407
293ea3d0 408static void __init __maybe_unused omap_hwmod_init_postsetup(void)
7b250aff 409{
6d63b12d 410 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
2092e5cc
PW		 411
412 /* Set the default postsetup state for all hwmods */
2092e5cc 413 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
4805734b 414}
f21af425
TL		 415#else
416static inline void omap_hwmod_init_postsetup(void)
417{
418}
419#endif
4805734b 420
16110798 421#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 422void __init omap2420_init_early(void)
423{
b6a4226c
PW		 424 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
425 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
426 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
2208bf11 427 omap2_control_base_init();
4de34f35 428 omap2xxx_check_revision();
ab7b2ffc 429 omap2_prcm_base_init();
7b250aff
TL		 430 omap2xxx_voltagedomains_init();
431 omap242x_powerdomains_init();
432 omap242x_clockdomains_init();
433 omap2420_hwmod_init();
434 omap_hwmod_init_postsetup();
6a194a6e
TK		 435 omap_clk_soc_init = omap2420_dt_clk_init;
436 rate_table = omap2420_rate_table;
8f5b5a41 437}
16110798 438#endif
8f5b5a41 439
16110798 440#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 441void __init omap2430_init_early(void)
442{
b6a4226c
PW		 443 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
444 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
445 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
2208bf11 446 omap2_control_base_init();
4de34f35 447 omap2xxx_check_revision();
ab7b2ffc 448 omap2_prcm_base_init();
7b250aff
TL		 449 omap2xxx_voltagedomains_init();
450 omap243x_powerdomains_init();
451 omap243x_clockdomains_init();
452 omap2430_hwmod_init();
453 omap_hwmod_init_postsetup();
6a194a6e
TK		 454 omap_clk_soc_init = omap2430_dt_clk_init;
455 rate_table = omap2430_rate_table;
7b250aff 456}
c4e2d245 457#endif
7b250aff
TL		 458
459/*
460 * Currently only board-omap3beagle.c should call this because of the
461 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
462 */
c4e2d245 463#ifdef CONFIG_ARCH_OMAP3
6aeb51c1 464static void __init omap3_init_early(void)
7b250aff 465{
b6a4226c
PW		 466 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
467 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
468 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
2208bf11 469 omap2_control_base_init();
4de34f35
VH		 470 omap3xxx_check_revision();
471 omap3xxx_check_features();
ab7b2ffc 472 omap2_prcm_base_init();
7b250aff
TL		 473 omap3xxx_voltagedomains_init();
474 omap3xxx_powerdomains_init();
475 omap3xxx_clockdomains_init();
476 omap3xxx_hwmod_init();
477 omap_hwmod_init_postsetup();
db711893 478 omap_secure_init();
8f5b5a41
TL		 479}
480
481void __init omap3430_init_early(void)
482{
7b250aff 483 omap3_init_early();
58a641c8 484 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 485}
486
8f5b5a41
TL		 487void __init omap3630_init_early(void)
488{
7b250aff 489 omap3_init_early();
58a641c8 490 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 491}
492
493void __init am35xx_init_early(void)
494{
7b250aff 495 omap3_init_early();
58a641c8 496 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 497}
498
bbd707ac
SG		 499void __init omap3_init_late(void)
500{
02b83dcb 501 omap_pm_soc_init = omap3_pm_init;
bbd707ac
SG		 502}
503
504void __init ti81xx_init_late(void)
505{
02b83dcb 506 omap_pm_soc_init = omap_pm_nop_init;
bbd707ac 507}
c4e2d245 508#endif
8f5b5a41 509
a64459c4
AM		 510#ifdef CONFIG_SOC_TI81XX
511void __init ti814x_init_early(void)
512{
513 omap2_set_globals_tap(TI814X_CLASS,
514 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 515 omap2_control_base_init();
a64459c4
AM		 516 omap3xxx_check_revision();
517 ti81xx_check_features();
ab7b2ffc 518 omap2_prcm_base_init();
a64459c4
AM		 519 omap3xxx_voltagedomains_init();
520 omap3xxx_powerdomains_init();
185fde6d 521 ti814x_clockdomains_init();
0f3ccb24 522 dm814x_hwmod_init();
a64459c4 523 omap_hwmod_init_postsetup();
d893656e 524 omap_clk_soc_init = dm814x_dt_clk_init;
db711893 525 omap_secure_init();
a64459c4
AM		 526}
527
528void __init ti816x_init_early(void)
529{
530 omap2_set_globals_tap(TI816X_CLASS,
531 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 532 omap2_control_base_init();
a64459c4
AM		 533 omap3xxx_check_revision();
534 ti81xx_check_features();
ab7b2ffc 535 omap2_prcm_base_init();
a64459c4
AM		 536 omap3xxx_voltagedomains_init();
537 omap3xxx_powerdomains_init();
185fde6d 538 ti816x_clockdomains_init();
0f3ccb24 539 dm816x_hwmod_init();
a64459c4 540 omap_hwmod_init_postsetup();
58a641c8 541 omap_clk_soc_init = dm816x_dt_clk_init;
db711893 542 omap_secure_init();
a64459c4
AM		 543}
544#endif
545
08f30989
AM		 546#ifdef CONFIG_SOC_AM33XX
547void __init am33xx_init_early(void)
548{
b6a4226c
PW		 549 omap2_set_globals_tap(AM335X_CLASS,
550 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 551 omap2_control_base_init();
08f30989 552 omap3xxx_check_revision();
7bcad170 553 am33xx_check_features();
ab7b2ffc 554 omap2_prcm_base_init();
3f0ea764 555 am33xx_powerdomains_init();
9c80f3aa 556 am33xx_clockdomains_init();
149c09d3 557 omap_clk_soc_init = am33xx_dt_clk_init;
db711893 558 omap_secure_init();
08f30989 559}
765e7a06
NM		 560
561void __init am33xx_init_late(void)
562{
02b83dcb 563 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 564}
08f30989
AM		 565#endif
566
c5107027
AM		 567#ifdef CONFIG_SOC_AM43XX
568void __init am43xx_init_early(void)
569{
570 omap2_set_globals_tap(AM335X_CLASS,
571 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 572 omap2_control_base_init();
c5107027 573 omap3xxx_check_revision();
7a2e0513 574 am33xx_check_features();
ab7b2ffc 575 omap2_prcm_base_init();
8835cf6e
A		 576 am43xx_powerdomains_init();
577 am43xx_clockdomains_init();
d941f86f 578 omap_l2_cache_init();
d22031e2 579 omap_clk_soc_init = am43xx_dt_clk_init;
db711893 580 omap_secure_init();
c5107027 581}
765e7a06
NM		 582
583void __init am43xx_init_late(void)
584{
02b83dcb 585 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 586}
c5107027
AM		 587#endif
588
c4e2d245 589#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 590void __init omap4430_init_early(void)
591{
b6a4226c
PW		 592 omap2_set_globals_tap(OMAP443X_CLASS,
593 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
d9a16f9a 594 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
ca125b5e 595 omap2_control_base_init();
4de34f35
VH		 596 omap4xxx_check_revision();
597 omap4xxx_check_features();
ab7b2ffc 598 omap2_prcm_base_init();
f4b9f40a 599 omap4_sar_ram_init();
0573b957 600 omap4_mpuss_early_init();
de70af49 601 omap4_pm_init_early();
7b250aff
TL		 602 omap44xx_voltagedomains_init();
603 omap44xx_powerdomains_init();
604 omap44xx_clockdomains_init();
b39b14e6 605 omap_l2_cache_init();
c8c88d85 606 omap_clk_soc_init = omap4xxx_dt_clk_init;
db711893 607 omap_secure_init();
8f5b5a41 608}
bbd707ac
SG		 609
610void __init omap4430_init_late(void)
611{
02b83dcb 612 omap_pm_soc_init = omap4_pm_init;
bbd707ac 613}
c4e2d245 614#endif
8f5b5a41 615
05e152c7
S		 616#ifdef CONFIG_SOC_OMAP5
617void __init omap5_init_early(void)
618{
b6a4226c
PW		 619 omap2_set_globals_tap(OMAP54XX_CLASS,
620 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
d9a16f9a 621 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 622 omap2_control_base_init();
ab7b2ffc 623 omap2_prcm_base_init();
05e152c7 624 omap5xxx_check_revision();
f4b9f40a 625 omap4_sar_ram_init();
8a8be46a
TL		 626 omap4_mpuss_early_init();
627 omap4_pm_init_early();
e4020aa9
SS		 628 omap54xx_voltagedomains_init();
629 omap54xx_powerdomains_init();
630 omap54xx_clockdomains_init();
cfa9667d 631 omap_clk_soc_init = omap5xxx_dt_clk_init;
db711893 632 omap_secure_init();
05e152c7 633}
765e7a06
NM		 634
635void __init omap5_init_late(void)
636{
02b83dcb 637 omap_pm_soc_init = omap4_pm_init;
765e7a06 638}
05e152c7
S		 639#endif
640
a3a9384a
S		 641#ifdef CONFIG_SOC_DRA7XX
642void __init dra7xx_init_early(void)
643{
ec490f6f
NM		 644 omap2_set_globals_tap(DRA7XX_CLASS,
645 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
a3a9384a 646 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 647 omap2_control_base_init();
6af16a1d 648 omap4_pm_init_early();
ab7b2ffc 649 omap2_prcm_base_init();
733d20ee 650 dra7xxx_check_revision();
7de516a6
A		 651 dra7xx_powerdomains_init();
652 dra7xx_clockdomains_init();
f1cf498e 653 omap_clk_soc_init = dra7xx_dt_clk_init;
db711893 654 omap_secure_init();
a3a9384a 655}
765e7a06
NM		 656
657void __init dra7xx_init_late(void)
658{
02b83dcb 659 omap_pm_soc_init = omap4_pm_init;
765e7a06 660}
a3a9384a
S		 661#endif
662
663
a4ca9dbe 664void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 665 struct omap_sdrc_params *sdrc_cs1)
666{
a66cb345
TL		 667 omap_sram_init();
668
01001712 669 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 670 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
671 _omap2_init_reprogram_sdrc();
672 }
1dbae815 673}
cfa9667d
TK		 674
675int __init omap_clk_init(void)
676{
677 int ret = 0;
678
679 if (!omap_clk_soc_init)
680 return 0;
681
8111e010
TK		 682 ti_clk_init_features();
683
e9e63088
TK		 684 omap2_clk_setup_ll_ops();
685
58a641c8
TL		 686 ret = omap_control_init();
687 if (ret)
688 return ret;
fe87414f 689
58a641c8
TL		 690 ret = omap_prcm_init();
691 if (ret)
692 return ret;
c08ee14c 693
58a641c8 694 of_clk_init(NULL);
c08ee14c 695
58a641c8 696 ti_dt_clk_init_retry_clks();
c08ee14c 697
58a641c8 698 ti_dt_clockdomains_setup();
c08ee14c
TK		 699
700 ret = omap_clk_soc_init();
cfa9667d
TK		 701
702 return ret;
703}
Linux 6.x block layer and io_uring tree(s)