Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
91773a00 | 24 | #include <linux/omapfb.h> |
1dbae815 | 25 | |
120db2cb | 26 | #include <asm/tlb.h> |
120db2cb TL |
27 | |
28 | #include <asm/mach/map.h> | |
29 | ||
ce491cf8 TL |
30 | #include <plat/sram.h> |
31 | #include <plat/sdrc.h> | |
ce491cf8 | 32 | #include <plat/serial.h> |
646e3ed1 | 33 | |
e80a9729 | 34 | #include "clock2xxx.h" |
657ebfad | 35 | #include "clock3xxx.h" |
e80a9729 | 36 | #include "clock44xx.h" |
1dbae815 | 37 | |
a66cb345 | 38 | #include <plat/common.h> |
ce491cf8 | 39 | #include <plat/omap-pm.h> |
81a60482 | 40 | #include "voltage.h" |
72e06d08 | 41 | #include "powerdomain.h" |
1dbae815 | 42 | |
1540f214 | 43 | #include "clockdomain.h" |
ce491cf8 | 44 | #include <plat/omap_hwmod.h> |
5d190c40 | 45 | #include <plat/multi.h> |
4c3cf901 | 46 | #include <plat/common.h> |
02bfc030 | 47 | |
1dbae815 TL |
48 | /* |
49 | * The machine specific code may provide the extra mapping besides the | |
50 | * default mapping provided here. | |
51 | */ | |
cc26b3b0 | 52 | |
088ef950 | 53 | #ifdef CONFIG_ARCH_OMAP2 |
cc26b3b0 | 54 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
55 | { |
56 | .virtual = L3_24XX_VIRT, | |
57 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
58 | .length = L3_24XX_SIZE, | |
59 | .type = MT_DEVICE | |
60 | }, | |
09f21ed4 | 61 | { |
cc26b3b0 SMK |
62 | .virtual = L4_24XX_VIRT, |
63 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
64 | .length = L4_24XX_SIZE, | |
65 | .type = MT_DEVICE | |
09f21ed4 | 66 | }, |
cc26b3b0 SMK |
67 | }; |
68 | ||
59b479e0 | 69 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
70 | static struct map_desc omap242x_io_desc[] __initdata = { |
71 | { | |
7adb9987 PW |
72 | .virtual = DSP_MEM_2420_VIRT, |
73 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
74 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
75 | .type = MT_DEVICE |
76 | }, | |
77 | { | |
7adb9987 PW |
78 | .virtual = DSP_IPI_2420_VIRT, |
79 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
80 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 81 | .type = MT_DEVICE |
09f21ed4 | 82 | }, |
cc26b3b0 | 83 | { |
7adb9987 PW |
84 | .virtual = DSP_MMU_2420_VIRT, |
85 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
86 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
87 | .type = MT_DEVICE |
88 | }, | |
89 | }; | |
90 | ||
91 | #endif | |
92 | ||
59b479e0 | 93 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 94 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
95 | { |
96 | .virtual = L4_WK_243X_VIRT, | |
97 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
98 | .length = L4_WK_243X_SIZE, | |
99 | .type = MT_DEVICE | |
100 | }, | |
101 | { | |
102 | .virtual = OMAP243X_GPMC_VIRT, | |
103 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
104 | .length = OMAP243X_GPMC_SIZE, | |
105 | .type = MT_DEVICE | |
106 | }, | |
cc26b3b0 SMK |
107 | { |
108 | .virtual = OMAP243X_SDRC_VIRT, | |
109 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
110 | .length = OMAP243X_SDRC_SIZE, | |
111 | .type = MT_DEVICE | |
112 | }, | |
113 | { | |
114 | .virtual = OMAP243X_SMS_VIRT, | |
115 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
116 | .length = OMAP243X_SMS_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | }; | |
72d0f1c3 | 120 | #endif |
72d0f1c3 | 121 | #endif |
cc26b3b0 | 122 | |
a8eb7ca0 | 123 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 124 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 125 | { |
cc26b3b0 SMK |
126 | .virtual = L3_34XX_VIRT, |
127 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
128 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
129 | .type = MT_DEVICE |
130 | }, | |
131 | { | |
cc26b3b0 SMK |
132 | .virtual = L4_34XX_VIRT, |
133 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
134 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
135 | .type = MT_DEVICE |
136 | }, | |
cc26b3b0 SMK |
137 | { |
138 | .virtual = OMAP34XX_GPMC_VIRT, | |
139 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
140 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 141 | .type = MT_DEVICE |
cc26b3b0 SMK |
142 | }, |
143 | { | |
144 | .virtual = OMAP343X_SMS_VIRT, | |
145 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
146 | .length = OMAP343X_SMS_SIZE, | |
147 | .type = MT_DEVICE | |
148 | }, | |
149 | { | |
150 | .virtual = OMAP343X_SDRC_VIRT, | |
151 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
152 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 153 | .type = MT_DEVICE |
cc26b3b0 SMK |
154 | }, |
155 | { | |
156 | .virtual = L4_PER_34XX_VIRT, | |
157 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
158 | .length = L4_PER_34XX_SIZE, | |
159 | .type = MT_DEVICE | |
160 | }, | |
161 | { | |
162 | .virtual = L4_EMU_34XX_VIRT, | |
163 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
164 | .length = L4_EMU_34XX_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
a4f57b81 TL |
167 | #if defined(CONFIG_DEBUG_LL) && \ |
168 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
169 | { | |
170 | .virtual = ZOOM_UART_VIRT, | |
171 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
172 | .length = SZ_1M, | |
173 | .type = MT_DEVICE | |
174 | }, | |
175 | #endif | |
1dbae815 | 176 | }; |
cc26b3b0 | 177 | #endif |
01001712 HP |
178 | |
179 | #ifdef CONFIG_SOC_OMAPTI816X | |
180 | static struct map_desc omapti816x_io_desc[] __initdata = { | |
181 | { | |
182 | .virtual = L4_34XX_VIRT, | |
183 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
184 | .length = L4_34XX_SIZE, | |
185 | .type = MT_DEVICE | |
186 | }, | |
187 | }; | |
188 | #endif | |
189 | ||
44169075 SS |
190 | #ifdef CONFIG_ARCH_OMAP4 |
191 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
192 | { | |
193 | .virtual = L3_44XX_VIRT, | |
194 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
195 | .length = L3_44XX_SIZE, | |
196 | .type = MT_DEVICE, | |
197 | }, | |
198 | { | |
199 | .virtual = L4_44XX_VIRT, | |
200 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
201 | .length = L4_44XX_SIZE, | |
202 | .type = MT_DEVICE, | |
203 | }, | |
44169075 SS |
204 | { |
205 | .virtual = OMAP44XX_GPMC_VIRT, | |
206 | .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), | |
207 | .length = OMAP44XX_GPMC_SIZE, | |
208 | .type = MT_DEVICE, | |
209 | }, | |
f5d2d659 SS |
210 | { |
211 | .virtual = OMAP44XX_EMIF1_VIRT, | |
212 | .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), | |
213 | .length = OMAP44XX_EMIF1_SIZE, | |
214 | .type = MT_DEVICE, | |
215 | }, | |
216 | { | |
217 | .virtual = OMAP44XX_EMIF2_VIRT, | |
218 | .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), | |
219 | .length = OMAP44XX_EMIF2_SIZE, | |
220 | .type = MT_DEVICE, | |
221 | }, | |
222 | { | |
223 | .virtual = OMAP44XX_DMM_VIRT, | |
224 | .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), | |
225 | .length = OMAP44XX_DMM_SIZE, | |
226 | .type = MT_DEVICE, | |
227 | }, | |
44169075 SS |
228 | { |
229 | .virtual = L4_PER_44XX_VIRT, | |
230 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
231 | .length = L4_PER_44XX_SIZE, | |
232 | .type = MT_DEVICE, | |
233 | }, | |
234 | { | |
235 | .virtual = L4_EMU_44XX_VIRT, | |
236 | .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), | |
237 | .length = L4_EMU_44XX_SIZE, | |
238 | .type = MT_DEVICE, | |
239 | }, | |
240 | }; | |
241 | #endif | |
1dbae815 | 242 | |
59b479e0 | 243 | #ifdef CONFIG_SOC_OMAP2420 |
8185e468 | 244 | void __init omap242x_map_common_io(void) |
1dbae815 | 245 | { |
cc26b3b0 SMK |
246 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
247 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 248 | } |
cc26b3b0 SMK |
249 | #endif |
250 | ||
59b479e0 | 251 | #ifdef CONFIG_SOC_OMAP2430 |
8185e468 | 252 | void __init omap243x_map_common_io(void) |
6fbd55d0 | 253 | { |
cc26b3b0 SMK |
254 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
255 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 256 | } |
cc26b3b0 SMK |
257 | #endif |
258 | ||
a8eb7ca0 | 259 | #ifdef CONFIG_ARCH_OMAP3 |
8185e468 | 260 | void __init omap34xx_map_common_io(void) |
6fbd55d0 | 261 | { |
cc26b3b0 | 262 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 263 | } |
cc26b3b0 | 264 | #endif |
120db2cb | 265 | |
01001712 HP |
266 | #ifdef CONFIG_SOC_OMAPTI816X |
267 | void __init omapti816x_map_common_io(void) | |
268 | { | |
269 | iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); | |
01001712 HP |
270 | } |
271 | #endif | |
272 | ||
6fbd55d0 | 273 | #ifdef CONFIG_ARCH_OMAP4 |
8185e468 | 274 | void __init omap44xx_map_common_io(void) |
6fbd55d0 | 275 | { |
44169075 | 276 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
120db2cb | 277 | } |
6fbd55d0 | 278 | #endif |
120db2cb | 279 | |
2f135eaf PW |
280 | /* |
281 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
282 | * | |
283 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
284 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
285 | * registers to the values currently defined by the kernel. Currently | |
286 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
287 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
288 | * or passes along the return value of clk_set_rate(). | |
289 | */ | |
290 | static int __init _omap2_init_reprogram_sdrc(void) | |
291 | { | |
292 | struct clk *dpll3_m2_ck; | |
293 | int v = -EINVAL; | |
294 | long rate; | |
295 | ||
296 | if (!cpu_is_omap34xx()) | |
297 | return 0; | |
298 | ||
299 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 300 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
301 | return -EINVAL; |
302 | ||
303 | rate = clk_get_rate(dpll3_m2_ck); | |
304 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
305 | v = clk_set_rate(dpll3_m2_ck, rate); | |
306 | if (v) | |
307 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
308 | ||
309 | clk_put(dpll3_m2_ck); | |
310 | ||
311 | return v; | |
312 | } | |
313 | ||
2092e5cc PW |
314 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
315 | { | |
316 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
317 | } | |
318 | ||
741e3a89 | 319 | /* See irq.c, omap4-common.c and entry-macro.S */ |
9f9605c2 RK |
320 | void __iomem *omap_irq_base; |
321 | ||
7b250aff | 322 | static void __init omap_common_init_early(void) |
120db2cb | 323 | { |
7b250aff | 324 | omap2_check_revision(); |
8aca3ab5 | 325 | omap_ioremap_init(); |
cfaf8fc5 | 326 | omap_init_consistent_dma_size(); |
7b250aff | 327 | } |
2092e5cc | 328 | |
7b250aff TL |
329 | static void __init omap_hwmod_init_postsetup(void) |
330 | { | |
331 | u8 postsetup_state; | |
2092e5cc PW |
332 | |
333 | /* Set the default postsetup state for all hwmods */ | |
334 | #ifdef CONFIG_PM_RUNTIME | |
335 | postsetup_state = _HWMOD_STATE_IDLE; | |
336 | #else | |
337 | postsetup_state = _HWMOD_STATE_ENABLED; | |
338 | #endif | |
339 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 340 | |
ff2516fb PW |
341 | /* |
342 | * Set the default postsetup state for unusual modules (like | |
343 | * MPU WDT). | |
344 | * | |
345 | * The postsetup_state is not actually used until | |
346 | * omap_hwmod_late_init(), so boards that desire full watchdog | |
347 | * coverage of kernel initialization can reprogram the | |
348 | * postsetup_state between the calls to | |
a4ca9dbe | 349 | * omap2_init_common_infra() and omap_sdrc_init(). |
ff2516fb PW |
350 | * |
351 | * XXX ideally we could detect whether the MPU WDT was currently | |
352 | * enabled here and make this conditional | |
353 | */ | |
354 | postsetup_state = _HWMOD_STATE_DISABLED; | |
355 | omap_hwmod_for_each_by_class("wd_timer", | |
356 | _set_hwmod_postsetup_state, | |
357 | &postsetup_state); | |
358 | ||
53da4ce2 | 359 | omap_pm_if_early_init(); |
4805734b PW |
360 | } |
361 | ||
8f5b5a41 TL |
362 | void __init omap2420_init_early(void) |
363 | { | |
4c3cf901 | 364 | omap2_set_globals_242x(); |
7b250aff TL |
365 | omap_common_init_early(); |
366 | omap2xxx_voltagedomains_init(); | |
367 | omap242x_powerdomains_init(); | |
368 | omap242x_clockdomains_init(); | |
369 | omap2420_hwmod_init(); | |
370 | omap_hwmod_init_postsetup(); | |
371 | omap2420_clk_init(); | |
8f5b5a41 TL |
372 | } |
373 | ||
374 | void __init omap2430_init_early(void) | |
375 | { | |
4c3cf901 | 376 | omap2_set_globals_243x(); |
7b250aff TL |
377 | omap_common_init_early(); |
378 | omap2xxx_voltagedomains_init(); | |
379 | omap243x_powerdomains_init(); | |
380 | omap243x_clockdomains_init(); | |
381 | omap2430_hwmod_init(); | |
382 | omap_hwmod_init_postsetup(); | |
383 | omap2430_clk_init(); | |
384 | } | |
385 | ||
386 | /* | |
387 | * Currently only board-omap3beagle.c should call this because of the | |
388 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
389 | */ | |
390 | void __init omap3_init_early(void) | |
391 | { | |
4c3cf901 | 392 | omap2_set_globals_3xxx(); |
7b250aff TL |
393 | omap_common_init_early(); |
394 | omap3xxx_voltagedomains_init(); | |
395 | omap3xxx_powerdomains_init(); | |
396 | omap3xxx_clockdomains_init(); | |
397 | omap3xxx_hwmod_init(); | |
398 | omap_hwmod_init_postsetup(); | |
399 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
400 | } |
401 | ||
402 | void __init omap3430_init_early(void) | |
403 | { | |
7b250aff | 404 | omap3_init_early(); |
8f5b5a41 TL |
405 | } |
406 | ||
407 | void __init omap35xx_init_early(void) | |
408 | { | |
7b250aff | 409 | omap3_init_early(); |
8f5b5a41 TL |
410 | } |
411 | ||
412 | void __init omap3630_init_early(void) | |
413 | { | |
7b250aff | 414 | omap3_init_early(); |
8f5b5a41 TL |
415 | } |
416 | ||
417 | void __init am35xx_init_early(void) | |
418 | { | |
7b250aff | 419 | omap3_init_early(); |
8f5b5a41 TL |
420 | } |
421 | ||
422 | void __init ti816x_init_early(void) | |
423 | { | |
4c3cf901 TL |
424 | omap2_set_globals_ti816x(); |
425 | omap_common_init_early(); | |
426 | omap3xxx_voltagedomains_init(); | |
427 | omap3xxx_powerdomains_init(); | |
428 | omap3xxx_clockdomains_init(); | |
429 | omap3xxx_hwmod_init(); | |
430 | omap_hwmod_init_postsetup(); | |
431 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
432 | } |
433 | ||
434 | void __init omap4430_init_early(void) | |
435 | { | |
4c3cf901 | 436 | omap2_set_globals_443x(); |
7b250aff TL |
437 | omap_common_init_early(); |
438 | omap44xx_voltagedomains_init(); | |
439 | omap44xx_powerdomains_init(); | |
440 | omap44xx_clockdomains_init(); | |
441 | omap44xx_hwmod_init(); | |
442 | omap_hwmod_init_postsetup(); | |
443 | omap4xxx_clk_init(); | |
8f5b5a41 TL |
444 | } |
445 | ||
a4ca9dbe | 446 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
447 | struct omap_sdrc_params *sdrc_cs1) |
448 | { | |
a66cb345 TL |
449 | omap_sram_init(); |
450 | ||
01001712 | 451 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
452 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
453 | _omap2_init_reprogram_sdrc(); | |
454 | } | |
1dbae815 | 455 | } |
df1e9d1c TL |
456 | |
457 | /* | |
458 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | |
459 | */ | |
460 | ||
461 | u8 omap_readb(u32 pa) | |
462 | { | |
463 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | |
464 | } | |
465 | EXPORT_SYMBOL(omap_readb); | |
466 | ||
467 | u16 omap_readw(u32 pa) | |
468 | { | |
469 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | |
470 | } | |
471 | EXPORT_SYMBOL(omap_readw); | |
472 | ||
473 | u32 omap_readl(u32 pa) | |
474 | { | |
475 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | |
476 | } | |
477 | EXPORT_SYMBOL(omap_readl); | |
478 | ||
479 | void omap_writeb(u8 v, u32 pa) | |
480 | { | |
481 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | |
482 | } | |
483 | EXPORT_SYMBOL(omap_writeb); | |
484 | ||
485 | void omap_writew(u16 v, u32 pa) | |
486 | { | |
487 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | |
488 | } | |
489 | EXPORT_SYMBOL(omap_writew); | |
490 | ||
491 | void omap_writel(u32 v, u32 pa) | |
492 | { | |
493 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | |
494 | } | |
495 | EXPORT_SYMBOL(omap_writel); |