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OMAP hwmod: convert header files with static allocations into C files
[linux-2.6-block.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
1dbae815
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
2f135eaf 24#include <linux/clk.h>
91773a00 25#include <linux/omapfb.h>
1dbae815 26
120db2cb 27#include <asm/tlb.h>
120db2cb
TL		 28
29#include <asm/mach/map.h>
30
ce491cf8 31#include <plat/mux.h>
ce491cf8
TL		 32#include <plat/sram.h>
33#include <plat/sdrc.h>
34#include <plat/gpmc.h>
35#include <plat/serial.h>
afedec18 36#include <plat/vram.h>
646e3ed1 37
e80a9729 38#include "clock2xxx.h"
657ebfad 39#include "clock3xxx.h"
e80a9729 40#include "clock44xx.h"
1dbae815 41
ce491cf8
TL		 42#include <plat/omap-pm.h>
43#include <plat/powerdomain.h>
9717100f 44#include "powerdomains.h"
1dbae815 45
ce491cf8 46#include <plat/clockdomain.h>
801954d3 47#include "clockdomains.h"
ce491cf8 48#include <plat/omap_hwmod.h>
02bfc030 49
1dbae815
TL		 50/*
51 * The machine specific code may provide the extra mapping besides the
52 * default mapping provided here.
53 */
cc26b3b0 54
088ef950 55#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 56static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 57 {
58 .virtual = L3_24XX_VIRT,
59 .pfn = __phys_to_pfn(L3_24XX_PHYS),
60 .length = L3_24XX_SIZE,
61 .type = MT_DEVICE
62 },
09f21ed4 63 {
cc26b3b0
SMK		 64 .virtual = L4_24XX_VIRT,
65 .pfn = __phys_to_pfn(L4_24XX_PHYS),
66 .length = L4_24XX_SIZE,
67 .type = MT_DEVICE
09f21ed4 68 },
cc26b3b0
SMK		 69};
70
71#ifdef CONFIG_ARCH_OMAP2420
72static struct map_desc omap242x_io_desc[] __initdata = {
73 {
7adb9987
PW		 74 .virtual = DSP_MEM_2420_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
76 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 77 .type = MT_DEVICE
78 },
79 {
7adb9987
PW		 80 .virtual = DSP_IPI_2420_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
82 .length = DSP_IPI_2420_SIZE,
cc26b3b0 83 .type = MT_DEVICE
09f21ed4 84 },
cc26b3b0 85 {
7adb9987
PW		 86 .virtual = DSP_MMU_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
88 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 89 .type = MT_DEVICE
90 },
91};
92
93#endif
94
72d0f1c3 95#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0 96static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 97 {
98 .virtual = L4_WK_243X_VIRT,
99 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
100 .length = L4_WK_243X_SIZE,
101 .type = MT_DEVICE
102 },
103 {
104 .virtual = OMAP243X_GPMC_VIRT,
105 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
106 .length = OMAP243X_GPMC_SIZE,
107 .type = MT_DEVICE
108 },
cc26b3b0
SMK		 109 {
110 .virtual = OMAP243X_SDRC_VIRT,
111 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
112 .length = OMAP243X_SDRC_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_SMS_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
118 .length = OMAP243X_SMS_SIZE,
119 .type = MT_DEVICE
120 },
121};
72d0f1c3 122#endif
72d0f1c3 123#endif
cc26b3b0 124
a8eb7ca0 125#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 126static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 127 {
cc26b3b0
SMK		 128 .virtual = L3_34XX_VIRT,
129 .pfn = __phys_to_pfn(L3_34XX_PHYS),
130 .length = L3_34XX_SIZE,
c40fae95
TL		 131 .type = MT_DEVICE
132 },
133 {
cc26b3b0
SMK		 134 .virtual = L4_34XX_VIRT,
135 .pfn = __phys_to_pfn(L4_34XX_PHYS),
136 .length = L4_34XX_SIZE,
c40fae95
TL		 137 .type = MT_DEVICE
138 },
139 {
cc26b3b0
SMK		 140 .virtual = L4_WK_34XX_VIRT,
141 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
142 .length = L4_WK_34XX_SIZE,
143 .type = MT_DEVICE
144 },
145 {
146 .virtual = OMAP34XX_GPMC_VIRT,
147 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
148 .length = OMAP34XX_GPMC_SIZE,
1dbae815 149 .type = MT_DEVICE
cc26b3b0
SMK		 150 },
151 {
152 .virtual = OMAP343X_SMS_VIRT,
153 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
154 .length = OMAP343X_SMS_SIZE,
155 .type = MT_DEVICE
156 },
157 {
158 .virtual = OMAP343X_SDRC_VIRT,
159 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
160 .length = OMAP343X_SDRC_SIZE,
1dbae815 161 .type = MT_DEVICE
cc26b3b0
SMK		 162 },
163 {
164 .virtual = L4_PER_34XX_VIRT,
165 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
166 .length = L4_PER_34XX_SIZE,
167 .type = MT_DEVICE
168 },
169 {
170 .virtual = L4_EMU_34XX_VIRT,
171 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
172 .length = L4_EMU_34XX_SIZE,
173 .type = MT_DEVICE
174 },
1dbae815 175};
cc26b3b0 176#endif
44169075
SS		 177#ifdef CONFIG_ARCH_OMAP4
178static struct map_desc omap44xx_io_desc[] __initdata = {
179 {
180 .virtual = L3_44XX_VIRT,
181 .pfn = __phys_to_pfn(L3_44XX_PHYS),
182 .length = L3_44XX_SIZE,
183 .type = MT_DEVICE,
184 },
185 {
186 .virtual = L4_44XX_VIRT,
187 .pfn = __phys_to_pfn(L4_44XX_PHYS),
188 .length = L4_44XX_SIZE,
189 .type = MT_DEVICE,
190 },
191 {
192 .virtual = L4_WK_44XX_VIRT,
193 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
194 .length = L4_WK_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = OMAP44XX_GPMC_VIRT,
199 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
200 .length = OMAP44XX_GPMC_SIZE,
201 .type = MT_DEVICE,
202 },
f5d2d659
SS		 203 {
204 .virtual = OMAP44XX_EMIF1_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
206 .length = OMAP44XX_EMIF1_SIZE,
207 .type = MT_DEVICE,
208 },
209 {
210 .virtual = OMAP44XX_EMIF2_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
212 .length = OMAP44XX_EMIF2_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_DMM_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
218 .length = OMAP44XX_DMM_SIZE,
219 .type = MT_DEVICE,
220 },
44169075
SS		 221 {
222 .virtual = L4_PER_44XX_VIRT,
223 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
224 .length = L4_PER_44XX_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_EMU_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
230 .length = L4_EMU_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233};
234#endif
1dbae815 235
6fbd55d0
TL		 236static void __init _omap2_map_common_io(void)
237{
238 /* Normally devicemaps_init() would flush caches and tlb after
239 * mdesc->map_io(), but we must also do it here because of the CPU
240 * revision check below.
241 */
242 local_flush_tlb_all();
243 flush_cache_all();
244
245 omap2_check_revision();
246 omap_sram_init();
247 omapfb_reserve_sdram();
248 omap_vram_reserve_sdram();
249}
250
251#ifdef CONFIG_ARCH_OMAP2420
252void __init omap242x_map_common_io()
1dbae815 253{
cc26b3b0
SMK		 254 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
255 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0
TL		 256 _omap2_map_common_io();
257}
cc26b3b0
SMK		 258#endif
259
6fbd55d0
TL		 260#ifdef CONFIG_ARCH_OMAP2430
261void __init omap243x_map_common_io()
262{
cc26b3b0
SMK		 263 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
264 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0
TL		 265 _omap2_map_common_io();
266}
cc26b3b0
SMK		 267#endif
268
a8eb7ca0 269#ifdef CONFIG_ARCH_OMAP3
6fbd55d0
TL		 270void __init omap34xx_map_common_io()
271{
cc26b3b0 272 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0
TL		 273 _omap2_map_common_io();
274}
cc26b3b0 275#endif
120db2cb 276
6fbd55d0
TL		 277#ifdef CONFIG_ARCH_OMAP4
278void __init omap44xx_map_common_io()
279{
44169075 280 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
6fbd55d0 281 _omap2_map_common_io();
120db2cb 282}
6fbd55d0 283#endif
120db2cb 284
2f135eaf
PW		 285/*
286 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
287 *
288 * Sets the CORE DPLL3 M2 divider to the same value that it's at
289 * currently. This has the effect of setting the SDRC SDRAM AC timing
290 * registers to the values currently defined by the kernel. Currently
291 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
292 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
293 * or passes along the return value of clk_set_rate().
294 */
295static int __init _omap2_init_reprogram_sdrc(void)
296{
297 struct clk *dpll3_m2_ck;
298 int v = -EINVAL;
299 long rate;
300
301 if (!cpu_is_omap34xx())
302 return 0;
303
304 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
305 if (!dpll3_m2_ck)
306 return -EINVAL;
307
308 rate = clk_get_rate(dpll3_m2_ck);
309 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
310 v = clk_set_rate(dpll3_m2_ck, rate);
311 if (v)
312 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
313
314 clk_put(dpll3_m2_ck);
315
316 return v;
317}
318
58cda884
JP		 319void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
320 struct omap_sdrc_params *sdrc_cs1)
120db2cb 321{
3a759f09 322 pwrdm_init(powerdomains_omap);
55ed9694 323 clkdm_init(clockdomains_omap, clkdm_autodeps);
44169075 324#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
7359154e
PW		 325 if (cpu_is_omap242x())
326 omap2420_hwmod_init();
327 else if (cpu_is_omap243x())
328 omap2430_hwmod_init();
329 else if (cpu_is_omap34xx())
330 omap3xxx_hwmod_init();
61f04ee8 331 omap2_mux_init();
7359154e 332 /* The OPP tables have to be registered before a clk init */
c0407a96 333 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
5b7815b5 334#endif
e80a9729 335
81b34fbe
PW		 336 if (cpu_is_omap2420())
337 omap2420_clk_init();
338 else if (cpu_is_omap2430())
339 omap2430_clk_init();
e80a9729
PW		 340 else if (cpu_is_omap34xx())
341 omap3xxx_clk_init();
342 else if (cpu_is_omap44xx())
343 omap4xxx_clk_init();
344 else
345 pr_err("Could not init clock framework - unknown CPU\n");
346
b3c6df3a 347 omap_serial_early_init();
5b7815b5 348#ifndef CONFIG_ARCH_OMAP4
02bfc030 349 omap_hwmod_late_init();
c0407a96 350 omap_pm_if_init();
58cda884 351 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
2f135eaf 352 _omap2_init_reprogram_sdrc();
44169075 353#endif
4bbbc1ad 354 gpmc_init();
1dbae815 355}
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