Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
ce491cf8 | 24 | #include <plat/common.h> |
ce491cf8 | 25 | #include <plat/cpu.h> |
72d0f1c3 | 26 | |
2e130fc3 KRC |
27 | #include <mach/id.h> |
28 | ||
4814ced5 PW |
29 | #include "control.h" |
30 | ||
097c584c | 31 | static struct omap_chip_id omap_chip; |
84a34344 LL |
32 | static unsigned int omap_revision; |
33 | ||
8384ce07 | 34 | u32 omap3_features; |
84a34344 LL |
35 | |
36 | unsigned int omap_rev(void) | |
37 | { | |
38 | return omap_revision; | |
39 | } | |
40 | EXPORT_SYMBOL(omap_rev); | |
097c584c PW |
41 | |
42 | /** | |
43 | * omap_chip_is - test whether currently running OMAP matches a chip type | |
44 | * @oc: omap_chip_t to test against | |
45 | * | |
46 | * Test whether the currently-running OMAP chip matches the supplied | |
47 | * chip type 'oc'. Returns 1 upon a match; 0 upon failure. | |
48 | */ | |
49 | int omap_chip_is(struct omap_chip_id oci) | |
50 | { | |
51 | return (oci.oc & omap_chip.oc) ? 1 : 0; | |
52 | } | |
53 | EXPORT_SYMBOL(omap_chip_is); | |
54 | ||
8e25ad96 KH |
55 | int omap_type(void) |
56 | { | |
57 | u32 val = 0; | |
58 | ||
edeae658 | 59 | if (cpu_is_omap24xx()) { |
8e25ad96 | 60 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
edeae658 | 61 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 62 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 63 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 64 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
edeae658 | 65 | } else { |
8e25ad96 KH |
66 | pr_err("Cannot detect omap type!\n"); |
67 | goto out; | |
68 | } | |
69 | ||
70 | val &= OMAP2_DEVICETYPE_MASK; | |
71 | val >>= 8; | |
72 | ||
73 | out: | |
74 | return val; | |
75 | } | |
76 | EXPORT_SYMBOL(omap_type); | |
77 | ||
78 | ||
a8823143 | 79 | /*----------------------------------------------------------------------------*/ |
097c584c | 80 | |
a8823143 TL |
81 | #define OMAP_TAP_IDCODE 0x0204 |
82 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
83 | #define OMAP_TAP_DIE_ID_1 0x021C | |
84 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
85 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 86 | |
b235e007 AG |
87 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
88 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
89 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
90 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
91 | ||
a8823143 | 92 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 93 | |
a8823143 TL |
94 | struct omap_id { |
95 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
96 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 97 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 98 | }; |
097c584c | 99 | |
a8823143 TL |
100 | /* Register values to detect the OMAP version */ |
101 | static struct omap_id omap_ids[] __initdata = { | |
102 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
103 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
104 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
105 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
106 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
107 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
108 | }; | |
097c584c | 109 | |
a8823143 TL |
110 | static void __iomem *tap_base; |
111 | static u16 tap_prod_id; | |
1dbae815 | 112 | |
2e130fc3 KRC |
113 | void omap_get_die_id(struct omap_die_id *odi) |
114 | { | |
b235e007 AG |
115 | if (cpu_is_omap44xx()) { |
116 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); | |
117 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
118 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
119 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
120 | ||
121 | return; | |
122 | } | |
2e130fc3 KRC |
123 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
124 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
125 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
126 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
127 | } | |
128 | ||
5ebc0d52 | 129 | static void __init omap24xx_check_revision(void) |
1dbae815 TL |
130 | { |
131 | int i, j; | |
a8823143 | 132 | u32 idcode, prod_id; |
1dbae815 | 133 | u16 hawkeye; |
a8823143 | 134 | u8 dev_type, rev; |
c46732bb | 135 | struct omap_die_id odi; |
1dbae815 TL |
136 | |
137 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 138 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
139 | hawkeye = (idcode >> 12) & 0xffff; |
140 | rev = (idcode >> 28) & 0x0f; | |
141 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 142 | omap_get_die_id(&odi); |
1dbae815 | 143 | |
097c584c PW |
144 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
145 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 146 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 147 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
148 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
149 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
150 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
151 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
152 | prod_id, dev_type); | |
153 | ||
1dbae815 TL |
154 | /* Check hawkeye ids */ |
155 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
156 | if (hawkeye == omap_ids[i].hawkeye) | |
157 | break; | |
158 | } | |
159 | ||
160 | if (i == ARRAY_SIZE(omap_ids)) { | |
161 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
162 | return; | |
163 | } | |
164 | ||
165 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
166 | if (dev_type == omap_ids[j].dev) | |
167 | break; | |
168 | } | |
169 | ||
170 | if (j == ARRAY_SIZE(omap_ids)) { | |
171 | printk(KERN_ERR "Unknown OMAP device type. " | |
172 | "Handling it as OMAP%04x\n", | |
173 | omap_ids[i].type >> 16); | |
174 | j = i; | |
175 | } | |
1dbae815 | 176 | |
84a34344 LL |
177 | pr_info("OMAP%04x", omap_rev() >> 16); |
178 | if ((omap_rev() >> 8) & 0x0f) | |
179 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 180 | pr_info("\n"); |
a8823143 TL |
181 | } |
182 | ||
8384ce07 SP |
183 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
184 | if (((status & OMAP3_ ##feat## _MASK) \ | |
185 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
186 | omap3_features |= OMAP3_HAS_ ##feat; \ | |
187 | } | |
188 | ||
5ebc0d52 | 189 | static void __init omap3_check_features(void) |
8384ce07 SP |
190 | { |
191 | u32 status; | |
192 | ||
193 | omap3_features = 0; | |
194 | ||
195 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
196 | ||
197 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
198 | OMAP3_CHECK_FEATURE(status, IVA); | |
199 | OMAP3_CHECK_FEATURE(status, SGX); | |
200 | OMAP3_CHECK_FEATURE(status, NEON); | |
201 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 VB |
202 | if (cpu_is_omap3630()) |
203 | omap3_features |= OMAP3_HAS_192MHZ_CLK; | |
ad0c63f1 | 204 | if (!cpu_is_omap3505() && !cpu_is_omap3517()) |
205 | omap3_features |= OMAP3_HAS_IO_WAKEUP; | |
8384ce07 | 206 | |
01001712 HP |
207 | omap3_features |= OMAP3_HAS_SDRC; |
208 | ||
8384ce07 SP |
209 | /* |
210 | * TODO: Get additional info (where applicable) | |
211 | * e.g. Size of L2 cache. | |
212 | */ | |
213 | } | |
214 | ||
01001712 HP |
215 | static void __init ti816x_check_features(void) |
216 | { | |
217 | omap3_features = OMAP3_HAS_NEON; | |
218 | } | |
219 | ||
5ebc0d52 | 220 | static void __init omap3_check_revision(void) |
a8823143 TL |
221 | { |
222 | u32 cpuid, idcode; | |
223 | u16 hawkeye; | |
224 | u8 rev; | |
a8823143 | 225 | |
e9acb9b6 TL |
226 | omap_chip.oc = CHIP_IS_OMAP3430; |
227 | ||
a8823143 TL |
228 | /* |
229 | * We cannot access revision registers on ES1.0. | |
230 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
231 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
232 | */ | |
233 | cpuid = read_cpuid(CPUID_ID); | |
234 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 235 | omap_revision = OMAP3430_REV_ES1_0; |
e9acb9b6 | 236 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; |
048f4bd7 | 237 | return; |
a8823143 TL |
238 | } |
239 | ||
240 | /* | |
241 | * Detection for 34xx ES2.0 and above can be done with just | |
242 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
243 | * Note that rev does not map directly to our defined processor | |
244 | * revision numbers as ES1.0 uses value 0. | |
245 | */ | |
246 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
247 | hawkeye = (idcode >> 12) & 0xffff; | |
248 | rev = (idcode >> 28) & 0xff; | |
097c584c | 249 | |
2456a10f NM |
250 | switch (hawkeye) { |
251 | case 0xb7ae: | |
252 | /* Handle 34xx/35xx devices */ | |
a8823143 | 253 | switch (rev) { |
048f4bd7 SP |
254 | case 0: /* Take care of early samples */ |
255 | case 1: | |
84a34344 | 256 | omap_revision = OMAP3430_REV_ES2_0; |
e9acb9b6 | 257 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
a8823143 TL |
258 | break; |
259 | case 2: | |
84a34344 | 260 | omap_revision = OMAP3430_REV_ES2_1; |
e9acb9b6 | 261 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
a8823143 TL |
262 | break; |
263 | case 3: | |
84a34344 | 264 | omap_revision = OMAP3430_REV_ES3_0; |
e9acb9b6 | 265 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; |
a8823143 | 266 | break; |
187e688d | 267 | case 4: |
e9acb9b6 TL |
268 | omap_revision = OMAP3430_REV_ES3_1; |
269 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | |
270 | break; | |
271 | case 7: | |
edeae658 | 272 | /* FALLTHROUGH */ |
a8823143 TL |
273 | default: |
274 | /* Use the latest known revision as default */ | |
e9acb9b6 TL |
275 | omap_revision = OMAP3430_REV_ES3_1_2; |
276 | ||
277 | /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ | |
278 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | |
a8823143 | 279 | } |
2456a10f | 280 | break; |
4cac6018 SP |
281 | case 0xb868: |
282 | /* Handle OMAP35xx/AM35xx devices | |
283 | * | |
284 | * Set the device to be OMAP3505 here. Actual device | |
285 | * is identified later based on the features. | |
e9acb9b6 TL |
286 | * |
287 | * REVISIT: AM3505/AM3517 should have their own CHIP_IS | |
4cac6018 SP |
288 | */ |
289 | omap_revision = OMAP3505_REV(rev); | |
e9acb9b6 | 290 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; |
4cac6018 | 291 | break; |
edeae658 | 292 | case 0xb891: |
b0a1a6ce AG |
293 | /* Handle 36xx devices */ |
294 | omap_chip.oc |= CHIP_IS_OMAP3630ES1; | |
295 | ||
296 | switch(rev) { | |
297 | case 0: /* Take care of early samples */ | |
298 | omap_revision = OMAP3630_REV_ES1_0; | |
299 | break; | |
300 | case 1: | |
301 | omap_revision = OMAP3630_REV_ES1_1; | |
302 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; | |
303 | break; | |
304 | case 2: | |
305 | default: | |
306 | omap_revision = OMAP3630_REV_ES1_2; | |
307 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; | |
b0a1a6ce | 308 | } |
77c0870c | 309 | break; |
01001712 HP |
310 | case 0xb81e: |
311 | omap_chip.oc = CHIP_IS_TI816X; | |
312 | ||
313 | switch (rev) { | |
314 | case 0: | |
315 | omap_revision = TI8168_REV_ES1_0; | |
316 | break; | |
317 | case 1: | |
318 | omap_revision = TI8168_REV_ES1_1; | |
319 | break; | |
320 | default: | |
321 | omap_revision = TI8168_REV_ES1_1; | |
322 | } | |
323 | break; | |
2456a10f NM |
324 | default: |
325 | /* Unknown default to latest silicon rev as default*/ | |
b0a1a6ce AG |
326 | omap_revision = OMAP3630_REV_ES1_2; |
327 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; | |
a8823143 | 328 | } |
1dbae815 TL |
329 | } |
330 | ||
5ebc0d52 | 331 | static void __init omap4_check_revision(void) |
b570e0ec SS |
332 | { |
333 | u32 idcode; | |
334 | u16 hawkeye; | |
335 | u8 rev; | |
b570e0ec SS |
336 | |
337 | /* | |
338 | * The IC rev detection is done with hawkeye and rev. | |
339 | * Note that rev does not map directly to defined processor | |
340 | * revision numbers as ES1.0 uses value 0. | |
341 | */ | |
342 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
343 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 344 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 345 | |
ed6be0ba | 346 | /* |
fa54dccd | 347 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
348 | * Use ARM register to detect the correct ES version |
349 | */ | |
fa54dccd | 350 | if (!rev && (hawkeye != 0xb94e)) { |
ed6be0ba SS |
351 | idcode = read_cpuid(CPUID_ID); |
352 | rev = (idcode & 0xf) - 1; | |
353 | } | |
354 | ||
355 | switch (hawkeye) { | |
356 | case 0xb852: | |
357 | switch (rev) { | |
358 | case 0: | |
359 | omap_revision = OMAP4430_REV_ES1_0; | |
360 | omap_chip.oc |= CHIP_IS_OMAP4430ES1; | |
361 | break; | |
362 | case 1: | |
e49c4d27 | 363 | default: |
ed6be0ba SS |
364 | omap_revision = OMAP4430_REV_ES2_0; |
365 | omap_chip.oc |= CHIP_IS_OMAP4430ES2; | |
e49c4d27 NK |
366 | } |
367 | break; | |
368 | case 0xb95c: | |
369 | switch (rev) { | |
370 | case 3: | |
371 | omap_revision = OMAP4430_REV_ES2_1; | |
372 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; | |
ed6be0ba | 373 | break; |
e49c4d27 | 374 | case 4: |
ed6be0ba | 375 | default: |
e49c4d27 NK |
376 | omap_revision = OMAP4430_REV_ES2_2; |
377 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; | |
378 | } | |
379 | break; | |
fa54dccd A |
380 | case 0xb94e: |
381 | switch (rev) { | |
382 | case 0: | |
383 | default: | |
384 | omap_revision = OMAP4460_REV_ES1_0; | |
385 | omap_chip.oc |= CHIP_IS_OMAP4460ES1_0; | |
386 | break; | |
387 | } | |
388 | break; | |
ed6be0ba | 389 | default: |
e49c4d27 NK |
390 | /* Unknown default to latest silicon rev as default */ |
391 | omap_revision = OMAP4430_REV_ES2_2; | |
392 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; | |
b570e0ec SS |
393 | } |
394 | ||
e49c4d27 NK |
395 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
396 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
397 | } |
398 | ||
8384ce07 | 399 | #define OMAP3_SHOW_FEATURE(feat) \ |
cedf900d KH |
400 | if (omap3_has_ ##feat()) \ |
401 | printk(#feat" "); | |
8384ce07 | 402 | |
5ebc0d52 | 403 | static void __init omap3_cpuinfo(void) |
8384ce07 | 404 | { |
048f4bd7 SP |
405 | u8 rev = GET_OMAP_REVISION(); |
406 | char cpu_name[16], cpu_rev[16]; | |
407 | ||
408 | /* OMAP3430 and OMAP3530 are assumed to be same. | |
409 | * | |
410 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
411 | * on available features. Upon detection, update the CPU id | |
412 | * and CPU class bits. | |
413 | */ | |
edeae658 | 414 | if (cpu_is_omap3630()) { |
4cac6018 | 415 | strcpy(cpu_name, "OMAP3630"); |
edeae658 | 416 | } else if (cpu_is_omap3505()) { |
4cac6018 SP |
417 | /* |
418 | * AM35xx devices | |
419 | */ | |
420 | if (omap3_has_sgx()) { | |
421 | omap_revision = OMAP3517_REV(rev); | |
422 | strcpy(cpu_name, "AM3517"); | |
edeae658 | 423 | } else { |
4cac6018 SP |
424 | /* Already set in omap3_check_revision() */ |
425 | strcpy(cpu_name, "AM3505"); | |
426 | } | |
01001712 HP |
427 | } else if (cpu_is_ti816x()) { |
428 | strcpy(cpu_name, "TI816X"); | |
edeae658 FB |
429 | } else if (omap3_has_iva() && omap3_has_sgx()) { |
430 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
4cac6018 | 431 | strcpy(cpu_name, "OMAP3430/3530"); |
0712fb39 | 432 | } else if (omap3_has_iva()) { |
048f4bd7 | 433 | omap_revision = OMAP3525_REV(rev); |
4cac6018 | 434 | strcpy(cpu_name, "OMAP3525"); |
0712fb39 | 435 | } else if (omap3_has_sgx()) { |
048f4bd7 | 436 | omap_revision = OMAP3515_REV(rev); |
4cac6018 | 437 | strcpy(cpu_name, "OMAP3515"); |
edeae658 | 438 | } else { |
048f4bd7 | 439 | omap_revision = OMAP3503_REV(rev); |
4cac6018 | 440 | strcpy(cpu_name, "OMAP3503"); |
048f4bd7 SP |
441 | } |
442 | ||
01001712 | 443 | if (cpu_is_omap3630() || cpu_is_ti816x()) { |
76abab21 SP |
444 | switch (rev) { |
445 | case OMAP_REVBITS_00: | |
446 | strcpy(cpu_rev, "1.0"); | |
447 | break; | |
448 | case OMAP_REVBITS_01: | |
449 | strcpy(cpu_rev, "1.1"); | |
450 | break; | |
451 | case OMAP_REVBITS_02: | |
452 | /* FALLTHROUGH */ | |
453 | default: | |
454 | /* Use the latest known revision as default */ | |
455 | strcpy(cpu_rev, "1.2"); | |
456 | } | |
457 | } else if (cpu_is_omap3505() || cpu_is_omap3517()) { | |
458 | switch (rev) { | |
459 | case OMAP_REVBITS_00: | |
460 | strcpy(cpu_rev, "1.0"); | |
461 | break; | |
462 | case OMAP_REVBITS_01: | |
463 | /* FALLTHROUGH */ | |
464 | default: | |
465 | /* Use the latest known revision as default */ | |
466 | strcpy(cpu_rev, "1.1"); | |
467 | } | |
468 | } else { | |
469 | switch (rev) { | |
470 | case OMAP_REVBITS_00: | |
471 | strcpy(cpu_rev, "1.0"); | |
472 | break; | |
473 | case OMAP_REVBITS_01: | |
474 | strcpy(cpu_rev, "2.0"); | |
475 | break; | |
476 | case OMAP_REVBITS_02: | |
477 | strcpy(cpu_rev, "2.1"); | |
478 | break; | |
479 | case OMAP_REVBITS_03: | |
480 | strcpy(cpu_rev, "3.0"); | |
481 | break; | |
482 | case OMAP_REVBITS_04: | |
483 | strcpy(cpu_rev, "3.1"); | |
484 | break; | |
485 | case OMAP_REVBITS_05: | |
486 | /* FALLTHROUGH */ | |
487 | default: | |
488 | /* Use the latest known revision as default */ | |
489 | strcpy(cpu_rev, "3.1.2"); | |
490 | } | |
048f4bd7 SP |
491 | } |
492 | ||
edeae658 | 493 | /* Print verbose information */ |
cedf900d | 494 | pr_info("%s ES%s (", cpu_name, cpu_rev); |
048f4bd7 | 495 | |
8384ce07 SP |
496 | OMAP3_SHOW_FEATURE(l2cache); |
497 | OMAP3_SHOW_FEATURE(iva); | |
498 | OMAP3_SHOW_FEATURE(sgx); | |
499 | OMAP3_SHOW_FEATURE(neon); | |
500 | OMAP3_SHOW_FEATURE(isp); | |
7356f0b2 | 501 | OMAP3_SHOW_FEATURE(192mhz_clk); |
cedf900d KH |
502 | |
503 | printk(")\n"); | |
8384ce07 SP |
504 | } |
505 | ||
a8823143 TL |
506 | /* |
507 | * Try to detect the exact revision of the omap we're running on | |
508 | */ | |
5ba02dca TL |
509 | void __init omap2_check_revision(void) |
510 | { | |
a8823143 TL |
511 | /* |
512 | * At this point we have an idea about the processor revision set | |
513 | * earlier with omap2_set_globals_tap(). | |
514 | */ | |
edeae658 | 515 | if (cpu_is_omap24xx()) { |
a8823143 | 516 | omap24xx_check_revision(); |
edeae658 | 517 | } else if (cpu_is_omap34xx()) { |
8384ce07 | 518 | omap3_check_revision(); |
01001712 HP |
519 | |
520 | /* TI816X doesn't have feature register */ | |
521 | if (!cpu_is_ti816x()) | |
522 | omap3_check_features(); | |
523 | else | |
524 | ti816x_check_features(); | |
525 | ||
8384ce07 | 526 | omap3_cpuinfo(); |
e9acb9b6 | 527 | return; |
edeae658 | 528 | } else if (cpu_is_omap44xx()) { |
b570e0ec | 529 | omap4_check_revision(); |
44169075 | 530 | return; |
edeae658 | 531 | } else { |
a8823143 | 532 | pr_err("OMAP revision unknown, please fix!\n"); |
edeae658 | 533 | } |
a8823143 TL |
534 | |
535 | /* | |
536 | * OK, now we know the exact revision. Initialize omap_chip bits | |
537 | * for powerdowmain and clockdomain code. | |
538 | */ | |
539 | if (cpu_is_omap243x()) { | |
540 | /* Currently only supports 2430ES2.1 and 2430-all */ | |
541 | omap_chip.oc |= CHIP_IS_OMAP2430; | |
e9acb9b6 | 542 | return; |
a8823143 TL |
543 | } else if (cpu_is_omap242x()) { |
544 | /* Currently only supports 2420ES2.1.1 and 2420-all */ | |
545 | omap_chip.oc |= CHIP_IS_OMAP2420; | |
e9acb9b6 | 546 | return; |
a8823143 | 547 | } |
e9acb9b6 TL |
548 | |
549 | pr_err("Uninitialized omap_chip, please fix!\n"); | |
5ba02dca TL |
550 | } |
551 | ||
a8823143 TL |
552 | /* |
553 | * Set up things for map_io and processor detection later on. Gets called | |
554 | * pretty much first thing from board init. For multi-omap, this gets | |
555 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
556 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
557 | * is done. | |
558 | */ | |
0e564848 TL |
559 | void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) |
560 | { | |
84a34344 | 561 | omap_revision = omap2_globals->class; |
0e564848 TL |
562 | tap_base = omap2_globals->tap; |
563 | ||
a8823143 | 564 | if (cpu_is_omap34xx()) |
0e564848 TL |
565 | tap_prod_id = 0x0210; |
566 | else | |
567 | tap_prod_id = 0x0208; | |
568 | } |