Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
4e65331c | 24 | #include "common.h" |
72d0f1c3 | 25 | |
4952af43 | 26 | #include "id.h" |
2e130fc3 | 27 | |
dbc04161 | 28 | #include "soc.h" |
4814ced5 PW |
29 | #include "control.h" |
30 | ||
42a1cc9c IK |
31 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
32 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | |
33 | ||
84a34344 | 34 | static unsigned int omap_revision; |
50a01e64 | 35 | static const char *cpu_rev; |
cc0170b2 | 36 | u32 omap_features; |
84a34344 LL |
37 | |
38 | unsigned int omap_rev(void) | |
39 | { | |
40 | return omap_revision; | |
41 | } | |
42 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 43 | |
8e25ad96 KH |
44 | int omap_type(void) |
45 | { | |
46 | u32 val = 0; | |
47 | ||
edeae658 | 48 | if (cpu_is_omap24xx()) { |
8e25ad96 | 49 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
971b8a9c | 50 | } else if (soc_is_am33xx()) { |
fb3cfb1f | 51 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
edeae658 | 52 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 53 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 54 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 55 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
b13e80a8 S |
56 | } else if (soc_is_omap54xx()) { |
57 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); | |
58 | val &= OMAP5_DEVICETYPE_MASK; | |
59 | val >>= 6; | |
60 | goto out; | |
edeae658 | 61 | } else { |
8e25ad96 KH |
62 | pr_err("Cannot detect omap type!\n"); |
63 | goto out; | |
64 | } | |
65 | ||
66 | val &= OMAP2_DEVICETYPE_MASK; | |
67 | val >>= 8; | |
68 | ||
69 | out: | |
70 | return val; | |
71 | } | |
72 | EXPORT_SYMBOL(omap_type); | |
73 | ||
74 | ||
a8823143 | 75 | /*----------------------------------------------------------------------------*/ |
097c584c | 76 | |
a8823143 TL |
77 | #define OMAP_TAP_IDCODE 0x0204 |
78 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
79 | #define OMAP_TAP_DIE_ID_1 0x021C | |
80 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
81 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 82 | |
b235e007 AG |
83 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
84 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
85 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
86 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
87 | ||
a8823143 | 88 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 89 | |
a8823143 TL |
90 | struct omap_id { |
91 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
92 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 93 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 94 | }; |
097c584c | 95 | |
a8823143 TL |
96 | /* Register values to detect the OMAP version */ |
97 | static struct omap_id omap_ids[] __initdata = { | |
98 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
99 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
100 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
101 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
102 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
103 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
104 | }; | |
097c584c | 105 | |
a8823143 TL |
106 | static void __iomem *tap_base; |
107 | static u16 tap_prod_id; | |
1dbae815 | 108 | |
2e130fc3 KRC |
109 | void omap_get_die_id(struct omap_die_id *odi) |
110 | { | |
b13e80a8 | 111 | if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
b235e007 AG |
112 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
113 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
114 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
115 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
116 | ||
117 | return; | |
118 | } | |
2e130fc3 KRC |
119 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
120 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
121 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
122 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
123 | } | |
124 | ||
4de34f35 | 125 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
126 | { |
127 | int i, j; | |
a8823143 | 128 | u32 idcode, prod_id; |
1dbae815 | 129 | u16 hawkeye; |
a8823143 | 130 | u8 dev_type, rev; |
c46732bb | 131 | struct omap_die_id odi; |
1dbae815 TL |
132 | |
133 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 134 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
135 | hawkeye = (idcode >> 12) & 0xffff; |
136 | rev = (idcode >> 28) & 0x0f; | |
137 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 138 | omap_get_die_id(&odi); |
1dbae815 | 139 | |
097c584c PW |
140 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
141 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 142 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 143 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
144 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
145 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
146 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
147 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
148 | prod_id, dev_type); | |
149 | ||
1dbae815 TL |
150 | /* Check hawkeye ids */ |
151 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
152 | if (hawkeye == omap_ids[i].hawkeye) | |
153 | break; | |
154 | } | |
155 | ||
156 | if (i == ARRAY_SIZE(omap_ids)) { | |
157 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
158 | return; | |
159 | } | |
160 | ||
161 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
162 | if (dev_type == omap_ids[j].dev) | |
163 | break; | |
164 | } | |
165 | ||
166 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
167 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
168 | omap_ids[i].type >> 16); | |
1dbae815 TL |
169 | j = i; |
170 | } | |
1dbae815 | 171 | |
84a34344 LL |
172 | pr_info("OMAP%04x", omap_rev() >> 16); |
173 | if ((omap_rev() >> 8) & 0x0f) | |
174 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 175 | pr_info("\n"); |
a8823143 TL |
176 | } |
177 | ||
50a01e64 VH |
178 | #define OMAP3_SHOW_FEATURE(feat) \ |
179 | if (omap3_has_ ##feat()) \ | |
180 | printk(#feat" "); | |
181 | ||
182 | static void __init omap3_cpuinfo(void) | |
183 | { | |
184 | const char *cpu_name; | |
185 | ||
186 | /* | |
187 | * OMAP3430 and OMAP3530 are assumed to be same. | |
188 | * | |
189 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
190 | * on available features. Upon detection, update the CPU id | |
191 | * and CPU class bits. | |
192 | */ | |
193 | if (cpu_is_omap3630()) { | |
194 | cpu_name = "OMAP3630"; | |
68a88b98 | 195 | } else if (soc_is_am35xx()) { |
50a01e64 VH |
196 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
197 | } else if (cpu_is_ti816x()) { | |
198 | cpu_name = "TI816X"; | |
971b8a9c | 199 | } else if (soc_is_am335x()) { |
50a01e64 VH |
200 | cpu_name = "AM335X"; |
201 | } else if (cpu_is_ti814x()) { | |
202 | cpu_name = "TI814X"; | |
203 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
204 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
205 | cpu_name = "OMAP3430/3530"; | |
206 | } else if (omap3_has_iva()) { | |
207 | cpu_name = "OMAP3525"; | |
208 | } else if (omap3_has_sgx()) { | |
209 | cpu_name = "OMAP3515"; | |
210 | } else { | |
211 | cpu_name = "OMAP3503"; | |
212 | } | |
213 | ||
214 | /* Print verbose information */ | |
215 | pr_info("%s ES%s (", cpu_name, cpu_rev); | |
216 | ||
217 | OMAP3_SHOW_FEATURE(l2cache); | |
218 | OMAP3_SHOW_FEATURE(iva); | |
219 | OMAP3_SHOW_FEATURE(sgx); | |
220 | OMAP3_SHOW_FEATURE(neon); | |
221 | OMAP3_SHOW_FEATURE(isp); | |
222 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
223 | ||
224 | printk(")\n"); | |
225 | } | |
226 | ||
8384ce07 SP |
227 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
228 | if (((status & OMAP3_ ##feat## _MASK) \ | |
229 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 230 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
231 | } |
232 | ||
4de34f35 | 233 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
234 | { |
235 | u32 status; | |
236 | ||
cc0170b2 | 237 | omap_features = 0; |
8384ce07 SP |
238 | |
239 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
240 | ||
241 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
242 | OMAP3_CHECK_FEATURE(status, IVA); | |
243 | OMAP3_CHECK_FEATURE(status, SGX); | |
244 | OMAP3_CHECK_FEATURE(status, NEON); | |
245 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 246 | if (cpu_is_omap3630()) |
cc0170b2 | 247 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 248 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 249 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
250 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
251 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
252 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 253 | |
cc0170b2 | 254 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 255 | |
1ce02996 MG |
256 | /* |
257 | * am35x fixups: | |
258 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
259 | * reserved and therefore return 0 when read. Unfortunately, | |
260 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
261 | * mean that a feature is present even though it isn't so clear | |
262 | * the incorrectly set feature bits. | |
263 | */ | |
264 | if (soc_is_am35xx()) | |
265 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
266 | ||
8384ce07 SP |
267 | /* |
268 | * TODO: Get additional info (where applicable) | |
269 | * e.g. Size of L2 cache. | |
270 | */ | |
4de34f35 VH |
271 | |
272 | omap3_cpuinfo(); | |
8384ce07 SP |
273 | } |
274 | ||
4de34f35 | 275 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
276 | { |
277 | u32 si_type; | |
278 | ||
42a1cc9c IK |
279 | si_type = |
280 | (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; | |
cc0170b2 | 281 | |
42a1cc9c IK |
282 | if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) |
283 | omap_features = OMAP4_HAS_PERF_SILICON; | |
cc0170b2 A |
284 | } |
285 | ||
4de34f35 | 286 | void __init ti81xx_check_features(void) |
01001712 | 287 | { |
cc0170b2 | 288 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 289 | omap3_cpuinfo(); |
01001712 HP |
290 | } |
291 | ||
4de34f35 | 292 | void __init omap3xxx_check_revision(void) |
a8823143 TL |
293 | { |
294 | u32 cpuid, idcode; | |
295 | u16 hawkeye; | |
296 | u8 rev; | |
a8823143 TL |
297 | |
298 | /* | |
299 | * We cannot access revision registers on ES1.0. | |
300 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
301 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
302 | */ | |
303 | cpuid = read_cpuid(CPUID_ID); | |
304 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 305 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 306 | cpu_rev = "1.0"; |
048f4bd7 | 307 | return; |
a8823143 TL |
308 | } |
309 | ||
310 | /* | |
311 | * Detection for 34xx ES2.0 and above can be done with just | |
312 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
313 | * Note that rev does not map directly to our defined processor | |
314 | * revision numbers as ES1.0 uses value 0. | |
315 | */ | |
316 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
317 | hawkeye = (idcode >> 12) & 0xffff; | |
318 | rev = (idcode >> 28) & 0xff; | |
097c584c | 319 | |
2456a10f NM |
320 | switch (hawkeye) { |
321 | case 0xb7ae: | |
322 | /* Handle 34xx/35xx devices */ | |
a8823143 | 323 | switch (rev) { |
048f4bd7 SP |
324 | case 0: /* Take care of early samples */ |
325 | case 1: | |
84a34344 | 326 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 327 | cpu_rev = "2.0"; |
a8823143 TL |
328 | break; |
329 | case 2: | |
84a34344 | 330 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 331 | cpu_rev = "2.1"; |
a8823143 TL |
332 | break; |
333 | case 3: | |
84a34344 | 334 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 335 | cpu_rev = "3.0"; |
a8823143 | 336 | break; |
187e688d | 337 | case 4: |
e9acb9b6 | 338 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 339 | cpu_rev = "3.1"; |
e9acb9b6 TL |
340 | break; |
341 | case 7: | |
edeae658 | 342 | /* FALLTHROUGH */ |
a8823143 TL |
343 | default: |
344 | /* Use the latest known revision as default */ | |
e9acb9b6 | 345 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 346 | cpu_rev = "3.1.2"; |
a8823143 | 347 | } |
2456a10f | 348 | break; |
4cac6018 | 349 | case 0xb868: |
1f1b0353 PW |
350 | /* |
351 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 352 | * |
1f1b0353 | 353 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
354 | * is identified later based on the features. |
355 | */ | |
9ed2ba7a PW |
356 | switch (rev) { |
357 | case 0: | |
68a88b98 | 358 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 359 | cpu_rev = "1.0"; |
9ed2ba7a PW |
360 | break; |
361 | case 1: | |
362 | /* FALLTHROUGH */ | |
363 | default: | |
68a88b98 | 364 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 365 | cpu_rev = "1.1"; |
9ed2ba7a | 366 | } |
4cac6018 | 367 | break; |
edeae658 | 368 | case 0xb891: |
b0a1a6ce | 369 | /* Handle 36xx devices */ |
b0a1a6ce AG |
370 | |
371 | switch(rev) { | |
372 | case 0: /* Take care of early samples */ | |
373 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 374 | cpu_rev = "1.0"; |
b0a1a6ce AG |
375 | break; |
376 | case 1: | |
377 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 378 | cpu_rev = "1.1"; |
b0a1a6ce AG |
379 | break; |
380 | case 2: | |
51ec811a | 381 | /* FALLTHROUGH */ |
b0a1a6ce | 382 | default: |
51ec811a | 383 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 384 | cpu_rev = "1.2"; |
b0a1a6ce | 385 | } |
77c0870c | 386 | break; |
01001712 | 387 | case 0xb81e: |
01001712 HP |
388 | switch (rev) { |
389 | case 0: | |
390 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 391 | cpu_rev = "1.0"; |
01001712 HP |
392 | break; |
393 | case 1: | |
51ec811a | 394 | /* FALLTHROUGH */ |
01001712 | 395 | default: |
51ec811a | 396 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 397 | cpu_rev = "1.1"; |
3b32b7d6 | 398 | break; |
01001712 HP |
399 | } |
400 | break; | |
1e6cb146 | 401 | case 0xb944: |
5af044f4 AC |
402 | switch (rev) { |
403 | case 0: | |
404 | omap_revision = AM335X_REV_ES1_0; | |
405 | cpu_rev = "1.0"; | |
406 | break; | |
407 | case 1: | |
408 | /* FALLTHROUGH */ | |
409 | default: | |
410 | omap_revision = AM335X_REV_ES2_0; | |
411 | cpu_rev = "2.0"; | |
412 | break; | |
413 | } | |
c2d13554 | 414 | break; |
4390f5b2 HP |
415 | case 0xb8f2: |
416 | switch (rev) { | |
417 | case 0: | |
418 | /* FALLTHROUGH */ | |
419 | case 1: | |
420 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 421 | cpu_rev = "1.0"; |
4390f5b2 HP |
422 | break; |
423 | case 2: | |
424 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 425 | cpu_rev = "2.0"; |
4390f5b2 HP |
426 | break; |
427 | case 3: | |
428 | /* FALLTHROUGH */ | |
429 | default: | |
430 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 431 | cpu_rev = "2.1"; |
4390f5b2 HP |
432 | break; |
433 | } | |
1e6cb146 | 434 | break; |
2456a10f | 435 | default: |
51ec811a | 436 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 437 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 438 | cpu_rev = "1.2"; |
51ec811a | 439 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 440 | } |
1dbae815 TL |
441 | } |
442 | ||
4de34f35 | 443 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
444 | { |
445 | u32 idcode; | |
446 | u16 hawkeye; | |
447 | u8 rev; | |
b570e0ec SS |
448 | |
449 | /* | |
450 | * The IC rev detection is done with hawkeye and rev. | |
451 | * Note that rev does not map directly to defined processor | |
452 | * revision numbers as ES1.0 uses value 0. | |
453 | */ | |
454 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
455 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 456 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 457 | |
ed6be0ba | 458 | /* |
fa54dccd | 459 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
460 | * Use ARM register to detect the correct ES version |
461 | */ | |
ec023e46 | 462 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ed6be0ba SS |
463 | idcode = read_cpuid(CPUID_ID); |
464 | rev = (idcode & 0xf) - 1; | |
465 | } | |
466 | ||
467 | switch (hawkeye) { | |
468 | case 0xb852: | |
469 | switch (rev) { | |
470 | case 0: | |
471 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
472 | break; |
473 | case 1: | |
e49c4d27 | 474 | default: |
ed6be0ba | 475 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
476 | } |
477 | break; | |
478 | case 0xb95c: | |
479 | switch (rev) { | |
480 | case 3: | |
481 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 482 | break; |
e49c4d27 | 483 | case 4: |
e49c4d27 | 484 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
485 | break; |
486 | case 6: | |
487 | default: | |
488 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
489 | } |
490 | break; | |
fa54dccd A |
491 | case 0xb94e: |
492 | switch (rev) { | |
493 | case 0: | |
fa54dccd | 494 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 495 | break; |
33ee0db5 CL |
496 | case 2: |
497 | default: | |
498 | omap_revision = OMAP4460_REV_ES1_1; | |
499 | break; | |
fa54dccd A |
500 | } |
501 | break; | |
ec023e46 LI |
502 | case 0xb975: |
503 | switch (rev) { | |
504 | case 0: | |
505 | default: | |
506 | omap_revision = OMAP4470_REV_ES1_0; | |
507 | break; | |
508 | } | |
509 | break; | |
ed6be0ba | 510 | default: |
e49c4d27 | 511 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 512 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
513 | } |
514 | ||
e49c4d27 NK |
515 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
516 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
517 | } |
518 | ||
b13e80a8 S |
519 | void __init omap5xxx_check_revision(void) |
520 | { | |
521 | u32 idcode; | |
522 | u16 hawkeye; | |
523 | u8 rev; | |
524 | ||
525 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
526 | hawkeye = (idcode >> 12) & 0xffff; | |
527 | rev = (idcode >> 28) & 0xff; | |
528 | switch (hawkeye) { | |
529 | case 0xb942: | |
530 | switch (rev) { | |
531 | case 0: | |
532 | default: | |
533 | omap_revision = OMAP5430_REV_ES1_0; | |
534 | } | |
535 | break; | |
536 | ||
537 | case 0xb998: | |
538 | switch (rev) { | |
539 | case 0: | |
540 | default: | |
541 | omap_revision = OMAP5432_REV_ES1_0; | |
542 | } | |
543 | break; | |
544 | ||
545 | default: | |
546 | /* Unknown default to latest silicon rev as default*/ | |
547 | omap_revision = OMAP5430_REV_ES1_0; | |
548 | } | |
549 | ||
550 | pr_info("OMAP%04x ES%d.0\n", | |
551 | omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); | |
552 | } | |
553 | ||
a8823143 TL |
554 | /* |
555 | * Set up things for map_io and processor detection later on. Gets called | |
556 | * pretty much first thing from board init. For multi-omap, this gets | |
557 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
558 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
559 | * is done. | |
560 | */ | |
b6a4226c | 561 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap) |
0e564848 | 562 | { |
b6a4226c PW |
563 | omap_revision = class; |
564 | tap_base = tap; | |
0e564848 | 565 | |
b6a4226c | 566 | /* XXX What is this intended to do? */ |
a8823143 | 567 | if (cpu_is_omap34xx()) |
0e564848 TL |
568 | tap_prod_id = 0x0210; |
569 | else | |
570 | tap_prod_id = 0x0208; | |
571 | } |