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4bbbc1ad JY |
1 | /* |
2 | * General-Purpose Memory Controller for OMAP2 | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __OMAP2_GPMC_H | |
12 | #define __OMAP2_GPMC_H | |
13 | ||
bc3668ea AM |
14 | #include <linux/platform_data/mtd-nand-omap2.h> |
15 | ||
fd1dc87d PW |
16 | /* Maximum Number of Chip Selects */ |
17 | #define GPMC_CS_NUM 8 | |
18 | ||
4bbbc1ad JY |
19 | #define GPMC_CS_CONFIG1 0x00 |
20 | #define GPMC_CS_CONFIG2 0x04 | |
21 | #define GPMC_CS_CONFIG3 0x08 | |
22 | #define GPMC_CS_CONFIG4 0x0c | |
23 | #define GPMC_CS_CONFIG5 0x10 | |
24 | #define GPMC_CS_CONFIG6 0x14 | |
25 | #define GPMC_CS_CONFIG7 0x18 | |
26 | #define GPMC_CS_NAND_COMMAND 0x1c | |
27 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
28 | #define GPMC_CS_NAND_DATA 0x24 | |
29 | ||
948d38e7 SG |
30 | /* Control Commands */ |
31 | #define GPMC_CONFIG_RDY_BSY 0x00000001 | |
32 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 | |
33 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 | |
34 | #define GPMC_SET_IRQ_STATUS 0x00000004 | |
35 | #define GPMC_CONFIG_WP 0x00000005 | |
36 | ||
db97eb7d SG |
37 | #define GPMC_ENABLE_IRQ 0x0000000d |
38 | ||
948d38e7 SG |
39 | /* ECC commands */ |
40 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | |
41 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | |
42 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | |
646e3ed1 | 43 | |
4bbbc1ad | 44 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) |
1c22cc13 | 45 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) |
4bbbc1ad JY |
46 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) |
47 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
1c22cc13 | 48 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) |
4bbbc1ad JY |
49 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) |
50 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
51 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
52 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | |
53 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | |
54 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
55 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | |
56 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | |
57 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
58 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
59 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | |
60 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
4bbbc1ad JY |
61 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) |
62 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
63 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
64 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
65 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
66 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
a2d3e7ba | 67 | #define GPMC_CONFIG7_CSVALID (1 << 6) |
4bbbc1ad | 68 | |
948d38e7 SG |
69 | #define GPMC_DEVICETYPE_NOR 0 |
70 | #define GPMC_DEVICETYPE_NAND 2 | |
71 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | |
948d38e7 | 72 | #define WR_RD_PIN_MONITORING 0x00600000 |
db97eb7d SG |
73 | #define GPMC_IRQ_FIFOEVENTENABLE 0x01 |
74 | #define GPMC_IRQ_COUNT_EVENT 0x02 | |
948d38e7 | 75 | |
317379a9 | 76 | |
559d94b0 AM |
77 | /* bool type time settings */ |
78 | struct gpmc_bool_timings { | |
79 | bool cycle2cyclediffcsen; | |
80 | bool cycle2cyclesamecsen; | |
81 | bool we_extra_delay; | |
82 | bool oe_extra_delay; | |
83 | bool adv_extra_delay; | |
84 | bool cs_extra_delay; | |
85 | bool time_para_granularity; | |
86 | }; | |
87 | ||
4bbbc1ad | 88 | /* |
a3551f5b AH |
89 | * Note that all values in this struct are in nanoseconds except sync_clk |
90 | * (which is in picoseconds), while the register values are in gpmc_fck cycles. | |
4bbbc1ad JY |
91 | */ |
92 | struct gpmc_timings { | |
a3551f5b AH |
93 | /* Minimum clock period for synchronous mode (in picoseconds) */ |
94 | u32 sync_clk; | |
4bbbc1ad JY |
95 | |
96 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | |
246da26d AM |
97 | u32 cs_on; /* Assertion time */ |
98 | u32 cs_rd_off; /* Read deassertion time */ | |
99 | u32 cs_wr_off; /* Write deassertion time */ | |
4bbbc1ad JY |
100 | |
101 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | |
246da26d AM |
102 | u32 adv_on; /* Assertion time */ |
103 | u32 adv_rd_off; /* Read deassertion time */ | |
104 | u32 adv_wr_off; /* Write deassertion time */ | |
4bbbc1ad JY |
105 | |
106 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | |
246da26d AM |
107 | u32 we_on; /* WE assertion time */ |
108 | u32 we_off; /* WE deassertion time */ | |
4bbbc1ad JY |
109 | |
110 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | |
246da26d AM |
111 | u32 oe_on; /* OE assertion time */ |
112 | u32 oe_off; /* OE deassertion time */ | |
4bbbc1ad JY |
113 | |
114 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | |
246da26d AM |
115 | u32 page_burst_access; /* Multiple access word delay */ |
116 | u32 access; /* Start-cycle to first data valid delay */ | |
117 | u32 rd_cycle; /* Total read cycle time */ | |
118 | u32 wr_cycle; /* Total write cycle time */ | |
cc26b3b0 | 119 | |
246da26d AM |
120 | u32 bus_turnaround; |
121 | u32 cycle2cycle_delay; | |
559d94b0 | 122 | |
246da26d AM |
123 | u32 wait_monitoring; |
124 | u32 clk_activation; | |
559d94b0 | 125 | |
cc26b3b0 | 126 | /* The following are only on OMAP3430 */ |
246da26d AM |
127 | u32 wr_access; /* WRACCESSTIME */ |
128 | u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ | |
559d94b0 AM |
129 | |
130 | struct gpmc_bool_timings bool_timings; | |
4bbbc1ad JY |
131 | }; |
132 | ||
246da26d AM |
133 | /* Device timings in picoseconds */ |
134 | struct gpmc_device_timings { | |
135 | u32 t_ceasu; /* address setup to CS valid */ | |
136 | u32 t_avdasu; /* address setup to ADV valid */ | |
137 | /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is | |
138 | * of tusb using these timings even for sync whilst | |
139 | * ideally for adv_rd/(wr)_off it should have considered | |
140 | * t_avdh instead. This indirectly necessitates r/w | |
141 | * variations of t_avdp as it is possible to have one | |
142 | * sync & other async | |
143 | */ | |
144 | u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ | |
145 | u32 t_avdp_w; | |
146 | u32 t_aavdh; /* address hold time */ | |
147 | u32 t_oeasu; /* address setup to OE valid */ | |
148 | u32 t_aa; /* access time from ADV assertion */ | |
149 | u32 t_iaa; /* initial access time */ | |
150 | u32 t_oe; /* access time from OE assertion */ | |
151 | u32 t_ce; /* access time from CS asertion */ | |
152 | u32 t_rd_cycle; /* read cycle time */ | |
153 | u32 t_cez_r; /* read CS deassertion to high Z */ | |
154 | u32 t_cez_w; /* write CS deassertion to high Z */ | |
155 | u32 t_oez; /* OE deassertion to high Z */ | |
156 | u32 t_weasu; /* address setup to WE valid */ | |
157 | u32 t_wpl; /* write assertion time */ | |
158 | u32 t_wph; /* write deassertion time */ | |
159 | u32 t_wr_cycle; /* write cycle time */ | |
160 | ||
161 | u32 clk; | |
162 | u32 t_bacc; /* burst access valid clock to output delay */ | |
163 | u32 t_ces; /* CS setup time to clk */ | |
164 | u32 t_avds; /* ADV setup time to clk */ | |
165 | u32 t_avdh; /* ADV hold time from clk */ | |
166 | u32 t_ach; /* address hold time from clk */ | |
167 | u32 t_rdyo; /* clk to ready valid */ | |
168 | ||
169 | u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ | |
170 | u32 t_ce_avd; /* CS on to ADV on delay */ | |
171 | ||
172 | /* XXX: check the possibility of combining | |
173 | * cyc_aavhd_oe & cyc_aavdh_we | |
174 | */ | |
175 | u8 cyc_aavdh_oe;/* read address hold time in cycles */ | |
176 | u8 cyc_aavdh_we;/* write address hold time in cycles */ | |
177 | u8 cyc_oe; /* access time from OE assertion in cycles */ | |
178 | u8 cyc_wpl; /* write deassertion time in cycles */ | |
179 | u32 cyc_iaa; /* initial access time in cycles */ | |
180 | ||
181 | bool mux; /* address & data muxed */ | |
182 | bool sync_write;/* synchronous write */ | |
183 | bool sync_read; /* synchronous read */ | |
184 | ||
185 | /* extra delays */ | |
186 | bool ce_xdelay; | |
187 | bool avd_xdelay; | |
188 | bool oe_xdelay; | |
189 | bool we_xdelay; | |
190 | }; | |
191 | ||
192 | extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
193 | struct gpmc_device_timings *dev_t); | |
194 | ||
52bd138d | 195 | extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); |
6b6c32fc | 196 | extern int gpmc_get_client_irq(unsigned irq_config); |
52bd138d | 197 | |
4bbbc1ad | 198 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); |
a3551f5b | 199 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); |
fd1dc87d | 200 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
23300597 KS |
201 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); |
202 | extern unsigned long gpmc_get_fclk_period(void); | |
4bbbc1ad JY |
203 | |
204 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | |
205 | extern u32 gpmc_cs_read_reg(int cs, int idx); | |
1b47ca1a | 206 | extern int gpmc_calc_divider(unsigned int sync_clk); |
4bbbc1ad | 207 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); |
f37e4580 ID |
208 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); |
209 | extern void gpmc_cs_free(int cs); | |
39b8e698 | 210 | extern int gpmc_cs_set_reserved(int cs, int reserved); |
f4e4c324 | 211 | extern int gpmc_cs_reserved(int cs); |
a2d3e7ba RN |
212 | extern void omap3_gpmc_save_context(void); |
213 | extern void omap3_gpmc_restore_context(void); | |
948d38e7 | 214 | extern int gpmc_cs_configure(int cs, int cmd, int wval); |
8d602cf5 | 215 | |
4bbbc1ad | 216 | #endif |